Freescale Semiconductor HCS08 Series, Reference Manual

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Chapter 2 Pins and Connections
MC9S08JS16 MCU Series Reference Manual, Rev. 4
Freescale Semiconductor 25
Internal power-on reset and low-voltage reset circuitry typically make external reset circuitry unnecessary.
This pin is normally connected to the standard 6-pin background debug connector so a development
system can directly reset the MCU system. If desired, a manual external reset can be added by supplying
a simple switch to ground (pull reset pin low to force a reset).
When any non-POR reset is initiated (whether from an external source or from an internal source), the
RESET pin is driven low for approximately 66 bus cycles and released. The reset circuity decodes the
cause of reset and records it by setting a corresponding bit in the system control reset status register (SRS).
NOTE
The voltage on the internally pulled up RESET pin when measured is below
V
DD
. The internal gates connected to this pin are pulled to V
DD
. If the
RESET pin is required to drive to a V
DD
level, an external pullup must be
used.
NOTE
In EMC-sensitive applications, an external RC filter is recommended on the
RESET pin, if enabled (
Figure 2-3 ).
2.3.4 Background/Mode Select (BKGD/MS)
During a power-on-reset (POR) or background debug force reset (see Section 5.7.3, “System Background
Debug Force Reset Register (SBDFR) ,” for details), the PTB2/BKGD/MS pin functions as a mode select
pin. Immediately after reset rises the pin functions as the background pin and can be used for background
debug communication. When enabled as the BKGD/MS pin (BKGDPE = 1), an internal pullup device is
automatically enabled.
The background debug communication function is enabled when BKGDPE in SOPT1 is set. BKGDPE is
set following any reset of the MCU and must be cleared to use the PTB2/BKGD/MS pin’s alternative pin
functions.
If nothing is connected to this pin, the MCU will enter normal operating mode at the rising edge of reset.
If a debug system is connected to the 6-pin standard background debug header, it can hold BKGD/MS low
during the rising edge of reset which forces the MCU to active background mode.
The BKGD pin is used primarily for background debug controller (BDC) communications using a custom
protocol that uses 16 clock cycles of the target MCU’s BDC clock per bit time. The target MCU’s BDC
clock could be as fast as the bus clock rate, so there must never be any significant capacitance connected
to the BKGD/MS pin that could interfere with background serial communications.
Although the BKGD pin is a pseudo open-drain pin, the background debug communication protocol
provides brief, actively driven, high speedup pulses to ensure fast rise times. Small capacitances from
cables and the absolute value of the internal pullup device play almost no role in determining rise and fall
times on the BKGD pin.