Freescale Semiconductor HCS08 Series, Reference Manual

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Timer/Pulse-Width Modulator (S08TPMV3)
MC9S08JS16 MCU Series Reference Manual, Rev. 4
228 Freescale Semiconductor
14.5.2 TPM-Counter Registers (TPMCNTH:TPMCNTL)
The two read-only TPM counter registers contain the high and low bytes of the value in the TPM counter.
Reading either byte (TPMCNTH or TPMCNTL) latches the contents of both bytes into a buffer where they
remain latched until the other half is read. This allows coherent 16-bit reads in either big-endian or
little-endian order which makes this more friendly to various compiler implementations. The coherency
mechanism is automatically restarted by an MCU reset or any write to the timer status/control register
(TPMSC).
Reset clears the TPM counter registers. Writing any value to TPMCNTH or TPMCNTL also clears the
TPM counter (TPMCNTH:TPMCNTL) and resets the coherency mechanism, regardless of the data
involved in the write.
Table 14-5. TPM-Clock-Source Selection
CLKSB:CLKSA TPM Clock Source to Prescaler Input
00 No clock selected (TPM counter disable)
01 Bus rate clock
10 Fixed system clock
11 External source
Table 14-6. Prescale Factor Selection
PS2:PS1:PS0 TPM Clock Source Divided-by
000 1
001 2
010 4
011 8
100 16
101 32
110 64
111 128
7 6 5 4 3 2 1 0
R Bit 15 14 13 12 11 10 9 Bit 8
W Any write to TPMCNTH clears the 16-bit counter
Reset 0 0 0 0 0 0 0 0
Figure 14-8. TPM Counter Register High (TPMCNTH)