Freescale Semiconductor HCS08 Series, Reference Manual

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Chapter 14 Timer/Pulse-Width Modulator (S08TPMV3)
MC9S08JS16 MCU Series Reference Manual, Rev. 4
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14.3 TPMV3 Differences from Previous Versions
The TPMV3 is the latest version of the Timer/PWM module that addresses errata found in previous
versions. The following section outlines the differences between TPMV3 and TPMV2 modules, and any
considerations that should be taken when porting code.
Table 14-1. TPMV2 and TPMV3 Porting Considerations
Action TPMV3 TPMV2
Write to TPMxCnTH:L registers
1
Any write to TPMCNTH or TPMCNTL registers Clears the TPM counter
(TPMCNTH:L) and the
prescaler counter. Clears the TPM counter
(TPMCNTH:L) only.
Read of TPMxCNTH:L registers
1
In BDM mode, any read of TPMCNTH:L registers Returns the value of the TPM
counter that is frozen. If only one byte of the
TPMCNTH:L registers was
read before the BDM mode
became active, returns the
latched value of TPMCNTH:L
from the read buffer (instead of
the frozen TPM counter value).
In BDM mode, a write to TPMSC, TPMCNTH or TPMCNTL Clears this read coherency
mechanism. Does not clear this read
coherency mechanism.
Read of TPMCnVH:L registers
2
In BDM mode, any read of TPMCnVH:L registers Returns the value of the
TPMCnVH:L register. If only one byte of the
TPMCnVH:L registers was
read before the BDM mode
became active, returns the
latched value of TPMCNTH:L
from the read buffer (instead of
the value in the TPMCnVH:L
registers).
In BDM mode, a write to TPMCnSC Clears this read coherency
mechanism. Does not clear this read
coherency mechanism.
Write to TPMCnVH:L registers
In Input Capture mode, writes to TPMCnVH:L registers
3
Not allowed. Allowed.
In Output Compare mode, when (CLKSB:CLKSA not = 0:0),
writes to TPMCnVH:L registers
3
Update the TPMCnVH:L
registers with the value of
their write buffer at the next
change of the TPM counter
(end of the prescaler
counting) after the second
byte is written. Always update these registers
when their second byte is
written.