Freescale Semiconductor HCS08 Series, Reference Manual

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16-Bit Serial Peripheral Interface (S08SPI16V1)
MC9S08JS16 MCU Series Reference Manual, Rev. 4
Freescale Semiconductor 209
• If a data transmission occurs in slave mode after reset without a write to SPIDH:SPIDL, it will
transmit garbage, or the data last received from the master before the reset.
• Reading from the SPIDH:SPIDL after reset will always read zeros.
13.4.9.5 Interrupts
The SPI only originates interrupt requests when the SPI is enabled (SPE bit in SPIC1 set). The following
is a description of how the SPI makes a request and how the MCU must acknowledge that request. The
interrupt vector offset and interrupt priority are chip dependent.
13.4.10 SPI Interrupts
There are four flag bits, three interrupt mask bits, and one interrupt vector associated with the SPI system.
The SPI interrupt enable mask (SPIE) enables interrupts from the SPI receiver full flag (SPRF) and mode
fault flag (MODF). The SPI transmit interrupt enable mask (SPTIE) enables interrupts from the SPI
transmit buffer empty flag (SPTEF). The SPI match interrupt enable mask bit (SPIMIE) enables interrupts
from the SPI match flag (SPMF). When one of the flag bits is set, and the associated interrupt mask bit is
set, a hardware interrupt request is sent to the CPU. If the interrupt mask bits are cleared, software can poll
the associated flag bits instead of using interrupts. The SPI interrupt service routine (ISR) must check the
flag bits to determine what event caused the interrupt. The service routine must also clear the flag bit(s)
before returning from the ISR (usually near the beginning of the ISR).
13.4.10.1 MODF
MODF occurs when the master detects an error on the SS pin. The master SPI must be configured for the
MODF feature (see
Table 13-2 ). Once MODF is set, the current transfer is aborted and the following bit is
changed:
• MSTR=0, The master bit in SPIC1 resets.
The MODF interrupt is reflected in the status register MODF flag. Clearing the flag will also clear the
interrupt. This interrupt will stay active while the MODF flag is set. MODF has an automatic clearing
process which is described in
Section 13.3.4, “SPI Status Register (SPIS) .”
13.4.10.2 SPRF
SPRF occurs when new data has been received and copied to the SPI receive data buffer. In 8-bit mode,
SPRF is set only after all 8 bits have been shifted out of the shift register and into SPIDL. In 16-bit mode,
SPRF is set only after all 16 bits have been shifted out of the shift register and into SPIDH:SPIDL.
Once SPRF is set, it does not clear until it is serviced. SPRF has an automatic clearing process which is
described in
Section 13.3.4, “SPI Status Register (SPIS) .” In the event that the SPRF is not serviced before
the end of the next transfer (i.e. SPRF remains active throughout another transfer), the latter transfers will
be ignored and no new data will be copied into the SPIDH:SPIDL.