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Freescale Semiconductor e200z3, Reference Manual

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Debug Support

e200z3 Power Architecture Core Reference Manual, Rev. 2

Freescale Semiconductor

9-7

 

Table 9-2. Debug Event Descriptions

Event Name

Type

Description

Instruction 
Address Compare 
Event

IAC

Occurs when enabled and upon attempted execution of an instruction at an address 
that meets the criteria specified in the DBCR0, DBCR1,and IAC

n registers. Instruction 

address compares may specify user/supervisor mode and instruction space 
(MSR[IS]), along with an effective address, masked effective address, or range of 
effective addresses for comparison. This event can occur and be recorded in DBSR 
regardless of the setting of MSR[DE]. IAC events do not occur when an instruction 
would not have normally begun execution due to a higher priority exception at an 
instruction boundary.
IAC compares perform a 31-bit compare for VLE instruction pages, and 30-bit 
compares for BookE instruction pages. Each half-word fetched by the instruction fetch 
unit will be marked with a set of bits indicating whether an Instruction Address 
Compare occurred on that half-word. Debug exceptions will occur if enabled and a 
16-bit instruction, or the first half-word of a 32-bit instruction, is tagged with an IAC hit. 
For instruction fetches that miss in the TLB, Book E pages are assumed, and a 30-bit 
compare is performed.

Data Address 
Compare Event

DAC

Data address compare debug events occur if data address compare debug events are 
enabled and execution of a load or store class instruction or a cache maintenance 
instruction results in a data access with an address that meets the criteria specified 
in DBCR0, DBCR2, DAC1, and DAC2. Data address compares may specify 
user/supervisor mode and data space (MSR[DS]), along with an effective address, 
masked effective address, or range of effective addresses for comparison. This event 
can occur and be recorded in DBSR regardless of the setting of MSR[DE]. Two 
address compare values (DAC1 and DAC2) are provided.

Note:

In contrast to the Book E definition, data address compare events on the core do not 
prevent the load or store instruction from completing. If a load or store class 
instruction completes successfully without a data TLB or data storage interrupt, data 
address compare exceptions are reported at the completion of the instruction. If the 
exception results in a precise debug interrupt, the address value saved in DSRR0 (or 
CSRR0 if the debug APU is disabled) is the address of the instruction following the 
load or store class instruction.
If a load or store class instruction does not complete successfully due to a data TLB 
or data storage exception, and a data address compare debug exception also occurs, 
the result is an imprecise debug interrupt, the address value saved in DSRR0 (or 
CSRR0 if the debug APU is disabled) is the address of the load or store class 
instruction, and DBSR[IDE] is set. In addition to occurring when DBCR0[IDM] = 1, this 
can also occur when DBCR0[EDM] = 1.

Note:

DAC events are not recorded or counted if an 

lmw

 or 

stmw

 instruction is interrupted 

before completion by a critical input or external input interrupt.

Note:

 • DAC events are not signaled on the following:

—The second portion of a misaligned load or store that is broken up into two 
separate accesses
—The 

tlbre

, 

tlbwe

, 

tlbsx

, or 

tlbivax

 instructions

Summary of Contents for e200z3

Page 1: ...e200z3 Power Architecture Core Reference Manual Supports e200z3 e200z335 e200z3coreRM Rev 2 06 2008 ...

Page 2: ...nductor does not convey any license under its patent rights nor the rights of others Freescale Semiconductor products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Freescale Semiconductor product could create a sit...

Page 3: ...rrupt Handling 1 9 1 5 2 Interrupt Classes 1 9 1 5 3 Interrupt Types 1 10 1 5 4 Interrupt Registers 1 10 1 6 Microarchitecture Summary 1 12 1 6 1 Instruction Unit Features 1 13 1 6 2 Integer Unit Features 1 13 1 6 3 Load Store Unit LSU Features 1 13 1 6 4 Memory Management Unit MMU Features 1 14 1 6 5 System Bus Core Complex Interface Features 1 14 1 6 6 Nexus 32 Module Features 1 14 1 7 Legacy Su...

Page 4: ... Compare Instructions 2 14 2 6 2 Count Register CTR 2 15 2 6 3 Link Register LR 2 15 2 7 SPE and SPFP APU Registers 2 16 2 7 1 Signal Processing Embedded Floating Point Status and Control Register SPEFSCR 2 16 2 7 2 Accumulator ACC 2 19 2 8 Interrupt Registers 2 19 2 8 1 Interrupt Registers Defined by Book E 2 19 2 8 1 1 Save Restore Register 0 SRR0 2 20 2 8 1 2 Save Restore Register 1 SRR1 2 20 2...

Page 5: ...l Register 2 DBCR2 2 41 2 12 3 4 Debug Control Register 3 DBCR3 2 43 2 12 3 5 Debug Control Register 4 DBCR4 e200z335 only 2 48 2 12 4 Debug Status Register DBSR 2 49 2 12 5 Debug External Resource Control Register DBERC0 2 50 2 13 Hardware Implementation Dependent Registers 2 57 2 13 1 Hardware Implementation Dependent Register 0 HID0 2 57 2 13 2 Hardware Implementation Dependent Register 1 HID1 ...

Page 6: ...3 1 3 1 3 e200z3 Floating Point Implementation 3 2 3 2 Unsupported Instructions and Instruction Forms 3 2 3 3 Optionally Supported Instructions and Instruction Forms 3 2 3 4 Implementation Specific Instructions 3 3 3 5 BookE Instruction Extensions 3 3 3 6 Memory Access Alignment Support 3 4 3 7 Memory Synchronization and Reservation Instructions 3 4 3 8 Branch Prediction 3 5 3 9 Interruption of In...

Page 7: ...t IVOR3 4 14 4 6 5 External Input Interrupt IVOR4 4 15 4 6 6 Alignment Interrupt IVOR5 4 16 4 6 7 Program Interrupt IVOR6 4 16 4 6 8 Floating Point Unavailable Interrupt IVOR7 4 17 4 6 9 System Call Interrupt IVOR8 4 18 4 6 10 Auxiliary Processor Unavailable Interrupt IVOR9 4 18 4 6 11 Decrementer Interrupt IVOR10 4 19 4 6 12 Fixed Interval Timer Interrupt IVOR11 4 19 4 6 13 Watchdog Timer Interru...

Page 8: ...try Field Summary 5 9 5 4 Software Interface and TLB Instructions 5 10 5 5 TLB Operations 5 11 5 5 1 Translation Reload 5 11 5 5 2 Reading the TLB 5 12 5 5 3 Writing the TLB 5 12 5 5 4 Searching the TLB 5 12 5 5 5 TLB Coherency Control 5 12 5 5 6 TLB Miss Exception Update 5 12 5 5 7 TLB Load on Reset 5 13 5 6 MMU Configuration and Control Registers 5 13 5 6 1 MMU Configuration Register MMUCFG 5 13...

Page 9: ... Move to from SPR Instruction Pipeline Operation 6 11 6 4 Stalls Caused by Accessing SPRs 6 13 6 5 Instruction Serialization 6 13 6 6 Interrupt Recognition and Exception Processing 6 14 6 7 Instruction Timings 6 16 6 7 1 SPE and Embedded Floating Point Instruction Timing 6 21 6 7 1 1 SPE Integer Simple Instructions Timing 6 22 6 7 1 2 SPE Load and Store Instruction Timing 6 23 6 7 1 3 SPE Complex ...

Page 10: ...re Considerations for Power Management 8 3 8 1 4 Debug Considerations for Power Management 8 3 Chapter 9 Debug Support 9 1 Introduction 9 2 9 2 Overview 9 2 9 2 1 Software Debug Facilities 9 2 9 2 1 1 PowerPC Book E Compatibility 9 3 9 2 2 Additional Debug Facilities 9 3 9 2 3 Hardware Debug Facilities 9 3 9 2 4 Sharing Debug Resources by Software Hardware in e200z335 9 4 9 2 4 1 Simultaneous Hard...

Page 11: ...ebug 9 34 9 8 Cache Array Access During Debug 9 34 9 9 Enabling Using and Exiting External Debug Mode Example 9 34 Chapter 10 Nexus3 Nexus2 Module 10 1 Introduction 10 2 10 1 1 General Description 10 2 10 1 2 Terms and Definitions 10 2 10 1 3 Feature List 10 3 10 2 Enabling Nexus3 Operation 10 6 10 3 TCODEs Supported 10 7 10 4 Nexus3 Nexus2 Programmer s Model 10 11 10 4 1 Client Select Control Reg...

Page 12: ... Debug Status Messages 10 30 10 7 2 6 Program Correlation Messages 10 30 10 7 2 7 BTM Overflow Error Messages 10 31 10 7 2 8 Program Trace Synchronization Messages 10 32 10 7 3 BTM Operation 10 34 10 7 3 1 Enabling Program Trace 10 34 10 7 3 2 Relative Addressing 10 34 10 7 3 3 Execution Mode Indication 10 35 10 7 3 4 Branch Predicate Instruction History HIST 10 35 10 7 3 5 Sequential Instruction ...

Page 13: ...Mode 10 47 10 10 4 Single Read Access 10 47 10 10 5 Block Read Access Non Burst Mode 10 48 10 10 6 Block Read Access Burst Mode 10 48 10 10 7 Error Handling 10 49 10 10 7 1 AHB Read Write Error 10 49 10 10 7 2 Access Termination 10 49 10 10 7 3 Read Write Access Error Message 10 50 10 11 Nexus3 Nexus2 Pin Interface 10 50 10 11 1 Pins Implemented 10 50 10 11 2 Pin Protocol 10 52 10 12 Rules for Out...

Page 14: ...e200z3 Power Architecture Core Reference Manual Rev 2 xiv Freescale Semiconductor Contents Paragraph Number Title Page Number ...

Page 15: ...2 14 Critical Save Restore Register 1 CSRR1 2 20 2 15 Data Exception Address Register DEAR 2 20 2 16 Interrupt Vector Prefix Register IVPR 2 21 2 17 Interrupt Vector Offset Registers IVOR 2 21 2 18 Exception Syndrome Register ESR 2 23 2 19 Debug Save Restore Register 0 DSRR0 2 25 2 20 Debug Save Restore Register 1 DSRR1 2 25 2 21 Machine Check Syndrome Register MCSR 2 26 2 22 Software Use SPRs SPR...

Page 16: ...0 2 52 Context Control Register CTXCR 2 61 2 53 Parallel Signature Control Register PSCR 2 68 2 54 Parallel Signature Status Register PSSR 2 69 2 55 Parallel Signature High Register PSHR 2 70 2 56 Parallel Signature Low Register PSLR 2 70 2 57 Parallel Signature Counter Register PSCTR 2 70 2 58 Parallel Signature Update High Register PSUHR 2 71 2 59 Parallel Signature Update Low Register PSULR 2 7...

Page 17: ...ing 7 32 7 4 Read with Wait State Single Cycle Reads Full Pipelining 7 33 7 5 Basic Write Transfers Single Cycle Writes Full Pipelining 7 34 7 6 Write with Wait state Single Cycle Writes Full Pipelining 7 35 7 7 Single Cycle Reads Single Cycle Write Full Pipelining 7 36 7 8 Single Cycle Read Write Read Full Pipelining 7 37 7 9 Multiple Cycle Reads with Wait State Single Cycle Writes Full Pipelinin...

Page 18: ...D 9 18 9 7 OnCE Control Register 9 20 9 8 CPU Scan Chain Register CPUSCR 9 25 9 9 Control State Register CTL 9 26 9 10 OnCE PC FIFO 9 30 10 1 Nexus3 Functional Block Diagram 10 4 10 2 Client Select Control Register 10 10 10 3 Port Configuration Register 10 11 10 4 Development Control Register 1 DC1 10 12 10 5 Development Control Register 2 DC2 10 13 10 6 Development Status Register DS 10 14 10 7 R...

Page 19: ...ct Branch Message History 10 33 10 29 Program Trace Direct Branch Traditional and Error Messages 10 33 10 30 Program Trace Indirect Branch with Synchronization Message 10 34 10 31 Data Write Message Format 10 35 10 32 Data Read Message Format 10 35 10 33 Error Message Format 10 36 10 34 Data Write Read with Synchronization Message Format 10 36 10 35 Data Trace Data Write Message 10 39 10 36 Data T...

Page 20: ...e200z3 Power Architecture Core Reference Manual Rev 2 6 Freescale Semiconductor Figures Figure Number Title Page Number ...

Page 21: ...ield Descriptions 2 26 2 15 TCR Field Descriptions 2 29 2 16 Timer Status Register Field Descriptions 2 30 2 17 DBCR0 Field Descriptions 2 36 2 18 DBCR1 Field Descriptions 2 38 2 19 DBCR2 Field Descriptions 2 40 2 20 DBCR3 Field Descriptions 2 43 2 21 DBSR Field Descriptions 2 47 2 22 HID0 Field Descriptions 2 49 2 23 HID1 Field Descriptions 2 51 2 24 Branch Unit Control and Status Register 2 52 2...

Page 22: ...2 Instructions Sorted by Opcode 3 29 3 13 Full Instruction Listing 3 40 4 1 Interrupt Classifications 4 2 4 2 Exceptions and Conditions 4 3 4 3 ESR Field Descriptions 4 4 4 4 MSR Field Descriptions 4 6 4 5 MCSR Field Descriptions 4 7 4 6 IVPR Field Descriptions 4 8 4 7 IVOR Register Fields 4 9 4 8 IVOR Assignments 4 9 4 9 Critical Input Interrupt Register Settings 4 10 4 10 Machine Check Interrupt...

Page 23: ...r Simple Instructions 6 22 6 5 SPE Load and Store Instruction Timing 6 23 6 6 SPE Complex Integer Instruction Timing 6 24 6 7 SPE Vector Floating Point Instruction Timing 6 28 6 8 Scalar SPE Floating Point Instruction Timing 6 29 6 9 Performance Effects of Storage Operand Placement 6 30 7 1 Interface Signal Definitions 7 4 7 2 Processor Clock Signal Description 7 7 7 3 Descriptions of Signals Rela...

Page 24: ...face Signals 9 13 9 4 OnCE Internal Interface Signals 9 14 9 5 OnCE Interface Signals 9 15 9 6 OSR Field Descriptions 9 17 9 7 OCMD Field Descriptions 9 18 9 8 OnCE Control Register Bit Definitions 9 20 9 9 OnCE Register Access Requirements 9 22 9 10 Methods for Entering Debug Mode 9 24 9 11 CTL Field Definitions 9 26 9 12 Watchpoint Output Signal Assignments 9 31 10 1 Terms and Definitions 10 1 1...

Page 25: ...ite Access Field Settings 10 42 10 29 Single Read Access Parameter Settings 10 44 10 30 JTAG Pins for Nexus3 10 47 10 31 Nexus3 Auxiliary Pins 10 47 10 32 Nexus Port Arbitration Signals 10 48 10 33 MSEO Pin s Protocol 10 48 10 34 MDO Request Encodings 10 51 10 35 Indirect Branch Message Example 2 MDO 1 MSEO 10 52 10 36 Indirect Branch Message Example 8 MDO 2 MSEO 10 52 10 37 Direct Branch Message ...

Page 26: ...e200z3 Power Architecture Core Reference Manual Rev 2 6 Freescale Semiconductor Tables Table Number Title Page Number ...

Page 27: ...nd the operating environment architecture OEA Because the operating system resources such as the MMU and interrupts defined by Book E differ greatly from those defined by the AIM architecture Book E introduces many new registers and instructions Freescale Book E implementation standards EIS In many cases the Book E architecture definition provides a general framework leaving specific details up to...

Page 28: ...at indicate latency and throughput for each of the instructions supported by the e200z3 Chapter 7 External Core Complex Interfaces describes those aspects of the CCB that are configurable or that provide status information through the programming interface It provides a glossary of signals mentioned throughout the book to offer a clearer understanding of how the core is integrated as part of a lar...

Page 29: ...rocessors have follow on parts an addendum is provided that describes the additional features and functionality changes These addenda are intended for use with the corresponding reference manuals Hardware specifications Hardware specifications provide specific data regarding bus timing signal behavior and AC DC and thermal characteristics as well as other design considerations Product briefs Each ...

Page 30: ...minology Conventions Table i lists certain terms used in this manual that differ from the architecture terminology conventions Acronyms and Abbreviations Table ii contains acronyms and abbreviations that are used in this document Table i Terminology Conventions Architecture Specification This Manual Change bit Changed bit Extended mnemonics Simplified mnemonics Out of order memory accesses Specula...

Page 31: ...nagement unit MSB Most significant byte msb Most significant bit MSR Machine state register NaN Not a number NIA Next instruction address No op No operation PTE Page table entry RISC Reduced instruction set computing RTL Register transfer language SIMM Signed immediate value SPR Special purpose register TLB Translation lookaside buffer UIMM Unsigned immediate value UISA User instruction set archit...

Page 32: ...e200z3 Power Architecture Core Reference Manual Rev 2 xii Freescale Semiconductor ...

Page 33: ... Apple IBM and Freescale referred to as the AIM version of the PowerPC architecture Information regarding e200z3 and e200z335 features defined by the Freescale Book E implementation standards EIS 1 1 Overview of the e200z3 and e200z335 The e200z3 and e200z335 processor family is a set of CPU cores that are low cost implementations of Power Architecture technology for embedded processors e200z3 and...

Page 34: ...Additional Features OnCe Nexus 1 Nexus 3 control logic AMBA AHB Lite bus SPE SIMD VLE Embedded scalar vector floating point Power management Timebase decrementer counter Clock multiplier L1 Unified MMU Unit CTR LR Single instruction in order dispatch Single Instruction In Order Write Back 16 Entry Fully Associative TLB EA Calc Four cycle single path execute stage with overlapped execution and Fetc...

Page 35: ...e is integrated in the e200z335 The e200z3 platform is specified in such a way that functional units can be added or removed The e200z3 can be configured with a powerful vectored interrupt controller and one or more IP slave interfaces as well as support for configured memory units Instruction Bus Interface Unit Software Managed Unified Memory Unit MAS Registers 32 GPRs 64 Bit XER CR 4 Kbyte to 4 ...

Page 36: ...tegory supporting integer operations using both halves of the 64 bit GPRs Single precision embedded scalar floating point category Single precision embedded vector floating point category that uses both halves of the 64 bit GPRs Nexus Class 3 class 2 in the e200z335 real time development unit Power management Low power design extensive clock gating Power saving modes doze nap sleep Dynamic power m...

Page 37: ...ng which registers are accessible in supervisor mode and which are accessible in user mode The number to the left of the special purpose registers SPRs is the decimal number used in the instruction syntax to access the register For example the integer exception register XER is SPR 1 GPRs are accessed through instruction operands Access to other registers can be explicit by using instructions for t...

Page 38: ...1 Processor version register spr 528 IVOR323 Interrupt vector offset registers 32 34 spr 287 PVR spr 59 CSRR1 spr 529 IVOR333 spr 574 DSRR03 Debug interrupt SRR 0 1 spr 530 IVOR343 Timer Decrementer Registers spr 575 DSRR13 Exception syndrome register spr 22 DEC Decrementer spr 62 ESR MMU Control and Status Read Write Decrementer auto reload register MMU control and status register 0 spr 54 DECAR ...

Page 39: ...oating point categories provide single precision scalar and vector floating point instructions Scalar floating point instructions use only the lower 32 bits of the GPRs for single precision floating point calculations Table 1 1 lists embedded floating point instructions Wait category in the e200z335 only This category consists of the wait instruction that allows software to cease all synchronous a...

Page 40: ...loating Point Absolute Value efsabs evfsabs rD rA Floating Point Add efsadd evfsadd rD rA rB Floating Point Compare Equal efscmpeq evfscmpeq crD rA rB Floating Point Compare Greater Than efscmpgt evfscmpgt crD rA rB Floating Point Compare Less Than efscmplt evfscmplt crD rA rB Floating Point Divide efsdiv evfsdiv rD rA rB Floating Point Multiply efsmul evfsmul rD rA rB Floating Point Negate efsneg...

Page 41: ...at are independent of instruction execution For asynchronous interrupts the address reported in a save restore register is the address of the instruction that would have executed next had the asynchronous interrupt not occurred Synchronous interrupts are those that are caused directly by the execution or attempted execution of instructions Synchronous inputs are further divided into precise and im...

Page 42: ... portion of the architecture They use the save and restore registers SRR0 SRR1 to save state when they are taken and they use the rfi instruction to restore state Asynchronous noncritical interrupts can be masked by the external interrupt enable bit MSR EE 3 Critical interrupts Critical interrupts can be taken during a noncritical interrupt or during regular program flow They use the critical save...

Page 43: ...achine check syndrome register Saves machine check syndrome information on machine check interrupts ESR Exception syndrome register Provides a syndrome to differentiate among the different kinds of exceptions that generate the same interrupt type Upon generation of a specific exception type the associated bits are set and all other bits are cleared SPE Interrupt Registers SPEFSCR Signal processing...

Page 44: ...xecute in a single cycle Branches with successful target prefetching that are not folded have an effective execution time of 1 cycle All other taken branches have an execution time of 2 clocks Memory load and store operations are provided for byte half word word 32 bit and double word data with automatic zero or sign extension of byte and half word load data as well as optional byte reversal of da...

Page 45: ...program counter incrementer supporting instruction fetches Branch processing unit with dedicated branch address adder and branch target buffer BTB supporting single cycle execution of successfully predicted branches Target instruction buffer that holds up to two prefetched branch target instructions 1 6 2 Integer Unit Features The integer unit supports single cycle execution of most integer instru...

Page 46: ...Instruction interface has 64 bit read data bus Data interface has separate unidirectional 64 bit read data bus and 64 bit write data bus Pipelined in order accesses for both buses 1 6 6 Nexus 32 Module Features The Nexus 3 Nexus 2 in e200z335 module provides real time development capabilities for e200z3 and e200z335 processors in compliance with the IEEE ISTO Nexus 5001 2003 standard This module p...

Page 47: ... instructions are not implemented on the e200z3 core therefore trap emulation must be provided to ensure backward compatibility 1 7 1 2 Supervisor Instruction Set The supervisor mode instruction set in the original PowerPC architecture is compatible with the e200z3 core with the following exceptions The MMU architecture is different so some TLB manipulation instructions have different semantics In...

Page 48: ...apabilities of the e200z3 core can be found in Section 1 5 Interrupts and Exception Handling 1 7 4 Memory Management The e200z3 core implements a straightforward virtual address space that complies with the Power ISA MMU definition which eliminates segment registers and block address translation resources The Power ISA defines resources for multiple variable page sizes that can be configured in a ...

Page 49: ...tween memory and registers with explicit load and store instructions only The e200z3 extends the general purpose registers GPRs to 64 bits to support SPE APU operations PowerPC Book E instructions operate on the lower 32 bits of the GPRs only and the upper 32 bits are unaffected by these instructions SPE vector instructions operate on the entire 64 bit register The SPE APU defines load and store i...

Page 50: ...Register Model e200z3 Power Architecture Core Reference Manual Rev 2 2 2 Freescale Semiconductor ...

Page 51: ...egisters 32 34 spr 287 PVR spr 59 CSRR1 spr 529 IVOR333 spr 574 DSRR03 Debug interrupt SRR 0 1 spr 530 IVOR343 Timer Decrementer Registers spr 575 DSRR13 Exception syndrome register spr 22 DEC Decrementer spr 62 ESR MMU Control and Status Read Write Decrementer auto reload register MMU control and status register 0 spr 54 DECAR spr 572 MCSR3 Machine check syndrome register spr 1012 MMUCSR03 spr 28...

Page 52: ...the instruction that follows a branch and link instruction typically for linking to subroutines Count register CTR Holds a loop count that can be decremented during execution of appropriately coded branch instructions CTR also provides the branch target address for the branch conditional to count register bcctr bcctrl instructions The time base facility TB consists of two 32 bit registers time bas...

Page 53: ... interrupt vector offset registers IVORs Provide the address of the interrupt handler for different classes of interrupts Save restore register 0 SRR0 Saves machine state on a non critical interrupt and contains the address of the instruction at which execution resumes when an rfi instruction executes at the end of a non critical class interrupt handler routine Save restore register 1 SRR1 Saves m...

Page 54: ...r compliance with the IEEE 754 standard L1 cache configuration register L1CFG0 A read only register that allows software to query the configuration of the L1 cache For the e200z3 this register returns all zeros The EIS defined accumulator which is part of the SPE APU See Section 2 7 2 Accumulator ACC Supervisor level registers which are defined in the e200z3 in addition to the Book E registers des...

Page 55: ...ster SVR A read only register that identifies the version model and revision level of the system that includes an e200z3 processor NOTE Although other processors may implement similar or identical registers it is not guaranteed that the implementation of e200z3 core specific registers is consistent among PowerPC processors All e200z3 SPR definitions comply with the Freescale Book E definitions 2 3...

Page 56: ...n additional conditions are present The mode chosen is determined by HID0 DOZE NAP SLEEP described in Section 2 13 1 Hardware Implementation Dependent Register 0 HID0 46 CE Critical interrupt enable 0 Critical input and watchdog timer interrupts are disabled 1 Critical input and watchdog timer interrupts are enabled 47 Preserved 48 EE External interrupt enable 0 External input decrementer and fixe...

Page 57: ...eserved should be cleared 58 IS Instruction address space 0 The processor directs all instruction fetches to address space 0 TS 0 in the relevant TLB entry 1 The processor directs all instruction fetches to address space 1 TS 1 in the relevant TLB entry 59 DS Data address space 0 The core directs all data storage accesses to address space 0 TS 0 in the relevant TLB entry 1 The core directs all dat...

Page 58: ...n the p_cpuid 0 7 input signals 32 35 36 37 38 43 44 47 48 55 56 59 60 63 Field Manufacturer ID Type Version MBG Use Major Rev MBG ID Reset 1000 00 01_0001 0010 p_pvrin 16 31 R W Read only SPR SPR 287 Figure 2 4 Processor Version Register PVR Table 2 3 PVR Field Descriptions Bits Name Description 32 35 Manufacturer ID Manufacturer ID Freescale is 0b1000 36 37 Reserved should be cleared 38 43 Type ...

Page 59: ...address and integer data although all instructions except SPE APU vector instructions use and return 32 bit values in GPR bits 32 63 2 5 2 Integer Exception Register XER The XER shown in Figure 2 6 tracks exception conditions for integer operations XER fields are described in Table 2 5 32 63 Field Version Reset SoC dependent value determined by p_sysvers 0 31 on the e200z3 core R W Read only SPR S...

Page 60: ...he values 0 for SO and 1 for OV clears SO and sets OV 33 OV Overflow X form add subtract from and negate instructions with OE 1 set OV if the carry out of bit 32 is not equal to the carry out of bit 33 Otherwise they clear OV to indicate a signed overflow X form multiply low word and divide word instructions with OE 1 set OV if the result cannot be represented in 32 bits mullwo divwo and divwuo an...

Page 61: ...nd SPFP compare and test instructions Set if the low order element of rA is equal to the low order element of rB cleared otherwise CR1 2 38 00110 Zero EQ For SPE and SPFP compare and test instructions Set to the OR of the result of the compare of the high and low elements CR1 3 39 00111 Summary overflow SO For SPE and SPFP compare and test instructions Set to the AND of the result of the compare o...

Page 62: ...tore conditional instruction stwcx See instruction descriptions in Chapter 3 Instruction Model for details on how CR0 is set 2 6 1 3 CR Setting for Compare Instructions For compare instructions a CR field specified by the BI field in the instruction is set to reflect the result of the comparison as shown in Table 2 8 A complete description of how the bits are set is given in the EREF Table 2 7 CR0...

Page 63: ...t 4 cr5 gt 4 cr6 gt 4 cr7 gt 33 37 41 45 49 53 57 61 000 001 010 011 100 101 110 111 01 Greater than GT For integer compare instructions rA SIMM or rB signed comparison or rA UIMM or rB unsigned comparison CRn 2 4 cr0 eq or eq 4 cr1 eq 4 cr2 eq 4 cr3 eq 4 cr4 eq 4 cr5 eq 4 cr6 eq 4 cr7 eq 34 38 42 46 50 54 58 62 000 001 010 011 100 101 110 111 10 Equal EQ For integer compare instructions rA SIMM U...

Page 64: ...ol Register SPEFSCR SPEFSCR shown in Figure 2 10 is used for status and control of SPE and embedded floating point instructions 32 63 Field Link address Reset Undefined on m_por assertion unchanged on p_reset_b assertion R W R W SPR SPR 8 Figure 2 9 Link Register LR 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 Field SOVH OVH FGH FXH FINVH FDBZH FUNFH FOVFH FINXS FINVS FDBZS FUNFS FOVFS MODE Res...

Page 65: ...floating point instruction 38 FUNFH Embedded floating point underflow high Set when the execution of a floating point instruction results in an underflow in the high element FUNFH is cleared by a scalar floating point instruction 39 FOVFH Embedded floating point overflow high Set when the execution of a floating point instruction results in an overflow in the high element Cleared by a scalar float...

Page 66: ...EEE754 invalid operation IEEE754 1985 sec7 1 in the low element 53 FDBZ Embedded floating point divide by zero Set when a floating point divide instruction executes with a low element divisor of 0 and the low element dividend is a finite non zero number 54 FUNF Embedded floating point underflow Set when the execution of a floating point instruction results in an underflow in the low element 55 FOV...

Page 67: ...the registers for interrupt handling 2 8 1 Interrupt Registers Defined by Book E This section describes the following registers and their fields Section 2 8 1 1 Save Restore Register 0 SRR0 Section 2 8 1 2 Save Restore Register 1 SRR1 Section 2 8 1 3 Critical Save Restore Register 0 CSRR0 Section 2 8 1 4 Critical Save Restore Register 1 CSRR1 Section 2 8 1 5 Data Exception Address Register DEAR Se...

Page 68: ...See Section 2 4 1 Machine State Register MSR SRR0 and SRR1 are not affected by rfci or rfdi Reserved MSR bits can be altered by rfi rfci or rfdi 2 8 1 3 Critical Save Restore Register 0 CSRR0 CSRR0 is used to save and restore machine state during critical interrupts in the same way SRR0 is used for non critical interrupts to hold the address of the instruction to which control is passed at the end...

Page 69: ... alignment data TLB miss or data storage interrupt 2 8 1 6 Interrupt Vector Prefix Register IVPR The IVPR shown in Figure 2 16 is used during interrupt processing to determine the starting address for the software interrupt handler The value contained in the vector offset field of the IVOR selected for a particular interrupt type is concatenated with the value in the IVPR to form an instruction ad...

Page 70: ...ers IVPR IVORn values are concatenated to form the address of the handler in memory 48 63 Reserved should be cleared 32 47 48 59 60 61 63 Field Vector offset CS Reset Undefined on m_por assertion unchanged on p_reset_b assertion R W R W SPR See Table 2 12 Figure 2 17 Interrupt Vector Offset Registers IVOR Table 2 11 IVOR Field Descriptions Bits Name Setting Description 32 47 Reserved should be cle...

Page 71: ...signments IVOR Number SPR Interrupt Type IVOR0 400 Critical input IVOR1 401 Machine check IVOR2 402 Data storage IVOR3 403 Instruction storage IVOR4 404 External input IVOR5 405 Alignment IVOR6 406 Program IVOR7 407 Floating point unavailable IVOR8 408 System call IVOR9 409 Auxiliary processor unavailable Defined by the EIS but not supported in the e200z3 IVOR10 410 Decrementer IVOR11 411 Fixed in...

Page 72: ...PE VLEMI MIF XTE Reset All zeros R W R W SPR SPR 62 Table 2 13 ESR Field Descriptions Bits Name Description Associated Interrupt Type 32 35 Reserved should be cleared 36 PIL Illegal instruction exception Program 37 PPR Privileged instruction exception Program 38 PTR Trap exception Program 39 FP Floating point operation Alignment data storage data TLB program 40 ST Store operation Alignment data st...

Page 73: ... also indicates an Instruction TLB Interrupt caused by a TLB miss on the second half of a misaligned 32 bit VLE Instruction SRR0 points to the first half of the instruction which resides on the previous page from the miss at page offset 0xFFE The ITLB handler may need to note that the miss corresponds to the next page although MMU MAS2 contents correctly reflect the page corresponding to the miss ...

Page 74: ...ister 1 DSRR1 DSRR1 shown in Figure 2 20 saves and restores machine state during debug interrupts MSR contents are placed into DSRR1 When rfdi executes the contents of DSRR1 are restored into MSR DSRR1 bits that correspond to reserved MSR bits are also reserved See Section 2 4 1 Machine State Register MSR DSRR0 and DSRR1 are not affected by rfi or rfci Reserved MSR bits can be altered by rfi rfci ...

Page 75: ...G0 Accessible in supervisor or user mode 32 33 34 35 36 37 42 43 44 58 59 60 61 62 63 Field MCP CP_PERR CPERR EXCP_ERR NMI1 1 NMI bit in e200z335 only BUS_IRERR BUS_DRERR BUS_WRERR Reset All zeros R W R W SPR SPR 572 Figure 2 21 Machine Check Syndrome Register MCSR Table 2 14 MCSR Field Descriptions Bits Name Description Recoverable 32 MCP Machine check input signal Maybe 33 Reserved should be cle...

Page 76: ...sor 1 User mode access to SPRG3 is defined by Book E as implementation dependent It is not supported in the e200z3 275 Read Write Supervisor SPRG4 260 Read only User Supervisor 276 Read Write Supervisor SPRG5 261 Read only User Supervisor 277 Read Write Supervisor SPRG6 262 Read only User Supervisor 278 Read Write Supervisor SPRG7 263 Read only User Supervisor 279 Read Write Supervisor USPRG0 256 ...

Page 77: ...t transitions from 0 to 1 It typically triggers periodic system maintenance functions Bits that can be selected are implementation dependent The watchdog timer also a selected TB bit signals a critical exception when the selected bit transitions from 0 to 1 It is typically used for system error recovery If software does not respond in time to the initial interrupt by clearing the associated status...

Page 78: ...ut of the watchdog timer 10 Assert processor reset output p_resetout_b on second time out of watchdog timer 11 Reserved 36 WIE Watchdog timer interrupt enable 0 Watchdog timer interrupts disabled 1 Watchdog timer interrupts enabled 37 DIE Decrementer interrupt enable 0 Decrementer interrupts disabled 1 Decrementer interrupts enabled 38 39 FP Fixed interval timer period When concatenated with FPEXT...

Page 79: ... MSR CE To avoid another watchdog timer interrupt when MSR CE is reenabled assuming TCR WIE is not cleared instead the interrupt handler must reset TSR WIS by executing an mtspr setting WIS and any other bits to be cleared and a 0 in all other bits The data written to the TSR is not direct data but is a mask A 1 causes the bit to be cleared a 0 has no effect 0 Action on next watchdog timer time ou...

Page 80: ...m the TB has no effect on the accuracy of the TB Storing a GPR to the TB replaces the value in the TB with the value in the GPR Book E does not specify a relationship between the TB update frequency and other frequencies such as the CPU clock or bus clock The TB update frequency does not have to be constant One of the following is required to ensure that system software can keep time of day and op...

Page 81: ...TBCLK It provides way to signal a decrementer interrupt after a specified period unless one of the following occurs Software alters DEC in the interim The TB update frequency changes DEC is typically used as a general purpose software timer The decrementer auto reload register DECAR automatically reloads a programmed value into DEC 2 11 5 Decrementer Auto Reload Register DECAR If the auto reload f...

Page 82: ...ch compare modes are selected NOTE During instruction address comparisons the low order two address bits of the instruction address and the corresponding IAC register are ignored Data address compare registers DAC1 and DAC2 hold data access addresses for comparison In addition DAC2 holds mask information for DAC1 when address bit match compare mode is selected 2 12 1 1 Instruction Address Compare ...

Page 83: ...byte of the register labeled B7 in Figure 2 31 corresponds to byte offset 7 When enabled for performing data value comparisons each enabled byte in DVCn is compared with the memory value transferred on the corresponding active byte lane of the data memory interface to determine if a match occurs Inactive byte lanes do not participate in the comparison they are implicitly masked Software must also ...

Page 84: ...ied when one or more counters are enabled 2 12 3 Debug Control and Status Registers DBCR0 DBCR3 DBCR0 DBCR3 enable debug events reset the processor control timer operation during debug events and set the debug mode of the processor The debug status register DBSR records debug exceptions while internal or external debug mode is enabled To ensure that any alterations enabling disabling debug events ...

Page 85: ...ort 0 External debug mode is disabled Internal debug events not mapped into external debug events 1 External debug mode is enabled Events do not cause the CPU to vector to interrupt code Software is not permitted to write to debug registers DBCR0 DBCR3 DBSR DBCNT IAC1 IAC4 DAC1 DAC2 unless permitted by settings in DBERC0 Note DBSR status bits should be cleared before external debug mode is disable...

Page 86: ... compare 1 debug event enable 00 DAC1 debug events are disabled 01 DAC1 debug events are enabled only for store type data storage accesses 10 DAC1 debug events are enabled only for load type data storage accesses 11 DAC1 debug events are enabled for load type or store type data storage accesses 46 47 DAC2 Data address compare 2 debug event enable 00 DAC2 debug events are disabled 01 DAC2 debug eve...

Page 87: ...DAC debug event occurred on a VLE instruction Undefined for IRPT CIRPT DEVT 1 2 DCNT 1 2 and UDE events 60 62 Reserved 63 FT Freeze timers on debug event 0 Timebase timers are unaffected by set DBSR bits 1 Disable clocking of timebase timers if any DBSR bit is set except MRR or CNT1TRG 32 33 34 35 36 37 38 39 40 41 42 47 48 49 50 51 52 53 54 55 56 57 58 63 Field IAC1US IAC1ER IAC2US IAC2ER IAC12M ...

Page 88: ...act address compare IAC1 debug events can occur only if the address of the instruction fetch is equal to the value specified in IAC1 IAC2 debug events can occur only if the address of the instruction fetch is equal to the value specified in IAC2 01 Address bit match IAC1 debug events can occur only if the address of the instruction fetch ANDed with the contents of IAC2 is equal to the contents of ...

Page 89: ... in IAC4 01 Address bit match IAC3 debug events can occur only if the address of the instruction fetch ANDed with the contents of IAC4 is equal to the contents of IAC3 also ANDed with the contents of IAC4 IAC4 debug events do not occur IAC3US and IAC3ER settings are used 10 Inclusive address range compare IAC3 debug events can occur only if the address of the instruction fetch is greater than or e...

Page 90: ...he data access is equal to the value specified in DAC1 DAC2 debug events can occur only if the address of the data access is equal to the value specified in DAC2 01 Address bit match DAC1 debug events can occur only if the address of the data access ANDed with the contents of DAC2 is equal to the contents of DAC1 also ANDed with the contents of DAC2 DAC2 debug events do not occur DAC1US and DAC1ER...

Page 91: ...ter 2 or as a combined 32 bit counter using control bits in DBCR3 for counter 1 Counters are enabled when any of their respective count enable event control bits are set and either DBCR0 or DBCR0 EDM is set Counter 1 can be configured to count down on a number of different debug events Counter 2 is also configurable to count down on instruction complete instruction or data address compare events a...

Page 92: ...tion with the IAC and perhaps several additional instructions proceeds down the execution pipeline The instruction boundary where the debug exception is actually generated typically follows the IAC by up to several instructions Note that the counters operate regardless of whether counters are enabled to generate debug exceptions If counter 2 is used to trigger counter 1 counter 2 events should not...

Page 93: ... is disabled 1 Counting IAC3 debug events by counter 1 is enabled 38 IAC4C1 Instruction address compare 4 debug event count 1 enable 0 Counting IAC4 debug events by counter 1 is disabled 1 Counting IAC4 debug events by counter 1 is enabled 39 DAC1RC1 Data address compare 1 read debug event count 1 enable1 0 Counting DAC1R debug events by counter 1 is disabled 1 Counting DAC1R debug events by count...

Page 94: ...led 1 Counting IAC4 debug events by counter 2 is enabled 52 DAC1RC2 Data address compare 1 read debug event count 2 enable 1 0 Counting DAC1R debug events by counter 2 is disabled 1 Counting DAC1R debug events by counter 2 is enabled 53 DAC1WC2 Data address compare 1 write debug event count 2 enable 1 0 Counting DAC1W debug events by counter 2 is disabled 1 Counting DAC1W debug events by counter 2...

Page 95: ... no possibility of a counter related debug event on the mtspr For DBCR3 if a counter is enabled to count ICMP events MSR DE 1 and the counter value is 1 before execution of an mtspr that is loading DBCR3 with a different value a counter event may be generated after the mtspr completes even though DBCR3 is loaded with a value that prevents the particular event from being counted When the mtspr fini...

Page 96: ...reset_b if DBCR0 EDM 0 as well as unconditionally by m_por If DBCR0 EDM 1 DBERC0 masks off hardware owned resources from reset by p_reset_b and only software owned resources indicated by DBERC0 will be reset by p_reset_b Figure 2 37 DBCR4 Register Table 2 21 DBCR4 Bit Definitions Bit s Name Description 17 20 Reserved 0 DVC1C Data Value Compare 1 Control 0 Normal DVC1 operation 1 Inverted polarity ...

Page 97: ...2 provides field definitions for the debug status register 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 Field IDE UDE MRR ICMP BRT IRPT TRAP IAC1 IAC2 IAC3 IAC4 DAC1R DAC1W DAC2R DAC2W Reset 0001_0000_0000_0000 R W Read Clear 48 49 52 53 54 55 56 57 58 59 61 62 63 Field RET DEVT1 DEVT2 DCNT1 DCNT2 CIRPT CRET DAC_OFST CNT1TRG Reset 0000_0000_0000_0000 R W Read Clear SPR SPR 304 Figure 2 38 DBSR ...

Page 98: ... DAC1 0b11 45 DAC1W Data address compare 1 write debug event Set if a write type DAC1 debug event occurs while DBCR0 DAC1 0b01 or DBCR0 DAC1 0b11 46 DAC2R Data address compare 2 read debug event Set if a read type DAC2 debug event occurs while DBCR0 DAC2 0b10 or DBCR0 DAC2 0b11 47 DAC2W Data address compare 2 write debug event Set if a write type DAC2 debug event occurs while DBCR0 DAC2 0b01 or DB...

Page 99: ...by execution of a mtspr thus only a portion of these registers may be affected depending on the allocation settings in DBERC0 The debug interrupt handler is still responsible for clearing software owned DBSR bits prior to returning to normal execution Hardware always has full access to all registers and all register fields through the OnCE register access mechanism and it is up to the debug firmwa...

Page 100: ...wned exclusively by hardware debug No mtspr access by software to DBCR0 RST field 1 DBCR0 RST accessible by software debug DBCR0 RST is software readable writeable 3 UDE Unconditional Debug Event 0 Event owned by hardware debug No mtspr access by software to DBSR UDE field 1 Event owned by software debug DBSR UDE is software readable writeable 4 ICMP Instruction Complete Debug Event 0 Event owned ...

Page 101: ...control and status fields 1 Event owned by software debug IAC4 control and status fields are software readable writeable 12 DAC1 Data Address Compare 1 Debug Event 0 Event owned by hardware debug No mtspr access by software to DAC1 control and status fields 1 Event owned by software debug DAC1 control and status fields are software readable writeable 13 Reserved 14 DAC2 Data Address Compare 2 Debu...

Page 102: ...teable 25 CIRPT Critical Interrupt Taken Debug Event 0 Event owned by hardware debug No mtspr access by software to DBCR0 CIRPT or DBSR CIRPT fields 1 Event owned by software debug DBCR0 CIRPT and DBSR CIRPT are software readable writeable 26 CRET Critical Return Debug Event 0 Event owned by hardware debug No mtspr access by software to DBCR0 CRET or DBSR CRET fields 1 Event owned by software debu...

Page 103: ...DBERC0 CRET DBERC0 BKPT DBERC0 FT Name Software Accessible via mtspr affected by p_reset_b 0 DBCR0 4 DBSR DBCNT 1 1 DBSR MRR 1 1 1 DBCR0 IDM DBSR IDE VLES 1 1 1 DBCR0 RST 1 1 1 DBCR0 ICMP DBSR ICMP 1 1 1 DBCR0 BRT DBSR BRT 1 1 1 DBCR0 IRPT DBSR IRPT 1 1 1 DBCR0 TRAP DBSR TRAP 1 1 1 IAC1 DBCR0 IAC1 DBCR1 IAC1US IAC1ER DBSR IAC1 1 1 1 IAC2 DBCR0 IAC2 DBCR1 IAC2US IAC2ER DBSR IAC2 1 1 1 1 DBCR1 IAC12...

Page 104: ...T1 DEVT2T1 IAC1T1 IAC3T1 DAC1RT1 DAC1WT1 CNT2T1 2 DBSR DCNT1 CNT1TRG DBCNT CNT1 1 1 1 DBCR0 DCNT2 DBCR3 DEVT1C2 DEVT2C2 ICMPC2 IAC1C2 IAC2C2 IAC3C2 IAC4C2 DAC1RC2 DAC1WC2 DAC2RC2 DAC2WC2 3 DBSR DCNT2 DBCNT CNT2 1 1 1 1 DBCR3 CONFIG 1 1 1 DBCR0 CIRPT DBSR CIRPT 1 1 1 DBCR0 CRET DBSR CRET Table 2 24 DBERC0 Resource Control continued DBCR0 EDM DBERC0 IDM DBERC0 RST DBERC0 ICMP DBERC0 BRT DBERC0 IRPT ...

Page 105: ... and triggers regardless of whether software owns these events It is considered a programming error to enable counter or trigger events in DBCR3 which are not owned by software and operational results of the counter s are undefined if programmed 3 Note that software is given write access to all counter 2 control events regardless of whether software owns these events It is considered a programming...

Page 106: ...ower management mode Sleep mode is invoked by setting MSR WE while WE 1 Only one of DOZE NAP or SLEEP should be set for proper operation 0 Sleep mode is disabled 1 Sleep mode is enabled 43 45 Reserved should be cleared 46 ICR Interrupt inputs clear reservation 0 External and critical input interrupts do not affect reservation status 1 External and critical input interrupts clear an outstanding res...

Page 107: ...er the critical interrupt handler will not be run with MSR DE enabled 54 MCCLRDE Machine check interrupt clears MSR DE Controls whether machine check interrupts force debug interrupts to be disabled or are unaffected If critical interrupt debug events are enabled DBCR0 CIRPT is set which should only be done when the debug APU is enabled and MSR DE is set at the time of a machine check interrupt a ...

Page 108: ...cleared 56 ATS Atomic status read only Indicates state of the reservation bit in the load store unit See Section 3 7 Memory Synchronization and Reservation Instructions 57 62 Reserved should be cleared 63 ARD Address retraction disable 0 Address retraction enabled 1 Address retraction disabled Controls Address Retraction operation For details see Section 7 5 3 Address Retraction ...

Page 109: ...onfigure the e200z3 cache design For e200z3 reads of this register return a value of all zeros 32 53 54 55 62 63 Field BBFI BPEN Reset All zeros R W R W SPR SPR 1013 Figure 2 42 Branch Unit Control and Status Register BUCSR Table 2 27 Branch Unit Control and Status Register Bits Name Description 32 53 Reserved should be cleared 54 BBFI Branch target buffer flash invalidate When set BBFI flash clea...

Page 110: ... 44 32 61 62 63 Field TLB1_FI Reset All zeros R W R W SPR SPR 1012 Figure 2 43 MMU Control and Status Register 0 MMUCSR0 Table 2 28 MMUCSR0 Field Descriptions Bits Name Description 32 61 Reserved should be cleared 62 TLB1_FI TLB1 flash invalidate 0 No flash invalidate 1 TLB1 invalidation operation Hardware initiates a TLB1 invalidation after which TLB1_FI is cleared Setting TLB1_FI while an invali...

Page 111: ...me Description 32 48 Reserved should be cleared 49 52 NPIDS Number of PID registers 0001 This version of the MMU implements one PID register PID0 53 57 PIDSIZE PID register size 00111PID registers contain 8 bits in this version of the MMU 58 59 Reserved should be cleared 60 61 NTLBS Number of TLBs 01 This version of the MMU implements two TLB structures a null TLB0 and a populated TLB1 62 63 MAVN ...

Page 112: ... 46 TLB Configuration Register 1 TLB1CFG Table 2 31 TLB1CFG Field Descriptions Bits Name Description 32 39 ASSOC Associativity 0x8 Indicates that TLB1 associativity is 8 0x10 Indicates that TLB1 associativity is 16 40 43 MINSIZE Minimum page size 0x1 Smallest page size is 4 Kbytes 44 47 MAXSIZE Maximum page size 0x9 Largest page size is 256 Mbytes 0xb Largest page size is 4 Gbytes 48 IPROT Invalid...

Page 113: ...ESEL NV Reset Undefined on m_por assertion unchanged on p_reset_b assertion R W R W SPR SPR 624 Figure 2 47 MAS Register 0 MAS0 Format Table 2 32 MAS0 MMU Read Write and Replacement Control Bits Name Description 32 33 Reserved should be cleared 34 35 TLBSEL Selects TLB for access 01 TLB1 ignored by the e200z3 should be written to 01 for future compatibility 36 42 Reserved should be cleared 43 47 E...

Page 114: ...B1 34 39 Reserved should be cleared 40 47 TID Translation ID Compared with the current process IDs of the effective address to be translated A TID value of 0 defines an entry as global and matches with all process IDs 48 50 Reserved should be cleared 51 TS Translation address space Compared with MSR IS or MSR DS depending on the type of access to determine if this TLB entry may be used for transla...

Page 115: ...rformed to this page are written through to main memory 60 I Cache inhibited 0 This page is cacheable 1 This page is cache inhibited 61 M Memory coherence required The e200z3 does not support the memory coherence required attribute and thus it is ignored 0 Memory coherence is not required 1 Memory coherence is required 62 G Guarded The e200z3ignores the guarded attribute other than for generation ...

Page 116: ...D TIDSELD TSIZED VLED WD ID MD GD ED W Reset All zeros Figure 2 51 MMU Assist Register 4 MAS4 Table 2 36 MAS4 Hardware Replacement Assist Configuration Register Bits Name Description 32 33 Reserved should be cleared 34 35 TLBSELD Default TLB selected 01 TLB1 ignored by the e200z3 should be written to 01 for future compatibility 36 43 Reserved should be cleared 44 47 TIDSELD TID default selection v...

Page 117: ...gisters PID values are used to construct virtual addresses for accessing memory 2 17 Support for Fast Context Switching To provide real time capabilities for embedded systems future versions of the e200z3 core will include optional hardware support for fast context switching The initial version of the e200z3 does not implement additional register contexts 32 39 40 47 48 62 63 Field SPID SAS Reset ...

Page 118: ... and mtspr instructions The following sections outline additional access requirements 2 18 1 Invalid SPR References System behavior when an invalid SPR is referenced depends on the apparent privilege level of the register which is determined by bit 5 in the SPR address If the invalid SPR is accessible in user mode an illegal exception is generated If the invalid SPR is accessible only in superviso...

Page 119: ...on Required Before Required After Notes mtmsr UCLE None CSI mfspr DBCNT Debug counter register msync None 1 DBSR Debug status register msync None HID0 Hardware implementation dependent register 0 None None HID1 Hardware implementation dependent register 1 msync None MMUCSR MMU control and status register 0 CSI None mtspr BUCSR Branch unit control and status register None CSI CTXCR Context control ...

Page 120: ...ve restore register 1 575 R W Yes Yes ESR Exception syndrome register 62 R W Yes No HID0 Hardware implementation dependent reg 0 1008 R W Yes Yes HID1 Hardware implementation dependent reg 1 1009 R W Yes Yes IAC1 Instruction address compare 1 312 R W Yes No IAC2 Instruction address compare 2 313 R W Yes No IAC3 Instruction address compare 3 314 R W Yes No IAC4 Instruction address compare 4 315 R W...

Page 121: ...ache configuration register 0 515 Read only No Yes MAS0 MMU assist register 0 624 R W Yes Yes MAS1 MMU assist register 1 625 R W Yes Yes MAS2 MMU assist register 2 626 R W Yes Yes MAS3 MMU assist register 3 627 R W Yes Yes MAS4 MMU assist register 4 628 R W Yes Yes MAS6 MMU assist register 6 630 R W Yes Yes MCSR Machine check syndrome register 572 R W Yes Yes MMUCFG MMU configuration register 1015...

Page 122: ...figuration register 689 Read only Yes Yes TSR Timer status register 336 Read Clear4 Yes No USPRG0 User SPR general 0 256 R W No No XER Integer exception register 1 R W No No Notes 1 Only writable when multiple contexts are implemented Otherwise writes are ignored 2 The debug status register DBSR is read using mfspr DBSR cannot be directly written Instead DBSR bits corresponding to 1 bits in the GP...

Page 123: ...00_0000 DBSR 0x1000_0000 DEAR Unaffected 1 DEC Unaffected 1 DECAR Unaffected 1 DSRR0 Unaffected 1 DSRR1 Unaffected 1 ESR 0x0000_0000 HID0 HID1 0x0000_0000 IAC1 IAC4 0x0000_0000 IVOR0 IVOR15 Unaffected 1 IVOR32 IVOR34 Unaffected 1 IVPR Unaffected 1 L1CFG03 LR Unaffected 1 MAS0 MAS4 MAS6 Unaffected 1 MCSR 0x0000_0000 MMUCFG 3 MMUCSR0 0x0000_0000 MSR 0x0000_0000 PID0 0x0000_0000 PIR 3 0x0000_00 p_cpu...

Page 124: ...ring on data writes are not logged since the data driven by the CPU is valid The unit can be independently enabled for read cycles and write cycles allowing for flexible usage Software can also control accumulation of software provided values via a pair of update registers In addition there is a counter for software to monitor the number of beats of data compressed Updates are performed when the p...

Page 125: ...nc To ensure that the effects of an mtdcr to one of the PSU registers takes effect the mtdcr is followed by a context synchronizing instruction sc isync rfi rfci rfdi 2 19 1 Parallel Signature Control Register PSCR PSCR shown in Figure 2 55 controls operation of the parallel signature unit Figure 2 55 Parallel Signature Control Register PSCR 32 57 58 59 60 61 62 63 Field CNTEN RDEN WREN INIT Reset...

Page 126: ...S 59 60 Reserved should be cleared 61 RDEN Read enable 0 Processor data read cycles are ignored 1 Processor data reads cycles are accumulated For inactive byte lanes zeros are used for the data values 62 WREN Write enable 0 Processor write cycles are ignored 1 Processor write cycles are accumulated For inactive byte lanes zeros are used for the data values 63 INIT This bit can be written with a 1 ...

Page 127: ...ted by system reset thus should be initialized by software prior to performing parallel signature operations Figure 2 58 Parallel Signature Low Register PSLR 2 19 5 Parallel Signature Counter Register PSCTR PSCTR shown in Figure 2 59 provides count information for signature accumulation It is incremented on every accumulated transfer or on an mtdcr psulr rS Writing to PSCTR initializes a value bef...

Page 128: ... the PSCTR to increment Figure 2 60 Parallel Signature Update High Register PSUHR 2 19 7 Parallel Signature Update Low Register PSULR PSULR shown in Figure 2 61 updates the low signature value via software Writing to PSULR causes signature accumulation in the parallel signature low register PSLR using the data value written Writing to this register causes PSCTR to increment Figure 2 61 Parallel Si...

Page 129: ...ly Detailed descriptions are provided on conventions used for storing values in registers and memory for accessing processor registers and for representing data in these registers 3 1 1 Data Organization in Memory and Data Transfers Bytes in memory are numbered consecutively starting with 0 Each number is the address of the corresponding byte Memory operands can be bytes half words words or double...

Page 130: ...ng Point APU Instructions Unlike the PowerPC UISA the SPFP APUs store floating point values as single precision values in true 32 bit single precision format rather than in a 64 bit double precision format used with FPRs 3 2 Unsupported Instructions and Instruction Forms Because the e200z3 is a 32 bit Book E core all of the instructions defined for 64 bit implementations of the Book E architecture...

Page 131: ...pages marked as using the VLE extension are either 16 or 32 bits long and are aligned on 16 bit boundaries Therefore all instruction pages marked as VLE are required to use big endian byte ordering This section describes the various extensions to Book E instructions to support the VLE extension Table 3 2 List of Optionally Supported Instructions Type Name Mnemonics Unit Cache management instructio...

Page 132: ...aged because of the impact on performance Note Accesses that cross a translation boundary may be restarted A misaligned access that crosses a page boundary is restarted in its entirety in the event of a TLB miss of the second portion of the access This may result in the first portion being accessed twice Accesses that cross a translation boundary where endianness changes cause a byte ordering data...

Page 133: ...0 is the address of the interrupted instruction mbar Behaves identically to msync the mbar MO field is ignored by the e200z3 core lwarx stwcx Implemented as described in the EREF If the EA for either instruction is not a multiple of four an alignment interrupt is invoked The e200z3 allows lwarx and stwcx to access a page marked as write through required without invoking a data storage interrupt As...

Page 134: ...control of a predicate value supplied by a bit in the condition register isel can be used to eliminate branches in software and in many cases improve performance it can also increase program execution time determinism by eliminating the need to predict the target and direction of the branches replaced by the integer select function The isel instruction form and definition are described in the EREF...

Page 135: ...and multiply accumulate operations and of add and subtract to accumulator operations The SPE supports signed and unsigned forms and optional fractional forms For these instructions the fractional form does not apply to unsigned forms because integer and fractional forms are identical for unsigned operands Table 3 5 shows how SPE APU vector multiply instruction mnemonics are structured Table 3 6 de...

Page 136: ...uct wl Word low 32 32 32 low order 32 bits of product Data Type smf Signed modulo fractional Wrap no saturate smi Signed modulo integer Wrap no saturate ssf Signed saturate fractional ssi Signed saturate integer umi Unsigned modulo integer Wrap no saturate usi Unsigned saturate integer Accumulate Options a Update accumulator Update accumulator no add aa Add to accumulator Add result to accumulator...

Page 137: ... Signed Modulo Integer and Accumulate Negative evmhogsmian rD rA rB Multiply Half Words Odd Guarded Unsigned Modulo Integer and Accumulate evmhogumiaa rD rA rB Multiply Half Words Odd Guarded Unsigned Modulo Integer and Accumulate Negative evmhogumian rD rA rB Vector Absolute Value evabs rD rA Vector Add Immediate Word evaddiw rD rB UIMM Vector Add Signed Modulo Integer to Accumulator Word evaddsm...

Page 138: ... evfsdiv rD rA rB Vector Floating Point Multiply evfsmul rD rA rB Vector Floating Point Negate evfsneg rD rA Vector Floating Point Negative Absolute Value evfsnabs rD rA Vector Floating Point Subtract evfssub rD rA rB Vector Floating Point Test Equal evfststeq crD rA rB Vector Floating Point Test Greater Than evfststgt crD rA rB Vector Floating Point Test Less Than evfststlt crD rA rB Vector Load ...

Page 139: ...w rD rA rB Vector Multiply Half Words Even Signed Modulo Fractional and Accumulate Negative into Words evmhesmfanw rD rA rB Vector Multiply Half Words Even Signed Modulo Fractional Accumulate evmhesmfa rD rA rB Vector Multiply Half Words Even Signed Modulo Integer evmhesmi rD rA rB Vector Multiply Half Words Even Signed Modulo Integer and Accumulate into Words evmhesmiaaw rD rA rB Vector Multiply ...

Page 140: ...al and Accumulate into Words evmhossfaaw rD rA rB Vector Multiply Half Words Odd Signed Saturate Fractional and Accumulate Negative into Words evmhossfanw rD rA rB Vector Multiply Half Words Odd Signed Saturate Fractional Accumulate evmhossfa rD rA rB Vector Multiply Half Words Odd Signed Saturate Integer and Accumulate into Words evmhossiaaw rD rA rB Vector Multiply Half Words Odd Signed Saturate...

Page 141: ...y Word Signed Modulo Fractional and Accumulate evmwsmfa rD rA rB Vector Multiply Word Signed Modulo Fractional and Accumulate evmwsmfaa rD rA rB Vector Multiply Word Signed Modulo Fractional and Accumulate Negative evmwsmfan rD rA rB Vector Multiply Word Signed Modulo Integer evmwsmi rD rA rB Vector Multiply Word Signed Modulo Integer and Accumulate evmwsmia rD rA rB Vector Multiply Word Signed Mo...

Page 142: ... d rA Vector Store Word of Two Half Words from Even Indexed evstwhex rS rA rB Vector Store Word of Two Half Words from Odd evstwho rS d rA Vector Store Word of Two Half Words from Odd Indexed evstwhox rS rA rB Vector Store Word of Word from Even evstwwe rS d rA Vector Store Word of Word from Even Indexed evstwwex rS rA rB Vector Store Word of Word from Odd evstwwo rS d rA Vector Store Word of Word...

Page 143: ... listed in Table 3 8 NOTE Both the vector and scalar versions of the instructions have the same syntax Table 3 8 Vector and Scalar SPFP APU Floating Point Instructions Instruction Mnemonic Syntax Scalar Vector Convert Floating Point from Signed Fraction efscfsf evfscfsf rD rB Convert Floating Point from Signed Integer efscfsi evfscfsi rD rB Convert Floating Point from Unsigned Fraction efscfuf evf...

Page 144: ...alculation or conversion is denormalized the implementation may choose to use a same signed zero value in place of the denormalized operand Uses a same signed zero value in place of the denormalized operand Infinity and Infinity rounding modes are not required to be handled by an implementation If an implementation does not support Infinity rounding modes and the rounding mode is set to be Infinit...

Page 145: ... data In addition if rA 0 for any load or store with update instruction the e200z3 core updates rA GPR0 Load Multiple Word lmw Book E defines as invalid any form of the lmw instruction in which rA is in the range of registers to be loaded including the case in which rA 0 On the e200z3 invalid forms of lmw execute as follows Case 1 rA is in the range of rD rA 0 In this case address generation for i...

Page 146: ...ed with CA record CR X 011111 10100 01010 0 addeo Add Extended with CA record OV X 011111 10100 01010 1 addeo Add Extended with CA record OV CR D 001110 addi Add Immediate D 001100 addic Add Immediate Carrying D 001101 addic Add Immediate Carrying record CR D 001111 addis Add Immediate Shifted X 011111 00111 01010 0 addme Add to Minus One Extended with CA X 011111 00111 01010 1 addme Add to Minus ...

Page 147: ...and Link B 010000 0 1 bcl Branch Conditional and Link B 010000 1 1 bcla Branch Conditional and Link Absolute XL 010011 00000 10000 0 bclr Branch Conditional to Link Register XL 010011 00000 10000 1 bclrl Branch Conditional to Link Register and Link I 010010 0 1 bl Branch and Link I 010010 1 1 bla Branch and Link Absolute X 011111 00000 00000 cmp Compare D 001011 cmpi Compare Immediate X 011111 000...

Page 148: ... 01111 01011 1 divw Divide Word and record CR X 011111 11111 01011 0 divwo Divide Word and record OV X 011111 11111 01011 1 divwo Divide Word and record OV and CR X 011111 01110 01011 0 divwu Divide Word Unsigned X 011111 01110 01011 1 divwu Divide Word Unsigned and record CR X 011111 11110 01011 0 divwuo Divide Word Unsigned and record OV X 011111 11110 01011 1 divwuo Divide Word Unsigned and rec...

Page 149: ...ating Convert To Int Word with round to Zero and record CR A 111111 10010 0 fdiv1 Floating Divide A 111111 10010 1 fdiv 1 Floating Divide and record CR A 111011 10010 0 fdivs1 Floating Divide Single A 111011 10010 1 fdivs 1 Floating Divide Single and record CR A 111111 11101 0 fmadd1 Floating Multiply Add A 111111 11101 1 fmadd 1 Floating Multiply Add and record CR A 111011 11101 0 fmadds1 Floatin...

Page 150: ... 111011 11110 0 fnmsubs1 Floating Negative Multiply Subtract Single A 111011 11110 1 fnmsubs 1 Floating Negative Multiply Subtract Single and record CR A 111011 11000 0 fres1 Floating Reciprocal Estimate Single A 111011 11000 1 fres 1 Floating Reciprocal Estimate Single and record CR X 111111 00000 01100 0 frsp1 Floating Round to Single Precision X 111111 00000 01100 1 frsp 1 Floating Round to Sin...

Page 151: ...ating Point Double with Update Indexed X 011111 10010 10111 lfdx 1 Load Floating Point Double Indexed D 110000 lfs 1 Load Floating Point Single D 110001 lfsu 1 Load Floating Point Single with Update X 011111 10001 10111 lfsux 1 Load Floating Point Single with Update Indexed X 011111 10000 10111 lfsx 1 Load Floating Point Single Indexed D 101010 lha Load Half Word Algebraic D 101011 lhau Load Half ...

Page 152: ...ove From APID Indirect X 011111 00000 10011 mfcr Move From Condition Register XFX 011111 01010 00011 mfdcr3 Move From Device Control Register X 011111 01000 00011 mfdcrx3 Move From Device Control Register Indexed X 111111 10010 00111 0 mffs1 Move From FPSCR X 111111 10010 00111 1 mffs 1 Move From FPSCR and record CR X 011111 00010 10011 mfmsr Move From Machine State Register XFX 011111 01010 10011...

Page 153: ...ecord CR D 000111 mulli Multiply Low Immediate X 011111 00111 01011 0 mullw Multiply Low Word X 011111 00111 01011 1 mullw Multiply Low Word and record CR X 011111 10111 01011 0 mullwo Multiply Low Word and record OV X 011111 10111 01011 1 mullwo Multiply Low Word and record OV and CR X 011111 01110 11100 0 nand NAND X 011111 01110 11100 1 nand NAND and record CR X 011111 00011 01000 0 neg Negate ...

Page 154: ...X 011111 00000 11000 1 slw Shift Left Word and record CR X 011111 11000 11000 0 sraw Shift Right Algebraic Word X 011111 11000 11000 1 sraw Shift Right Algebraic Word and record CR X 011111 11001 11000 0 srawi Shift Right Algebraic Word Immediate X 011111 11001 11000 1 srawi Shift Right Algebraic Word Immediate and record CR X 011111 10000 11000 0 srw Shift Right Word X 011111 10000 11000 1 srw Sh...

Page 155: ...xed D 100100 stw Store Word X 011111 10100 10110 stwbrx Store Word Byte Reverse Indexed X 011111 00100 10110 1 stwcx 4 Store Word Conditional Indexed and record CR D 100101 stwu Store Word with Update X 011111 00101 10111 stwux Store Word with Update Indexed X 011111 00100 10111 stwx Store Word Indexed X 011111 00001 01000 0 subf Subtract From X 011111 00001 01000 1 subf Subtract From and record C...

Page 156: ...with CA X 011111 00110 01000 1 subfze Subtract From Zero Extended with CA and record CR X 011111 10110 01000 0 subfzeo Subtract From Zero Extended with CA and record OV X 011111 10110 01000 1 subfzeo Subtract From Zero Extended with CA and record OV and CR X 011111 11000 10010 tlbivax TLB Invalidate Virtual Address Indexed X 011111 11101 10010 tlbre TLB Read Entry X 011111 11100 10010 tlbsx TLB Se...

Page 157: ... D 000011 twi Trap Word Immediate D 000111 mulli Multiply Low Immediate D 001000 subfic Subtract From Immediate Carrying D 001010 cmpli Compare Logical Immediate D 001011 cmpi Compare Immediate D 001100 addic Add Immediate Carrying D 001101 addic Add Immediate Carrying and record CR D 001110 addi Add Immediate D 001111 addis Add Immediate Shifted B 010000 0 0 bc Branch Conditional B 010000 0 1 bcl...

Page 158: ... Condition Register XOR XL 010011 00111 00001 crnand Condition Register NAND XL 010011 01000 00001 crand Condition Register AND XL 010011 01001 00001 creqv Condition Register Equivalent XL 010011 01101 00001 crorc Condition Register OR with Complement XL 010011 01110 00001 cror Condition Register OR XL 010011 10000 10000 0 bcctr Branch Conditional to Count Register XL 010011 10000 10000 1 bcctrl B...

Page 159: ...0 01011 1 mulhwu Multiply High Word Unsigned and record CR X 011111 00000 10011 mfcr Move From Condition Register X 011111 00000 10100 lwarx Load Word and Reserve Indexed X 011111 00000 10110 icbt Instruction Cache Block Touch X 011111 00000 10111 lwzx Load Word and Zero Indexed X 011111 00000 11000 0 slw Shift Left Word X 011111 00000 11000 1 slw Shift Left Word and record CR X 011111 00000 11010...

Page 160: ... 00011 wrtee Write External Enable X 011111 00100 01000 0 subfe Subtract From Extended with CA X 011111 00100 01000 1 subfe Subtract From Extended with CA and record CR X 011111 00100 01010 0 adde Add Extended with CA X 011111 00100 01010 1 adde Add Extended with CA and record CR XFX 011111 00100 10000 mtcrf Move To Condition Register Fields X 011111 00100 10010 mtmsr Move To Machine State Registe...

Page 161: ...01000 01010 1 add Add and record CR X 011111 01000 10011 mfapidi Move From APID Indirect X 011111 01000 10110 dcbt Data Cache Block Touch X 011111 01000 10111 lhzx Load Halfword and Zero Indexed X 011111 01000 11100 0 eqv Equivalent X 011111 01000 11100 1 eqv Equivalent and record CR X 011111 01001 10111 lhzux Load Halfword and Zero with Update Indexed X 011111 01001 11100 0 xor XOR X 011111 01001...

Page 162: ...1111 10000 01000 0 subfco Subtract From Carrying and record OV X 011111 10000 01000 1 subfco Subtract From Carrying and record OV and CR X 011111 10000 01010 0 addco Add Carrying and record OV X 011111 10000 01010 1 addco Add Carrying and record OV and CR X 011111 10000 10101 lswx Load String Word Indexed X 011111 10000 10110 lwbrx Load Word Byte Reverse Indexed X 011111 10000 10111 lfsx Load Floa...

Page 163: ...OV X 011111 10110 01000 1 subfzeo Subtract From Zero Extended with CA and record OV and CR X 011111 10110 01010 0 addzeo Add to Zero Extended with CA and record OV X 011111 10110 01010 1 addzeo Add to Zero Extended with CA and record OV and CR X 011111 10110 10101 stswi Store String Word Immediate X 011111 10110 10111 stfdx Store Floating Point Double Indexed X 011111 10111 01000 0 subfmeo Subtrac...

Page 164: ...01 10010 tlbre TLB Read Entry X 011111 11101 11010 0 extsb Extend Sign Byte X 011111 11101 11010 1 extsb Extend Sign Byte and record CR X 011111 11110 01011 0 divwuo Divide Word Unsigned and record OV X 011111 11110 01011 1 divwuo Divide Word Unsigned and record OV and CR X 011111 11110 10010 tlbwe TLB Write Entry X 011111 11110 10110 icbi Instruction Cache Block Invalidate X 011111 11110 10111 st...

Page 165: ...stfs Store Floating Point Single D 110101 stfsu Store Floating Point Single with Update D 110110 stfd Store Floating Point Double D 110111 stfdu Store Floating Point Double with Update A 111011 10010 0 fdivs Floating Divide Single A 111011 10010 1 fdivs Floating Divide Single and record CR A 111011 10100 0 fsubs Floating Subtract Single A 111011 10100 1 fsubs Floating Subtract Single and record CR...

Page 166: ...iv Floating Divide A 111111 10010 1 fdiv Floating Divide and record CR A 111111 10100 0 fsub Floating Subtract A 111111 10100 1 fsub Floating Subtract and record CR A 111111 10101 0 fadd Floating Add A 111111 10101 1 fadd Floating Add and record CR A 111111 10110 0 fsqrt Floating Square Root A 111111 10110 1 fsqrt Floating Square Root and record CR A 111111 10111 0 fsel Floating Select A 111111 10...

Page 167: ...000 fcmpo Floating Compare Ordered X 111111 00001 00110 0 mtfsb1 Move To FPSCR Bit 1 X 111111 00001 00110 1 mtfsb1 Move To FPSCR Bit 1 and record CR X 111111 00001 01000 0 fneg Floating Negate X 111111 00001 01000 1 fneg Floating Negate and record CR X 111111 00010 00000 mcrfs Move to Condition Register from FPSCR X 111111 00010 00110 0 mtfsb0 Move To FPSCR Bit 0 X 111111 00010 00110 1 mtfsb0 Move...

Page 168: ...ruction Name Source add Add Book E add Add record CR Book E addc Add Carrying Book E addc Add Carrying record CR Book E addco Add Carrying record OV Book E addco Add Carrying record OV CR Book E adde Add Extended with CA Book E adde Add Extended with CA record CR Book E addeo Add Extended with CA record OV Book E addeo Add Extended with CA record OV CR Book E addi Add Immediate Book E addic Add Im...

Page 169: ...AND Immediate Shifted and record CR Book E b Branch Book E ba Branch Absolute Book E bc Branch Conditional Book E bca Branch Conditional Absolute Book E bcctr Branch Conditional to Count Register Book E bcctrl Branch Conditional to Count Register and Link Book E bcl Branch Conditional and Link Book E bcla Branch Conditional and Link Absolute Book E bclr Branch Conditional to Link Register Book E b...

Page 170: ... Block Touch for Store Book E dcbtstls 2 Data Cache Block Touch for Store and Lock Set Cache locking dcbz 2 Data Cache Block set to Zero Book E divw Divide Word Book E divw Divide Word and record CR Book E divwo Divide Word and record OV Book E divwo Divide Word and record OV and CR Book E divwu Divide Word Unsigned Book E divwu Divide Word Unsigned and record CR Book E divwuo Divide Word Unsigned...

Page 171: ...tract Scalar SPFP efststeq Floating Point Test Equal Scalar SPFP efststgt Floating Point Test Greater Than Scalar SPFP efststlt Floating Point Test Less Than Scalar SPFP e_ldmvgprw Load Multiple Volatile GPRs r0 r3 r12 Volatile context save restore e_ldmvsprw Load Multiple Volatile SPRs CR LR CTR and XER Volatile context save restore e_ldmvsrrw Load Multiple Volatile SRR SRR0 SRR1 Volatile context...

Page 172: ... Than Signed SPE evcmpltu Vector Compare Less Than Unsigned SPE evcntlsw Vector Count Leading Sign Bits Word SPE evcntlzw Vector Count Leading Zeros Word SPE evdivws Vector Divide Word Signed SPE evdivwu Vector Divide Word Unsigned SPE eveqv Vector Equivalent SPE evextsb Vector Extend Sign Byte SPE evextsh Vector Extend Sign Half Word SPE evfsabs Vector Floating Point Absolute Value SPE evfsabs Fl...

Page 173: ...Round toward Zero Vector SPFP evfsctuf Vector Convert Floating Point to Unsigned Fraction SPE evfsctuf Convert Floating Point to Unsigned Fraction Vector SPFP evfsctui Vector Convert Floating Point to Unsigned Integer SPE evfsctui Convert Floating Point to Unsigned Integer Vector SPFP evfsctuiz Vector Convert Floating Point to Unsigned Integer with Round toward Zero SPE evfsctuiz Convert Floating ...

Page 174: ... Odd Unsigned and Splat Indexed SPE evlwhe Vector Load Word into Two Half Words Even SPE evlwhex Vector Load Word into Two Half Words Even Indexed SPE evlwhos Vector Load Word into Half Words Odd Signed with sign extension SPE evlwhosx Vector Load Word into Half Words Odd Signed Indexed with sign extension SPE evlwhou Vector Load Word into Two Half Words Odd Unsigned zero extended SPE evlwhoux Vec...

Page 175: ...f Vector Multiply Half Words Even Signed Saturate Fractional SPE evmhessfa Vector Multiply Half Words Even Signed Saturate Fractional Accumulate SPE evmhessfaaw Vector Multiply Half Words Even Signed Saturate Fractional and Accumulate into Words SPE evmhessfanw Vector Multiply Half Words Even Signed Saturate Fractional and Accumulate Negative into Words SPE evmhessiaaw Vector Multiply Half Words E...

Page 176: ...ccumulate into Words SPE evmhosmianw Vector Multiply Half Words Odd Signed Modulo Integer and Accumulate Negative into Words SPE evmhossf Vector Multiply Half Words Odd Signed Saturate Fractional SPE evmhossfa Vector Multiply Half Words Odd Signed Saturate Fractional Accumulate SPE evmhossfaaw Vector Multiply Half Words Odd Signed Saturate Fractional and Accumulate into Words SPE evmhossfanw Vecto...

Page 177: ...ow Unsigned Modulo Integer and Accumulate SPE evmwlumiaaw Vector Multiply Word Low Unsigned Modulo Integer and Accumulate in Words SPE evmwlumianw Vector Multiply Word Low Unsigned Modulo Integer and Accumulate Negative in Words SPE evmwlusiaaw Vector Multiply Word Low Unsigned Saturate Integer and Accumulate in Words SPE evmwlusianw Vector Multiply Word Low Unsigned Saturate Integer and Accumulat...

Page 178: ...e SPE evsplati Vector Splat Immediate SPE evsrwis Vector Shift Right Word Immediate Signed SPE evsrwiu Vector Shift Right Word Immediate Unsigned SPE evsrws Vector Shift Right Word Signed SPE evsrwu Vector Shift Right Word Unsigned SPE evstdd Vector Store Double of Double SPE evstddx Vector Store Double of Double Indexed SPE evstdh Vector Store Double of Four Half Words SPE evstdhx Vector Store Do...

Page 179: ... operand Immediate and Record CR VLE 16 bit opcodes e_add2is Add 2 operand Immediate Shifted VLE 16 bit opcodes e_addi Add Immediate VLE 16 bit opcodes e_addi Add Immediate and Record VLE 16 bit opcodes e_addic Add Immediate Carrying VLE 16 bit opcodes e_addic Add Immediate Carrying and Record VLE 16 bit opcodes e_and2i AND 2 operand Immediate record CR VLE 16 bit opcodes e_and2is AND 2 operand Im...

Page 180: ...hau Load Halfword Algebraic With Update VLE 16 bit opcodes e_lhz Load Halfword Zero VLE 16 bit opcodes e_lhzu Load Halfword Zero with Update VLE 16 bit opcodes e_li Load Immediate VLE 16 bit opcodes e_lis Load Immediate Shifted VLE 16 bit opcodes e_lmw Load Multiple Word VLE 16 bit opcodes e_lwz Load Word Zero VLE 16 bit opcodes e_lwzu Load Word Zero with Update VLE 16 bit opcodes e_mcrf Move Cond...

Page 181: ...ract from Immediate Carrying VLE 16 bit opcodes e_subfic Subtract from Immediate and Record VLE 16 bit opcodes e_xori XOR Immediate VLE 16 bit opcodes e_xori XOR Immediate and Record VLE 16 bit opcodes icbi 2 Instruction Cache Block Invalidate Book E icblc 2 Instruction Cache Block Lock Clear Cache locking icbt 2 Instruction Cache Block Touch Book E icbtls 2 Instruction Cache Block Touch and Lock ...

Page 182: ...ce Control Register Book E mfdcrx4 Move From Device Control Register Indexed Book E mfmsr Move From Machine State Register Book E mfspr Move From Special Purpose Register Book E msync3 Memory Synchronize Book E mtcrf Move To Condition Register Fields Book E mtdcr4 Move To Device Control Register Book E mtdcrx4 Move To Device Control Register Indexed Book E mtmsr Move To Machine State Register Book...

Page 183: ...lwimi Rotate Left Word Immed then Mask Insert Book E rlwimi Rotate Left Word Immed then Mask Insert and record CR Book E rlwinm Rotate Left Word Immed then AND with Mask Book E rlwinm Rotate Left Word Immed then AND with Mask and record CR Book E rlwnm Rotate Left Word then AND with Mask Book E rlwnm Rotate Left Word then AND with Mask and record CR Book E sc System Call Book E se_add Add VLE 32 b...

Page 184: ...ompare Logical Immediate VLE 32 bit opcodes se_extsb Extend Sign Byte VLE 32 bit opcodes se_extsh Extend Sign Halfword VLE 32 bit opcodes se_extzb Extend with Zeros Byte VLE 32 bit opcodes se_extzh Extend with Zeros Halfword VLE 32 bit opcodes se_illegal Illegal VLE 32 bit opcodes se_isync Instruction Synchronize VLE 32 bit opcodes se_lbz Load Byte and Zero VLE 32 bit opcodes se_lhz Load Halfword ...

Page 185: ...2 bit opcodes se_stb Store Byte VLE 32 bit opcodes se_sth Store Halfword VLE 32 bit opcodes se_stw Store Word VLE 32 bit opcodes se_sub Subtract VLE 32 bit opcodes se_subf Subtract From VLE 32 bit opcodes se_subi Subtract Immediate VLE 32 bit opcodes se_subi Subtract Immediate and Record VLE 32 bit opcodes slw Shift Left Word Book E slw Shift Left Word and record CR Book E sraw Shift Right Algebra...

Page 186: ... Subtract From Extended with CA Book E subfe Subtract From Extended with CA and record CR Book E subfeo Subtract From Extended with CA and record OV Book E subfeo Subtract From Extended with CA and record OV and CR Book E subfic Subtract From Immediate Carrying Book E subfme Subtract From Minus One Extended with CA Book E subfme Subtract From Minus One Extended with CA and record CR Book E subfmeo...

Page 187: ...B Search Indexed Book E tlbsync TLB Synchronize Book E tlbwe TLB Write Entry Book E tw Trap Word Book E twi Trap Word Immediate Book E wrtee Write External Enable Book E wrteei Write External Enable Immediate Book E xor XOR Book E xor XOR and record CR Book E Table 3 13 Full Instruction Listing continued Mnemonic Instruction Name Source ...

Page 188: ...the user to perform bit reversed address computations for 65536 byte samples 2 Not supported by e200z3 unless the integrated device includes a cache treated as no ops with the exception of dcbz which results in an alignment interrupt and dcbi which is treated as a privileged no op 3 See Section 3 7 Memory Synchronization and Reservation Instructions 4 The core CPU will take an illegal instruction ...

Page 189: ...nterrupt occurs information about the processor state held in the MSR and the address at which execution should resume after the interrupt is handled are saved to a pair of save restore registers SRR0 SRR1 for non critical interrupts CSRR0 CSRR1 for critical interrupts or DSRR0 DSRR1 for debug interrupts when the debug APU is enabled and the processor begins executing at an address interrupt vecto...

Page 190: ...re caused by events external to the processor s instruction execution Synchronous exceptions are directly caused by instructions or by an event somehow synchronous to the program flow such as a context switch A precise interrupt architecturally guarantees that no instruction beyond the instruction causing the exception has visibly executed An imprecise interrupt does not have this guarantee Book E...

Page 191: ...d E bits Precise external termination error p_d_tea_b assertion and precise recognition and MSR EE 1 4 6 3 4 13 Instruction storage 3 Access control Precise external termination error p_i_tea_b assertion and precise recognition and MSR EE 1 Byte ordering due to misaligned instruction across page boundary to pages with mismatched VLE bits or access to page with VLE set and E indicating little endia...

Page 192: ...Data Interrupt IVOR33 4 6 19 4 27 SPE round 34 See Section 4 6 20 SPE Floating Point Round Interrupt IVOR34 4 6 20 4 27 1 Vector to p_rstbase 0 19 0xFFC in e200z3 Vector to p_rstbase 0 29 2 b00 in e200z335 2 Autovectored external and critical input interrupts use this IVOR Vectored interrupts supply an interrupt vector offset directly 32 35 36 37 38 39 40 41 42 43 44 45 46 47 48 55 56 57 58 59 61 ...

Page 193: ...ing point round exception alignment data storage data TLB 57 Reserved should be cleared 58 VLEMI VLE mode instruction SPE unavailable SPE floating point data exception SPE floating point round exception data storage data TLB instruction storage alignment program and system call 59 61 Reserved should be cleared 62 MIF Misaligned instruction fetch Instruction storage instruction TLB 63 XTE External ...

Page 194: ...l Input decrementer and fixed interval timer interrupts are disabled 1 External input decrementer and fixed interval timer interrupts are enabled 49 PR Problem state 0 The processor is in supervisor mode can execute any instruction and can access any resource for example GPRs SPRs MSR etc 1 The processor is in user mode cannot execute any privileged instruction and cannot access any privileged res...

Page 195: ...data storage accesses to address space 0 TS 0 in the relevant TLB entry 1 The core directs all data storage accesses to address space 1 TS 1 in the relevant TLB entry 60 61 Reserved should be cleared 62 RI Recoverable Interrupt e200z335 only 0 Machine Check interrupt is not recoverable 1 Machine Check interrupt may be recoverable This bit is cleared when a Machine check or critical class interrupt...

Page 196: ...used as the 36 EXCP_ERR ISI ITLB or bus error on first instruction fetch for an interrupt handler Precise 37 42 Reserved should be cleared 43 NMI Non maskable interrupt input signal e200z335 only Maybe 44 58 Reserved should be cleared 59 BUS_IRERR Read bus error on instruction fetch Unlikely 60 BUS_DRERR Read bus error on data load Unlikely 61 BUS_WRERR Write bus error on buffered store or cache l...

Page 197: ...Vector offset Provides a quadword index from the base address provided by the IVPR to locate an interrupt handler 60 Reserved should be cleared 61 63 CS Context selector When multiple hardware contexts are supported this selects an operating context for the interrupt handler This value is loaded into the CURCTX field of the context control register as part of the interrupt vectoring process This f...

Page 198: ...itical input interrupt may be delayed by other higher priority exceptions or if MSR CE is cleared when the exception occurs Table 4 9 lists register settings when a critical input interrupt is taken IVOR11 411 Fixed interval timer interrupt IVOR12 412 Watchdog timer interrupt IVOR13 413 Data TLB error IVOR14 414 Instruction TLB error IVOR15 415 Debug IVOR16 IVOR31 Reserved for future architectural...

Page 199: ...es an internal checkstop condition and enters checkstop state When a processor is in checkstop state instruction processing is suspended and generally cannot continue without restarting the processor Note that other conditions may lead to the checkstop condition the disabled machine check exception is only one of these The e200z3 implements MCSR to record the sources of machine checks See Section ...

Page 200: ...buffered store Precise external termination error occurs and MSR EE 0 Non exception related checkstop conditions are as follows TCR WRC Watchdog reset control bits set to checkstop on second watchdog timer overflow event Table 4 10 Machine Check Interrupt Register Settings Register Setting Description CSRR0 On a best effort basis the e200z3 sets this to the address of some instruction that was exe...

Page 201: ...hether these non maskable interrupts are potentially recoverable Since a non maskable interrupt overwrites the CSRR0 1 registers if these registers are currently holding essential state because a critical class interrupt handler has not yet been able to save this state away safely and a non maskable interrupt occurs no recovery from the earlier critical class interrupt is possible The machine chec...

Page 202: ...ESR as shown in Table 4 12 and Table 4 13 Table 4 13 lists register settings when an ISI is taken MSR UCLE 0 SPE 0 WE 0 CE EE 0 PR 0 FP 0 ME FE0 0 DE FE1 0 IS 0 DS 0 RI ESR Access Byte ordering External termination error precise ST VLEMI All other bits cleared ST VLEMI BO All other bits cleared ST VLEMI XTE All other bits cleared MCSR Unchanged DEAR For access and byte ordering exceptions set to t...

Page 203: ...ter settings when an external input interrupt is taken Table 4 13 Instruction Storage Interrupt Register Settings Register Setting Description SRR0 Set to the effective address of the excepting instruction SRR1 Set to the contents of the MSR at the time of the interrupt MSR UCLE 0 SPE 0 WE 0 CE EE 0 PR 0 FP 0 ME FE0 0 DE FE1 0 IS 0 DS 0 RI ESR XTE BO MIF VLEMI All other bits cleared MCSR Unchanged...

Page 204: ...ecution is attempted of an SPE APU load or store instruction that is not properly aligned Table 4 15 lists register settings when an alignment interrupt is taken 4 6 7 Program Interrupt IVOR6 The e200z3 implements the program interrupt as defined by Book E A program interrupt occurs when no higher priority exception exists and one or more of the following exception conditions defined in Book E occ...

Page 205: ...lemented by the e200z3 cause an illegal instruction program exception Table 4 16 lists register settings when a program interrupt is taken 4 6 8 Floating Point Unavailable Interrupt IVOR7 The floating point unavailable interrupt is implemented as defined in Book E A floating point unavailable interrupt occurs when no higher priority exception exists an attempt is made to execute a Book E defined f...

Page 206: ...available and no higher priority exception condition exists The e200z3 does not use this interrupt Table 4 17 Floating Point Unavailable Interrupt Register Settings Register Setting Description SRR0 Set to the effective address of the excepting instruction SRR1 Set to the contents of the MSR at the time of the interrupt MSR UCLE 0 SPE 0 WE 0 CE PR 0 FP 0 ME FE0 0 DE FE1 0 IS 0 DS 0 RI ESR Unchange...

Page 207: ...xists a fixed interval timer exception exists TSR FIS 1 and the interrupt is enabled both TCR FIE and MSR EE 1 The timer status register TSR holds the fixed interval timer interrupt bit set by the timer facility when an exception is detected Software must clear this bit in the interrupt handler to avoid repeated fixed interval timer interrupts Table 4 20 lists register settings when a fixed interv...

Page 208: ...0 RI ESR Unchanged MCSR Unchanged DEAR Unchanged Vector IVPR 32 47 IVOR11 48 59 0b0000 Table 4 21 Watchdog Timer Interrupt Register Settings Register Setting Description CSRR0 Set to the effective address of the instruction that the processor would have attempted to execute next if no exception conditions were present CSRR1 Set to the contents of the MSR at the time of the interrupt MSR UCLE 0 SPE...

Page 209: ...s in the TLB Table 4 23 lists register settings when an ITLB interrupt is taken Table 4 22 Data TLB Error Interrupt Register Settings Register Setting Description SRR0 Set to the effective address of the excepting load store instruction SRR1 Set to the contents of the MSR at the time of the interrupt MSR UCLE 0 SPE 0 WE 0 CE EE 0 PR 0 FP 0 ME FE0 0 DE FE1 0 IS 0 DS 0 RI ESR ST SPE VLEMI All other ...

Page 210: ...ts use CSRR0 and CSRR1 to save machine state NOTE For details regarding the following descriptions of debug exception types see Section 9 4 Software Debug Events and Exceptions Table 4 24 Debug Exceptions Exception Cause Instruction address compare IAC Instruction address compare events are enabled and an instruction address match occurs as defined by the debug control registers This could either ...

Page 211: ...ote that an IRPT debug interrupt occurs only when detecting a non critical interrupt on the e200z3 The value saved in CSRR0 DSRR0 is the address of the non critical interrupt handler Critical interrupt taken CIRPT A critical interrupt context switch is detected This exception is imprecise and unordered with respect to program flow Note that a CIRPT debug interrupt occurs only when detecting a crit...

Page 212: ...rrupt taken debug event Critical interrupt taken debug event Trap instruction debug event Instruction address compare Data address compare Return debug event Critical return debug event Debug counter event External debug event optional Imprecise debug event flag UDE ICMP BRT IRPT CIRPT TRAP IAC1 IAC2 IAC3 IAC4 DAC1R DAC1W DAC2R DAC2W RET CRET DCNT1 DCNT2 DEVT1 DEVT2 IDE ESR Unchanged MCSR Unchange...

Page 213: ...nated with 0xFFC in e200z3 and p_rstbase 0 29 concatenated with 2 b00 in e200z335 without attempting to reach a recoverable state If reset occurs during normal operation all operations stop and machine state is lost The internal state of the e200z6e200z3 after a reset is defined in Section 2 18 4 Reset Settings For reset initiated by watchdog timer or debug reset control the e200z6 implements TSR ...

Page 214: ...atus Bits Name Description 34 35 WRS 00 No action performed by watchdog timer 01 Watchdog timer second timeout caused checkstop 10 Watchdog timer second timeout caused p_resetout_b to be asserted 11 Reserved Table 4 27 DBSR Most Recent Reset Bits Name Function 34 35 MRR 00 No reset occurred since these bits were last cleared by software 01 A reset occurred since these bits were last cleared by sof...

Page 215: ...nstruction generates an inexact result and inexact exceptions are enabled Table 4 31 lists register settings when an SPE floating point round interrupt is taken MSR UCLE 0 SPE 0 WE 0 CE EE 0 PR 0 FP 0 ME FE0 0 DE FE1 0 IS 0 DS 0 RI ESR SPE VLEMI All other bits cleared MCSR Unchanged DEAR Unchanged Vector IVPR 32 47 IVOR32 48 59 0b0000 Table 4 30 SPE Floating Point Data Interrupt Register Settings ...

Page 216: ...sential state info and are overwritten when the NMI occurs Asynchronous maskable non recoverable Machine check interrupt Has priority over any other pending exception except system reset conditions is dependent on the source of the exception Typically non recoverable Asynchronous maskable recoverable External input fixed interval timer decrementer critical input unconditional debug external debug ...

Page 217: ...hout completing the exception causing instruction If completing previous instructions causes an exception that exception takes priority over the pending instruction dispatch execution exception which is discarded but may be encountered again when instruction processing resumes Post instruction execution Debug data address compare instruction complete interrupt Generated following execution and com...

Page 218: ...s in the TLB 14 11 Instruction storage 1 Access control 2 Precise external termination error p_tea_b assertion and precise recognition and MSR EE 1 3 Byte ordering due to misaligned instruction across page boundary to pages with mismatched VLE bits or access to page with VLE set and E indicating little endian 4 Misaligned Instruction fetch due to a change of flow to an odd halfword instruction bou...

Page 219: ...Exceptions require corresponding debug event enabled MSR DE 1 and DBCR0 IDM 1 15 Post Instruction Execution Exceptions 23 1 Debug DAC IAC linked2 2 Debug DAC unlinked2 1 Data address compare linked with instruction address compare 2 Data address compare unlinked Notes Exceptions require corresponding debug event enabled MSR DE 1 and DBCR0 IDM 1 Saved PC points to the instruction following the load...

Page 220: ... by a single exception type and thus do not use an ESR setting to indicate the interrupt cause The MSR is updated to preclude unrecoverable interrupts from occurring during the initial portion of the interrupt handler Specific settings are described in Table 4 33 For alignment data storage or data TLB miss interrupts or for a machine check due to cache parity error on data access interrupts the da...

Page 221: ...ns is delayed CE is cleared automatically when a critical interrupt is taken to mask further recognition of conditions causing those exceptions In addition MSR RI is cleared to indicate that the CSRR0 1 registers contain information essential to exception recovery Synchronous and asynchronous debug exceptions are enabled by setting MSR DE If DE 0 recognition of these exception conditions is masked...

Page 222: ...n and that rfci may be subject to a critical return type debug exception For a complete description of context synchronization refer to the EREF 4 9 Process Switching The following instructions are useful for restoring proper context during process switching msync orders the effects of data memory instruction execution All instructions previously initiated appear to have completed before the msync...

Page 223: ...tes 256 Kbytes 1 Mbyte 4 Mbytes 16 Mbytes 64 Mbytes 256 Mbytes shown in Table 5 2 One 32 bit PID register PID0 for supporting up to 255 translation IDs at any time in the TLB No page table format defined software is free to use its own page table format Hardware assist for TLB miss exceptions TLB1 managed by tlbre tlbwe tlbsx tlbsync and tlbivax instructions and six MMU assist MAS registers IPROT ...

Page 224: ...ion Section Page TLB Instructions tlbre TLB Read Entry instruction 5 4 5 10 tlbwe TLB Write Entry instruction 5 4 5 10 tlbsx rA rB TLB Search for Entry instruction 5 4 5 10 tlbivax rA rB TLB Invalidate Entries instruction 5 4 5 10 tlbsync TLB Synchronize Invalidations with other masters instruction privileged no op on the e200z3 5 4 5 10 Registers PID0 Process ID register 2 4 2 2 9 MMUCSR0 MMU con...

Page 225: ...et 0 n 31 TLB Multiple Entry MSR IS for Instruction Fetch AS MSR DS for Data Access RPN field of matching entry n 1 Real Page Number Offset 0 n 31 n 1 Effective Page Number Byte Address Real Page Number Byte Address 32 bit Effective Address EA 32 Bit Real Address 15 20 Bits 12 Bits 15 20 Bits 12 Bits MMU Unified Three 41 Bit Virtual Addresses VAs 8 Bits MSR IS DS Instruction Access Data Access AS ...

Page 226: ...or the corresponding value of either MSR IS or MSR DS is used in addition to the effective address generated by the processor for translation into a physical address by the TLB mechanism Because MSR IS and MSR DS are both cleared when an interrupt occurs an address space value of 0 can be used to denote interrupt related address spaces or possibly all system software address spaces An address spac...

Page 227: ... the access in PID0 or have a TID value of 0 indicating that the entry is globally shared among all processes Figure 5 2 shows the translation match logic for the effective address plus its attributes collectively called the virtual address and how it is compared with the corresponding fields in the TLB entries Figure 5 2 Virtual Address and TLB Entry Compare Process The page size defined for a TL...

Page 228: ...and store type cache management instructions to access the page while in supervisor mode MSR PR 0 SX Supervisor execute permission Allows instruction fetches to access the page and instructions to be executed from the page while in supervisor mode MSR PR 0 UR User read permission Allows loads and load type cache management instructions to access the page while in user mode MSR PR 1 UW User write p...

Page 229: ...iable page sizes thus it corresponds to TLB1 in the programming model For the rest of this document TLB TLBCAM and TLB1 are used interchangeably The TLB on the e200z3 MMU TLB1 consists of a 16 entry fully associative content addressable memory CAM array with support for nine page sizes To perform a lookup the TLB is searched in parallel for a matching TLB entry The contents of a matching TLB entry...

Page 230: ...ters and executing the tlbwe instruction Invalidation operations generated by execution of the tlbivax instruction are guaranteed to invalidate the entry that translates the address specified in the operand of the tlbivax instruction Additional entries may also be invalidated by this operation if they are not protected with IPROT A precise invalidation can be performed by writing a 0 to the valid ...

Page 231: ...instructions Because the core does not make requests for load or store instructions until it is known that prior instructions will complete without exceptions the G bit is essentially ignored Proper operation always occurs to guarded storage 5 3 4 TLB Entry Field Summary Table 5 3 summarizes the fields of e200z3 TLB entries Note that all of these fields are defined at the Freescale Book E level Ta...

Page 232: ...n On taking a DSI or ISI interrupt hardware updates only the search PID SPID and search address space SAS fields in the MAS registers using the contents of PID0 and the corresponding MSR IS or MSR DS value used when the data or instruction storage interrupt was recognized During the interrupt handler software can issue a TLB Search Instruction tlbsx which uses the SPID field along with the SAS fie...

Page 233: ... except for that shown in Table 5 4 is used for the invalidation AS and TID values are ignored Additional information about the targeted TLB entries is encoded in two of the lower bits of the effective address calculated by the tlbivax EA 0 19 are used to perform the tlbivax invalidation of TLB1 t TLB Synchronize tlbsync Treated as a privileged no op by the e200z3 5 5 TLB Operations This section d...

Page 234: ...sx instruction searches using EPN 0 19 from the GPR selected by the instruction SAS search AS bit in MAS6 and SPID in MAS6 If the search is successful the given TLB entry information is loaded into MAS0 MAS3 The valid bit in MAS1 is used as the success flag If the search is successful the valid bit in MAS1 is set if unsuccessful it is cleared The tlbsx instruction is useful for finding the TLB ent...

Page 235: ... there are a number of MMU control and assist registers summarized in Section 2 16 4 MMU Assist Registers MAS0 MAS4 MAS6 5 6 1 MMU Configuration Register MMUCFG MMUCFG provides configuration information for the MMU supplied with this version of the e200z3 CPU core See Section 2 16 2 MMU Configuration Register MMUCFG Table 5 5 TLB Entry 0 Values after Reset Field Reset Value Comments VALID 1 Entry ...

Page 236: ... Register 0 MMUCSR0 controls the state of the MMU 5 6 5 MMU Assist Registers MAS The e200z3 uses MAS0 MAS4 and MAS6 SPRs to facilitate reading writing and searching the TLBs The e200z3 does not implement MAS5 because the tlbsx instruction only searches based on a single SPID value MAS registers are described in Section 2 16 4 MMU Assist Registers MAS0 MAS4 MAS6 5 6 5 1 MAS Registers Summary The fi...

Page 237: ...OnCE OCR and normal translation including the possibility of a TLB miss or DSI remains in effect Refer to Section 9 5 5 3 OnCE Control Register OCR for details on controlling MMU operation during debug sessions Table 5 6 MMU Assist Register Field Updates Bit Field MAS Affected ITLB DTLB Error tlbsx hit tlbsx miss tlbre tlbwe ISI DSI TLBSEL 0 TLBSELD 01 TLBSELD NC1 1 NC no change NC NC ESEL 0 NV Ma...

Page 238: ...Memory Management Unit e200z3 Power Architecture Core Reference Manual Rev 2 5 16 Freescale Semiconductor ...

Page 239: ... instruction fetch unit attempts to supply a constant stream of instructions to the execution pipeline It does so by decoding and detecting branches early in the instruction buffer making branch predictions and prefetching their branch targets into the instruction buffer By prefetching the branch targets early some or all of the branch pipeline bubbles can be hidden from the execution pipeline The...

Page 240: ...trols the flow of instructions to the instruction buffers and decode unit Six prefetch buffers allow the instruction unit to fetch instructions ahead of actual execution and serve to decouple memory and the execution pipeline CPU Load Data Memory Address Store Unit Instruction Unit Branch Unit PC Unit Instruction Buffer GPR CR SPR Multiply Unit Data Bus Interface Unit Control 32 64 N OnCE Nexus In...

Page 241: ...single processor clock cycle 6 1 5 Exception Handling The exception handling unit includes logic to handle exceptions interrupts and traps 6 2 Execution Units The core data execution units consist of the integer unit and the load store unit Included in the execution units section are the general purpose registers GPRs Instructions with data dependencies begin execution when all such dependencies a...

Page 242: ...ute stage The processor also contains an instruction prefetch buffer to allow buffering of instructions prior to the decode stage Instructions proceed from this buffer to the instruction decode stage by entering the instruction decode register IR Figure 6 2 Pipeline Diagram 6 3 1 Description of Pipeline Stages The fetch pipeline stages retrieve instructions from the memory system and determine whe...

Page 243: ...d forwarding allows the result of one instruction to be made available as the source operand s of a subsequent instruction so that data dependent instructions can execute without waiting for previous instructions to write back their results 6 3 2 Instruction Buffers The e200z3 contains a set of instruction buffers that supply instructions into the instruction register IR for decoding Instruction p...

Page 244: ...es are allocated on taken branches using a FIFO replacement algorithm Each BTB entry holds a 2 bit branch history counter whose value is incremented or decremented on a BTB hit depending on whether the branch was taken The counter can assume four different values strongly taken weakly taken weakly not taken and strongly not taken A branch is predicted as taken on a hit in the BTB with a counter va...

Page 245: ...t branch entry The BTB uses virtual addresses for performing tag comparisons On allocation of a BTB entry the EA of a taken branch along with the current instruction space as indicated by MSR IS is loaded into the entry and the counter value is set to weakly taken The current PID value is not maintained as part of the tag information The BTB is automatically flushed when the current PID value is u...

Page 246: ...flow for a load instruction followed by a dependent add instruction Figure 6 6 A Load Followed by a Dependent Add Instruction Back to back load store instructions are executed in a pipelined fashion provided that their EA calculations are not dependent on their previous load instructions Figure 6 7 shows the basic pipeline flow for two back to back load instructions In this case the second load do...

Page 247: ...uction Pipeline Operation A branch instruction takes either one or 2 cycles to execute Simple change of flow instructions require 2 cycles to refill the pipeline with the target instruction for taken branches and branch and link instructions with no prediction For branch type instructions in some situations this 2 cycle timing may be reduced by performing the target fetch speculatively while the b...

Page 248: ... multi cycle instruction must wait for completion of the multi cycle instruction prior to its writeback in order to meet the in order requirement Result feed forward paths are provided so that execution may continue prior to result writeback 6 3 7 Additional Examples of Instruction Pipeline Operation for Load and Store Figure 6 12 shows an example of pipelining two non data dependent load or store...

Page 249: ...line and do not cause stalls Exceptions are for the MSR the debug SPRs the embedded floating point APUs and MMU SPRs which do cause stalls Figure 6 14 through Figure 6 16 show examples of mtspr and mfspr instruction timing Figure 6 14 applies to the debug SPRs and the EFPU s EFSCR These instructions do not begin execution until all previous instructions have finished their execute stage If a multi...

Page 250: ...s window where no translations or cache cycles are required Figure 6 16 shows an example where an outstanding bus access delays mtspr mfspr execution until the bus becomes idle Processor access requests are held off during execution of an MMU SPR instruction A subsequent access request may be generated in the WB cycle This same protocol applies to MMU management instructions such as tlbre tlbwe et...

Page 251: ...e instruction completes The following instructions are completion serialized Instructions that access or modify system control or status registers mcrxr mtmsr wrtee wrteei mtspr mfspr except to CTR LR Instructions that manage TLBs Instructions defined by the architecture as context or execution synchronizing isync msync rfi rfci rfdi and sc Dispatch decode issue serialization Some instructions are...

Page 252: ...ons 6 6 Interrupt Recognition and Exception Processing Figure 6 17 shows timing for interrupt recognition and exception processing overhead This example shows best case response timing when an interrupt is received and processed during execution of a sequence of single cycle instructions Figure 6 17 Interrupt Recognition and Handler Instruction Execution Time Slot IFETCH EXE WB DEC Single cycle In...

Page 253: ...or store instruction The fetch for the handler is delayed until completion of the load or store regardless of the number of wait states Figure 6 18 Interrupt Recognition and Handler Instruction Execution Load Store in Progress Time Slot DEC EA wait wait Mem Load Store Instructions IFETCH Abort DEC p_extint_b Final Sample Point p_iack IFETCH EXE WB DEC First Instruction of Handler 1 2 3 4 5 6 7 8 9...

Page 254: ... Pipelined instructions are shown with cycles of total latency and throughput Divide instructions are not pipelined and block other instructions from executing during divide execution Load store multiple instruction cycles are represented as a fixed number of cycles plus a variable number of cycles where n is the number of words accessed by the instruction Additionally cycle times marked with an a...

Page 255: ...2 1 Branches take between 1 and 2 cycles to execute Multiply 1 1 Divide 6 16 6 16 Data dependent timing CR logical 1 1 Loads non multiple 1 1 Load multiple 1 n 2 max 1 n 2 max Timing depends on n and address alignment Stores non multiple 1 1 Store multiple 1 n 2 max 1 n 2 max Timing depends on n and address alignment mtmsr wrtee wrteei 2 2 mcrf 1 1 mfspr mtspr 2 2 Applies to debug SPRs optional un...

Page 256: ... e_cmpl16i se_cmpl se_cmpli 1 None cntlzw 1 None crand e_crand 1 None crandc e_crandc 1 None creqv e_creqv 1 None crnand e_crnand 1 None crnor e_crnor 1 None cror e_cror 1 None crorc e_crorc 1 None crxor e_crxor 1 None divwu o 6 16 None divw o 6 16 None With early out capability timing is data dependent eqv 1 None extsb se_extsb 1 None extsh se_extsh 1 None e_li e_lis se_li 1 None The UISA defines...

Page 257: ...wzu 1 None Aligned lwzux 1 None Aligned lwzx 1 None Aligned mbar 1 Completion Plus additional synchronization time mcrf e_mcrf 1 None mcrxr 1 Completion mfcr 1 None mfmsr 1 None mfspr except debug MMU se_mfctr se_mflr 1 None mfspr debug MMU 3 Completion Plus additional synchronization time msync 1 Completion Plus additional synchronization time mtcrf 2 None mtmsr 2 Completion Plus additional synch...

Page 258: ...wimi 1 None rlwinm e_rlwinm 1 None rlwnm 1 None sc 3 Refetch se_bmski 1 None se_bseti 1 None se_btsti 1 None se_extzb se_extzh 1 None se_mfar 1 None se_mr 1 None The UISA defines mr as a simplified mnemonic for or se_mtar 1 None se_not 1 None slw se_slw e_slwi se_slwi 1 None srawi se_srawi 1 None sraw se_sraw 1 None srw se_srw e_srwi se_srwi 1 None stb e_stb se_stb 1 None Aligned stbu e_stbu 1 Non...

Page 259: ...PU instruction stalls until it can be ensured that no previous instruction can generate a floating point exception This determination is based on which floating point exception enable bits are set FINVE FOVFE FUNFE FDBZE and FINXE and at what sth sth e_sth se_sth e_sthu 1 None Aligned sthbrx 1 None Aligned sthu 1 None Aligned sthux 1 None Aligned sthx 1 None Aligned stmw e_stmw 1 n 2 None stw e_st...

Page 260: ...ious floating point instructions have already resolved the possibility of exceptional results 6 7 1 1 SPE Integer Simple Instructions Timing Instruction timing for SPE integer simple instructions is shown in Table 6 4 The table is sorted by opcode These instructions are issued as a pair of operations Table 6 4 Timing for Integer Simple Instructions Instruction Latency Throughput Comments brinc 1 1...

Page 261: ...r aligned operands evrlwi 1 1 evrndw 1 1 evsel 1 1 evslw 1 1 evslwi 1 1 evsplatfi 1 1 evsplati 1 1 evsrwis 1 1 evsrwiu 1 1 evsrws 1 1 evsrwu 1 1 evsubfw 1 1 evsubifw 1 1 evxor 1 1 Table 6 5 SPE Load and Store Instruction Timing Instruction Latency Throughput Comments evldd 1 1 evlddx 1 1 evldh 1 1 evldhx 1 1 evldw 1 1 evldwx 1 1 evlhhesplat 1 1 evlhhesplatx 1 1 evlhhossplat 1 1 evlhhossplatx 1 1 e...

Page 262: ...structions evlwhex 1 1 evlwhos 1 1 evlwhosx 1 1 evlwhou 1 1 evlwhoux 1 1 evlwhsplat 1 1 evlwhsplatx 1 1 evlwwsplat 1 1 evlwwsplatx 1 1 evstdd 1 1 evstddx 1 1 evstdh 1 1 evstdhx 1 1 evstdw 1 1 evstdwx 1 1 evstwhe 1 1 evstwhex 1 1 evstwho 1 1 evstwhox 1 1 evstwwe 1 1 evstwwex 1 1 evstwwo 1 1 evstwwox 1 1 Table 6 6 SPE Complex Integer Instruction Timing Instruction Latency Throughput Comments evaddsm...

Page 263: ... 1 evmhegumian 1 1 evmhesmf 1 1 evmhesmfa 1 1 evmhesmfaaw 1 1 evmhesmfanw 1 1 evmhesmi 1 1 evmhesmia 1 1 evmhesmiaaw 1 1 evmhesmianw 1 1 evmhessf 1 1 evmhessfa 1 1 evmhessfaaw 1 1 evmhessfanw 1 1 evmhessiaaw 1 1 evmhessianw 1 1 evmheumi 1 1 evmheumia 1 1 evmheumiaaw 1 1 evmheumianw 1 1 evmheusiaaw 1 1 evmheusianw 1 1 evmhogsmfaa 1 1 evmhogsmfan 1 1 evmhogsmiaa 1 1 evmhogsmian 1 1 evmhogumiaa 1 1 T...

Page 264: ...nw 1 1 evmhossf 1 1 evmhossfa 1 1 evmhossfaaw 1 1 evmhossfanw 1 1 evmhossiaaw 1 1 evmhossianw 1 1 evmhoumi 1 1 evmhoumia 1 1 evmhoumiaaw 1 1 evmhoumianw 1 1 evmhousiaaw 1 1 evmhousianw 1 1 evmra 1 1 evmwhsmf 1 1 evmwhsmfa 1 1 evmwhsmi 1 1 evmwhsmia 1 1 evmwhssf 1 1 evmwhssfa 1 1 evmwhumi 1 1 evmwhumia 1 1 evmwlsmiaaw 1 1 evmwlsmianw 1 1 evmwlssiaaw 1 1 Table 6 6 SPE Complex Integer Instruction Tim...

Page 265: ...fsdiv is latency cycles evmwlssianw 1 1 evmwlumi 1 1 evmwlumia 1 1 evmwlumiaaw 1 1 evmwlumianw 1 1 evmwlusiaaw 1 1 evmwlusianw 1 1 evmwsmf 1 1 evmwsmfa 1 1 evmwsmfaa 1 1 evmwsmfan 1 1 evmwsmi 1 1 evmwsmia 1 1 evmwsmiaa 1 1 evmwsmian 1 1 evmwssf 1 1 evmwssfa 1 1 evmwssfaa 1 1 evmwssfan 1 1 evmwumi 1 1 evmwumia 1 1 evmwumiaa 1 1 evmwumian 1 1 evsubfsmiaaw 1 1 evsubfssiaaw 1 1 evsubfumiaaw 1 1 evsubf...

Page 266: ...nstruction Latency Throughput Comments evfsabs 1 1 evfsadd 1 1 evfscfsf 1 1 evfscfsi 1 1 evfscfuf 1 1 evfscfui 1 1 evfscmpeq 1 1 evfscmpgt 1 1 evfscmplt 1 1 evfsctsf 1 1 evfsctsi 1 1 evfsctsiz 1 1 evfsctuf 1 1 evfsctui 1 1 evfsctuiz 1 1 evfsdiv 12 12 Blocking no overlap with next instruction evfsmadd 1 1 Destination also used as source evfsmsub 1 1 Destination also used as source evfsmul 1 1 evfsn...

Page 267: ...ng Instruction Latency Throughput Comments efsabs 1 1 efsadd 1 1 efscfsf 1 1 efscfsi 1 1 efscfuf 1 1 efscfui 1 1 efscmpeq 1 1 efscmpgt 1 1 efscmplt 1 1 efsctsf 1 1 efsctsi 1 1 efsctsiz 1 1 efsctuf 1 1 efsctui 1 1 efsctuiz 1 1 efsdiv 12 12 Blocking no execution overlap with next instruction efsdiv 12 12 Blocking no execution overlap with next instruction efsmadd 1 1 Destination also used as source ...

Page 268: ...le bus transfers poor means that the access generates an alignment interrupt Table 6 9 Performance Effects of Storage Operand Placement Operand Boundary Crossing Size Byte Alignment None Cache Line Protection Boundary 4 byte 4 4 optimal good good good 2 byte 2 2 optimal good good good 1 byte 1 optimal lmw stmw 4 4 good poor good poor good poor String N A Note Optimal One EA calculation occurs Good...

Page 269: ...rface signals A test interface The memory interface that the BIU supports is based on the AMBA AHB Lite subset of the AMBA 2 0 AHB with V6 AMBA extensions Ref documents ARM IHI 0011A ARM DVI 0044A and ARM PR022 GENC 001011 0 4 Sideband signals described in this chapter support additional control functions A 64 bit data bus is implemented The pipelined memory interface supports read and write trans...

Page 270: ...ting the original data size either half word or word for the first transfer along with appropriate byte enables For the second transfer the address is incremented to the next 64 bit boundary and the size and byte enable signals are driven to correspond to the number of remaining bytes to be transferred 7 2 Signal Index This section contains an index of the core signals The following prefixes are u...

Page 271: ... p_tbint p_tbclk Time Base p_tbdisable Signals Debug Support e200z3 Module jd_debug_b dbg_dbgrq cpu_dbgack OnCE Control JTAG Interface jd_de_b Test Interface jd_de_en jd_en_once jd_watchpt 0 n jd_mclk_on j_en_once_regsel m_por p_resetout_b p_rstbase 0 19 related Signals OnCE Debug p_d_hwdata 63 0 p_ d i _hrdata 63 0 p_cpuid 0 7 Miscellaneous p_sysvers 0 31 p_pvrin 16 31 Signals Processor p_ d i _h...

Page 272: ... to be loaded into TLB entry 0 on reset p_rst_vlemode I Reset VLE mode select value to be loaded into TLB entry 0 on reset Memory Interface Signals p_i_hmaster 3 0 p_d_hmaster 3 0 O Master ID p_i_haddr 31 0 p_d_haddr 31 0 O Address bus p_i_hwrite p_d_hwrite O 0 Write signal always driven low for p_i_hwrite p_i_hprot 5 0 p_d_hprot 5 0 O Protection codes p_i_htrans 1 0 p_d_htrans 1 0 O Transfer type...

Page 273: ...gnals p_tbint O 0 Time base interrupt p_tbdisable I Time base disable input p_tbclk I Time base clock input Misc CPU Signals p_cpuid 0 7 I CPU ID input p_sysvers 0 31 I System version inputs for SVR p_pvrin 16 31 I Inputs for PVR p_pid0 0 7 O 0 PID0 24 31 outputs p_pid0_updt O 0 PID0 update status CPU Reservation Signals p_rsrv O 0 Reservation status p_rsrv_clr I Clear reservation flag CPU State S...

Page 274: ...k jd_watchpt 0 7 O 0 Address watchpoint occurred Development Support Signals Nexus 3 nex_mcko O Nexus3 clock output nex_rdy_b O Nexus3 ready output nex_evto_b O Nexus3 event out output nex_evti_b I Nexus3 event in input nex_mdo n 0 O Nexus3 message data output nex_mseo_b 1 0 O Nexus3 message start end output JTAG Related Signals j_trst_b I JTAG test reset from pad j_tclk I JTAG test clock from pad...

Page 275: ...ie m_por low it is required to assert j_trst_b during processor power up reset When a power up reset is achieved the two resets can be asserted independently A reset output signal p_resetout_b is also provided j_shift_ir O 0 Shift_IR state of JTAG controller j_capture_dr O 0 Parallel test data register load state of JTAG controller j_shift_dr O 0 TAP controller in shift DR state j_update_gp_reg O ...

Page 276: ...ntrol logic p_resetout_b is not asserted by p_reset_b p_rstbase 0 19 I Reset base Allows system integrators to specify or relocate the base address of the reset exception handler State Meaning Forms the upper 20 bits of the instruction access following negation of reset which is used to fetch the initial instruction of the reset exception handler These bits should be driven to a value correspondin...

Page 277: ...ition p_d_hwdata 63 is the msb and p_d_hwdata 0 is the lsb Memory Byte AddressWired to p_d_hwdata Bits 0007 0 00115 8 01023 16 01131 24 10039 32 10147 40 11055 48 11163 56 Table 7 5 Descriptions of Transfer Attribute Signals Signal I O Signal Description p_ d i _htrans 1 0 O Transfer type The processor drives p_ d i _htrans 1 0 to indicate the current transfer type as follows 00 IDLE No data trans...

Page 278: ...supervisor p_ d i _hprot 5 indicates whether the access is exclusive that is for an lwarx or stwcx p_ d i _hprot 4 2 allocate cacheable bufferable indicate particular cache attributes for the access The following table shows the definitions of the p_ d i _hprot 5 0 signals p_hprot5 p_hprot4 p_hprot3 p_hprot2 p_hprot1 p_hprot0 Transfer Type 0 Instruction access 1 Data access 0 User mode access 1 Su...

Page 279: ...ligned When p_ d i _hunalign is asserted the p_ d i _hbstrb 7 0 byte strobe signals indicate the selected bytes involved in the current portion of the misaligned access which may not include all bytes defined by the size and low order address signals Aligned transfers also assert the byte strobes but in a manner corresponding to size and low order address bits Negated No misaligned data access is ...

Page 280: ...3 0 0 X X 1 0 Word 000 0 0 0 1 0 X X X X 0 Word 001 0 0 1 1 1 2 X X X X 1 Word 010 0 1 0 1 1 2 X X X X 1 Word 011 0 1 1 1 1 2 X X X X 1 Word 100 1 0 0 1 0 X X X X 0 Word 101 Two bus transfers 1 0 1 0 0 0 1 0 0 0 X X X X 1 0 Word 110 Two bus transfers 1 1 0 0 0 0 1 0 3 0 1 X X X X 1 0 Word 111 Two bus transfers 1 1 1 0 0 0 1 0 3 1 0 X X X X 1 1 Double word 0 0 0 1 1 X X X X X X X X 0 1 X indicates ...

Page 281: ...10 0 1 1 0 0 0 H Byte 0111 0 1 1 1 0 0 H Byte 1000 1 0 0 0 0 0 H Byte 1001 1 0 0 1 0 0 H Byte 1010 1 0 1 0 0 0 H Byte 1011 1 0 1 1 0 0 H Byte 1100 1 1 0 0 0 0 H Byte 1101 1 1 0 1 0 0 H Byte 1110 1 1 1 0 0 0 H Byte 1111 1 1 1 1 0 0 H B E Half 0000 0 0 0 0 0 1 G H B E Half 0001 0 0 0 1 1 01 G H B E Half 0010 0 0 1 0 0 1 G H B E Half 0011 0 0 1 1 1 1 1 G H B E Half 0100 0 1 0 0 0 1 G H B E Half 0101 ...

Page 282: ... 0 1 1 0 1 H G L E Half 1010 1 0 1 0 0 1 H G L E Half 1011 1 0 1 1 1 1 1 H G L E Half 1100 1 1 0 0 0 1 H G L E Half 1101 1 1 0 1 1 0 1 H G L E Half 1110 1 1 1 0 0 1 H G L E Half 1111 1 1 1 1 0 1 H 0 0 0 0 next dword 0 0 G B E Word 0000 0 0 0 0 1 0 E F G H B E Word 0001 0 0 0 1 1 1 1 E F G H B E Word 0010 0 0 1 0 1 1 1 E F G H B E Word 0011 0 0 1 1 1 1 1 E F G H B E Word 0100 0 1 0 0 1 0 E F G H B ...

Page 283: ... H L E Word 0000 0 0 0 0 1 0 H G F E L E Word 0001 0 0 0 1 1 1 1 H G F E L E Word 0010 0 0 1 0 1 1 1 H G F E L E Word 0011 0 0 1 1 1 1 1 H G F E L E Word 0100 0 1 0 0 1 0 H G F E L E Word 0101 0 1 0 1 1 0 H G F 1 0 0 0 0 0 E L E Word 0110 0 1 1 0 1 0 H G 1 0 0 0 0 1 F E L E Word 0111 0 1 1 1 1 0 H 1 0 0 0 1 0 G F E L E Word 1000 1 0 0 0 1 0 H G F E L E Word 1001 1 0 0 1 1 1 1 H G F E L E Word 1010...

Page 284: ...tion has completed An external device asserts p_ d i _hready to terminate the transfer Negated A requested transfer operation has not completed p_hresp 2 0 I Transfer response Indicate status of a terminating transfer 000 OKAY Transfer terminated normally 001 ERROR Transfer terminated abnormally See note for assertion 010 Reserved RETRY not supported in AHB Lite protocol 011 Reserved SPLIT not sup...

Page 285: ...pt request has not been signaled Timing Not internally synchronized by the core It must meet setup and hold time constraints relative to m_clk when the core clock is running Assertion Level sensitive must remain asserted to be guaranteed recognition p_critint_b I Critical input interrupt request Critical input interrupt request to the core Masked by MSR CE State Meaning Asserted Critical input int...

Page 286: ...iven to a valid value when either signal is asserted unless p_avec_b is also asserted If p_avec_b is asserted these inputs are not used Assertion Level sensitive must remain asserted to guarantee correct recognition Must be asserted concurrently with p_extint_b and p_critint_b when used p_iack O Interrupt vector acknowledge Interrupt vector acknowledge indicator to allow external interrupt control...

Page 287: ...WIS 1 and TCR WIE 1 or TSR DIS 1 and TCR DIE 1 or TSR FIS 1 and TCR FIE 1 May be used to exit low power operation or for other system purposes State Meaning Asserted An internal timer facility unit is generating an interrupt request Negated An internal timer facility unit is not generating an interrupt request Table 7 13 Descriptions of Processor Reservation Signals Signal I O Signal Description p...

Page 288: ...e exception 00010xx Instruction squashed 01000xx Processor in halted state 01001xx Processor in stopped state 01010xx Processor in debug mode1 01011xx Processor in checkstop state 10000sm Complete instruction2 3 1000100 Complete lmw or stmw 1000101 Complete e_lmw or e_stmw 1001000 Complete isync 1001011 Complete se_isync 100110m Complete lwarx or stwcx 3 1100000 Complete branch instruction bc bcl ...

Page 289: ...or has not indicated a checkstop condition 1 As reflected on the cpu_dbgack internal state signal 2 Except rfi rfci rfdi lmw stmw lwarx stwcx isync isel se_rfi se_rfci se_rfdi e_lmw e_stmw se_isel and change of flow instructions 3 s instruction size 0 32 bit 1 16 bit m 0 for Book E page 1 for VLE page Table 7 16 Descriptions of Power Management Control Signals Signal I O Signal Description p_halt ...

Page 290: ...pplicable from a low power state State Meaning Asserted Asserts whenever one of the following occurs A valid pending interrupt is detected by the core A request to enter debug mode is made by setting the OCR DR or via the assertion of jd_de_b or p_ude The processor is in a debug session and jd_debug_b is asserted A request to enable m_clk has been made by setting OCR WKUP Timing See Section 7 5 5 ...

Page 291: ...zed by the core and must meet setup and hold time constraints relative to m_clk when the core clock is running p_devt2 I External debug event 2 Used to request an external debug event If the core clock is disabled this signal is not recognized In addition only a transition from negated to asserted state of p_devt2 causes an event to occur It is intended to signal core related events generated whil...

Page 292: ...gister or memory accesses See Section 9 5 4 OnCE Interface Signals State Meaning Asserted Asserted when the processor enters debug mode It remains asserted for the duration of a debug session that is during OnCE single step executions jd_de_b I Debug request Normally the input from the top level DE_b open drain bidirectional I O cell See Section 9 5 4 OnCE Interface Signals State Meaning Asserted ...

Page 293: ...utput nex_mseo_b 1 0 O Nexus3 message start end output Table 7 21 JTAG Primary Interface Signals Signal Name Type Description j_trst_b I JTAG test reset j_tclk I JTAG test clock j_tms I JTAG test mode select j_tdi I JTAG test data input j_tdo O Test data out to master controller or pad j_tdo_en O Enables TDO output buffer j_tdo_en is asserted when the TAP controller is in the shift_dr or shift_ir ...

Page 294: ...s the TAP controller is in update IR state j_capture_dr O Indicates the TAP controller is in the capture DR state j_shift_dr O Indicates the TAP controller is in shift DR state j_update_gp_reg O Updates JTAG controller general purpose data register j_gp_regsel 0 11 O General purpose external JTAG register select j_en_once_regsel O External enable OnCE register select j_key_in I Serial data from ex...

Page 295: ...ignal Name Type RS j_gp_regsel 0 O 0x70 j_gp_regsel 1 O 0x71 j_gp_regsel 2 O 0x72 j_gp_regsel 3 O 0x73 j_gp_regsel 4 O 0x74 j_gp_regsel 5 O 0x75 j_gp_regsel 6 O 0x76 j_gp_regsel 7 O 0x77 j_gp_regsel 8 O 0x78 j_gp_regsel 9 O 0x79 j_gp_regsel 10 O 0x7A j_gp_regsel 11 O 0x7B j_en_once_regsel O Enable once register select This control signal can be used by external security logic to help control jd_en...

Page 296: ...o j_tdo j_key_in I Key data in Receives serial data from logic to indicate a key or other value to be scanned out in the Shift_IR state when the current value in the IR is the Enable_OnCE instruction This input is provided to assist in implementing security logic outside of the core which conditionally asserts jd_en_once During the Shift_IR state when jd_en_once is negated this input is sampled on...

Page 297: ... the JTAG ID signals Table 7 23 JTAG Register ID Fields Bit Field Type Description Value 31 28 Variable Version number Variable 27 22 Fixed Design center number e200z3 01_1111 21 12 Variable Sequence number Variable 11 1 Fixed Motorola manufacturer ID 000_0000_1110 0 Fixed JTAG ID register identification bit 1 Table 7 24 JTAG ID Register Inputs Signal Name Type Description j_id_sequence 0 1 I JTAG...

Page 298: ...ign or zero extension and forwarding Table 7 26 Internal Signal Descriptions Signal Name Description p_addr 0 31 Address bus Provides the address for a bus transfer p_ta_b Transfer acknowledge Indicates completion of a requested data transfer operation An external device asserts p_ta_b to terminate the transfer For the core to accept the transfer as successful p_tea_b must remain high while p_ta_b...

Page 299: ...t bus cycle has an error when a fault is detected ERROR assertion requires a 2 cycle response In the first cycle of the response p_hresp 2 0 are driven to indicate ERROR and p_ d i _hready must be negated During the following cycle the ERROR response must continue to be driven and p_ d i _hready must be asserted When the core recognizes a bus error condition for an access at the end of the first c...

Page 300: ... indicate that a transfer is being requested Because the bus is currently idle 0 transfers outstanding the first read request to addrx is considered taken at the end of C1 The default slave drives a ready OKAY response for the current idle cycle Clock 2 C2 During C2 the addrx memory access takes place using the address and attribute values that were driven during C1 to enable reading of 1 or more ...

Page 301: ...ttribute signals are undefined 7 5 1 2 Read Transfer with Wait State Figure 7 4 shows an example of wait state operation Because signal p_ d i _hready for the first request addrx is not asserted during C2 a wait state is inserted until p_ d i _hready is recognized during C3 Meanwhile a subsequent request was generated by the CPU for addry which is not taken in C2 because the previous transaction i...

Page 302: ...t p_ d i _htrans NONSEQ during C1 to indicate that a transfer is being requested Because the bus is idle 0 transfers outstanding the first read request to addrx is considered taken at the end of C1 The default slave drives a ready OKAY response for the current idle cycle Clock 2 C2 During C2 the write data for the access is driven and the addrx memory access occurs using the address and attribute ...

Page 303: ...te Transfer with Wait States Figure 7 6 shows an example write wait state operation Because p_ d i _hready for the first request addrx is not asserted during C2 a wait state is inserted until p_ d i _hready is recognized during C3 Figure 7 6 Write with Wait state Single Cycle Writes Full Pipelining Meanwhile the core generates a subsequent request for addry which is not taken in C2 because the pre...

Page 304: ...e first read access addrx During C3 a request is generated for a write to addry which is taken at the end of C3 because the second access is terminating Data for the addrz write cycle is driven in C4 the cycle after the access is taken and a ready OKAY response is signaled to complete the write cycle to addrz Figure 7 8 shows another sequence of read and write cycles This example shows an interlea...

Page 305: ...ven in C3 the cycle after the access is taken Also during C3 a request is generated for a read to addrz which is taken at the end of C3 because the write access is terminating During C4 the addry write access is terminated and no further access is requested Figure 7 9 shows another sequence of read and write cycles In this example reads incur a single wait state nonseq nonseq nonseq idle addr x ad...

Page 306: ... during C4 for the second read access addry During C5 the request for a write to addrz is taken because the second access is terminating Data for the addrz write cycle is driven in C6 the cycle after the access is taken During C6 the addrz write access is terminated and the addrw write request is taken During C7 data for the addrw write access is driven and a ready OKAY response is asserted to com...

Page 307: ...s not taken at the end of C5 because the second read access is not terminating and it continues to drive the address and attributes into cycle C6 During C6 the addrz read access is terminated and the addrw write access is taken In cycle C7 data for the addrw write access is driven During C7 a ready OKAY response is asserted to complete the write cycle to addrw No further accesses are requested so ...

Page 308: ...nd portion of the misaligned read transfer request is made during C2 to addrx which is aligned to the next higher 64 bit boundary and because the first portion of the misaligned access is completing it is taken at the end of C2 The p_ d i _htrans signals indicate NONSEQ The size value driven is the size of the remaining bytes of data in the misaligned read rounded up for the 3 byte case to the nex...

Page 309: ...C1 to enable writing of one or more bytes of memory The second portion of the misaligned write transfer request is made during C2 to addrx which is aligned to the next higher 64 bit boundary and because the first portion of the misaligned access is completing it is taken at the end of C2 The p_ d i _htrans signals indicate NONSEQ The size value driven is the size of the remaining bytes of data in ...

Page 310: ...uctor Figure 7 13 Misaligned Write Single Cycle Read Transfer Full Pipelining nonseq nonseq nonseq idle addr x addr x addr y single single single data y data x data x okay okay okay okay 1 2 3 4 5 m_clk p_htrans p_addr p_hprot p_hsize p_hbstrb etc p_hburst p_hunalign p_hwrite p_hrdata p_hwdata p_hready p_hresp ...

Page 311: ...als are asserted The burst address is aligned to a 64 bit boundary and increments by double words Note that in this example four beats are shown but in operation the burst may be of any length including only a single beat NOTE Bursts can be interrupted immediately at any time and can be followed by any type of cycle No idle cycle is required nonseq seq seq seq addr x addr x 8 addr x 16 addr x 24 I...

Page 312: ...sfer Figure 7 15 Burst Read with Wait state Transfer The first cycle of the burst incurs a single wait state nonseq seq seq seq addr x addr x 8 addr x 16 addr x 24 incr data x data x 8 data x 16 data x 24 okay okay okay okay okay okay Burst Read with wait state 1 2 3 4 5 6 7 m_clk p_htrans p_addr p_hprot p_hsize p_hbstrb etc p_hburst p_hunalign p_hwrite p_hrdata p_hwdata p_hready p_hresp ...

Page 313: ...unctional timing for a burst write transfer Figure 7 16 Burst Write Transfer nonseq seq seq seq addr x addr x 8 addr x 16 addr x 24 incr data x data x 8 data x 16 data x 24 okay okay okay okay okay Burst Write 1 2 3 4 5 6 m_clk p_htrans p_addr p_hprot p_hsize p_hbstrb etc p_hburst p_hunalign p_hwrite p_hrdata p_hwdata p_hready p_hresp ...

Page 314: ... Transfer The first cycle of the burst incurs a single wait state Data for the second beat of the burst is valid the cycle after the second beat is taken nonseq seq seq seq addr x addr x 8 addr x 16 addr x 24 incr data x data x 8 data x 16 data x 24 okay okay okay okay okay okay Burst Write with Wait state 1 2 3 4 5 6 7 m_clk p_htrans p_addr p_hprot p_hsize p_hbstrb etc p_hburst p_hunalign p_hwrit...

Page 315: ...long and is followed immediately by a second burst which is unrelated to the first NOTE Bursts may be of any length including a single beat and may be followed immediately by any type of transfer No idle cycles are required nonseq seq nonseq seq addr x addr x 8 addr y addr y 8 incr data x data x 8 data y data y 8 okay okay okay okay okay Burst Read 1 2 3 4 5 6 m_clk p_htrans p_addr p_hprot p_hsize...

Page 316: ...urst transfer Figure 7 19 Burst Read with Wait State Transfer Retraction The first cycle of the burst incurs a single wait state and the burst is replaced by another burst nonseq seq seq seq idle addr x addr y 8 addr y 16 incr data x data y data y 8 data y 16 okay okay okay okay okay okay Burst Read with wait state 1 2 3 4 5 6 7 m_clk p_htrans p_addr p_hprot p_hsize p_hbstrb etc p_hburst p_hunalig...

Page 317: ... request addrx is not asserted during C2 so a wait state is inserted during C3 until p_ d i _hready is recognized Meanwhile a subsequent request has been generated by the CPU for addry which is not taken in C2 since the previous transaction is still outstanding The address and transfer attributes are retracted in cycle C3 and a new access request to addrz is requested and are taken at the end of C...

Page 318: ...ansfer with Wait State Address Retraction nonseq nonseq nonseq idle addr x addr y addr w single single single data x data z data w okay okay okay okay okay Read with wait state address retraction 1 2 3 4 5 6 m_clk p_htrans p_addr p_hprot p_hsize p_hbstrb etc p_hburst p_hunalign p_hwrite p_hrdata p_hwdata p_hready p_hresp addr z nonseq ...

Page 319: ...ination is a two cycle termination the first cycle consists of signaling the ERROR response on p_ d i _hresp 2 0 while holding p_ d i _hready negated and during the second cycle asserting p_ d i _hready while continuing to drive the ERROR response on p_ d i _hresp 2 0 This 2 cycle termination allows the BIU to retract a pending access if it desires to do so p_ d i _htrans may be driven to IDLE dur...

Page 320: ...s undefined In this example of error termination the CPU continues to request an access to addry It is taken at the end of C3 During C4 read data is supplied for the addry read and the access is terminated normally during C4 Also during C4 a request is generated for a write to addrz which is taken at the end of C4 because the second access is terminating Data for the addrz write cycle is driven in...

Page 321: ...se protocol p_ d i _hready is asserted during C3 for the first read access addrx while the ERROR encoding remains driven on p_ d i _hresp 2 0 terminating the access The read data bus is undefined In this example of error termination the CPU retracts the requested access to addry by driving p_ d i _htrans signals to the IDLE state during the second cycle of the two cycle error response A different ...

Page 322: ...tion is aborted by the CPU during the second cycle of the two cycle error response and a subsequent burst read access to addrw becomes pending instead Figure 7 26 shows another example of error termination this time on the initial portion of a burst read The aborted burst is followed by a burst write nonseq nonseq idle nonseq seq seq seq idle addr x addr x addr w addr w 8 addr w 16 addr w 24 singl...

Page 323: ...gnal p_hready for the first request addrx is not asserted during C2 so a wait state is inserted during C3 until p_hready is recognized Meanwhile a subsequent request has been generated by the CPU for addry which is not taken in C2 since the previous transaction is still outstanding The address and transfer attributes are retracted in cycle C3 and a new access to addrz is requested and made at the ...

Page 324: ...ansfer with Wait State Address Retraction nonseq nonseq nonseq idle addr x addr y addr w single single single data x data z data w okay okay okay okay okay Read with wait state address retraction 1 2 3 4 5 6 m_clk p_htrans p_addr p_hprot p_hsize p_hbstrb etc p_hburst p_hunalign p_hwrite p_hrdata p_hwdata p_hready p_hresp addr z nonseq ...

Page 325: ...s also possible Address retraction does not occur on a requested write cycle only on read cycles It also may occur any time during a burst cycle 7 5 5 Power Management Figure 7 29 shows the relationship of the wake up control signal p_wakeup to the relevant input signals Figure 7 29 Wakeup Control Signal p_wakeup nonseq seq seq seq idle addr x addr y 8 addr y 16 incr data x data y data y 8 data y ...

Page 326: ...ition during each clock cycle in which either p_extint_b or p_critint_b is asserted p_avec_b and p_voffset 0 15 are required to be in a valid state for the highest priority interrupt requested Figure 7 30 Interrupt Interface Input Signals Figure 7 31 shows the relationship between p_ipend and the interrupt request inputs Note that p_ipend is asserted combinationally from the p_extint_b and p_criti...

Page 327: ...of the p_iack output indicating that the values present on interrupt inputs at the beginning of cycle 2 have been internally latched and committed for servicing Note that the interrupt vector lines have changed to a value of B during cycle 2 and the p_critint_b input has been asserted by the interrupt controller The vector number and autovector signals must be consistent with the higher priority c...

Page 328: ...hange during that interval The CPU asserts the p_iack output to indicate the cycle at which an interrupt is committed to In the following example because the CPU was unable to acknowledge the external input interrupt during cycle 2 due to internal or external execution conditions the critical input request was sampled This case is shown in Figure 7 33 Figure 7 33 Interrupt Acknowledge Operation Ca...

Page 329: ...state if requested and to keep the time base operational if it is using m_clk as the clock source Power down stopped All core functional units except the time base unit and clock control state machine logic are stopped m_clk may be kept running to keep the time base active and to allow quick recovery to full on state Clocks are not running to functional units except to the time base The core reach...

Page 330: ...ht out of low power state by re enabling m_clk The time base facilities may be separately enabled or disabled using combinations of the timer facility control signals p_wakeup O Wakeup Used by external logic to remove the core and system logic from a low power state It can also indicate to the system clock controller that m_clk should be re enabled for debug purposes p_wakeup or other system state...

Page 331: ...etermining how to exit the low power loop if one is used The vectored interrupt capability provided by the core may help determine whether an external hardware interrupt is used to perform the wake up 8 1 4 Debug Considerations for Power Management When a debug request is presented to the core when it is in either the halted or stopped state p_wakeup is asserted and when m_clk is provided to the C...

Page 332: ...Power Management e200z3 Power Architecture Core Reference Manual Rev 2 8 4 Freescale Semiconductor ...

Page 333: ...pports a subset of these defined facilities In addition to the Book E defined facilities the core provides additional flexibility and functionality in the form of debug event counters linked instruction and data breakpoints and sequential debug event detection These features are also available to a hardware based debugger The core also supports an external Nexus real time debug module Real time sy...

Page 334: ...nd data breakpoints The core also provides a configurable debug event counter to allow debug exception generation and a sequential breakpoint control mechanism The core also defines two new debug events critical interrupt taken and critical return for debugging around critical interrupts In addition the core implements the debug auxiliary processing unit APU which when enabled allows debug interru...

Page 335: ...led DBCR0 EDM 1 and DBERC0 IDM 1 only software owned resources may be modified by software and all status bits associated with hardware owned resources will be forced to 0 in DBSR when read by software via a mfspr instruction Hardware always has full access to all registers and all register fields through the OnCE register access mechanism and it is up to the debug firmware to properly implement m...

Page 336: ...ug control register 1 309 R W Yes No DBCR2 Debug control register 2 310 R W Yes No DBCR3 Debug control register 3 561 R W Yes Yes DBCR4 Debug control register 4 563 R W Yes Yes DVC1 Data value compare 1 318 R W Yes Yes DVC2 Data value compare 2 319 R W Yes Yes Pstat Attr Addr j_tdo j_tdo_en j_tdi j_tclk Breakpoint and Trace Logic Pipeline Information j_tms dbg_dbgrq cpu_dbgack jd_watchpt 0 n inter...

Page 337: ...set to indicate that an exception bit in the DBSR was set while debug interrupts were disabled The debug interrupt handler software can use this bit to determine whether DSRR0 holds the address associated with the instruction causing the debug exception or the address of the instruction that enabled a delayed debug interrupt by setting MSR DE An mtmsr or mtdbcr0 which causes both MSR DE and DBCR0 ...

Page 338: ...xternal debug events DEVT1 and DEVT2 The critical interrupt taken debug event CIRPT The critical return debug event CRET The core debug framework supports most of these event types The following Book E defined functionality is not supported Instruction address compare and data address compare real address mode Data value compare mode A brief description of each of the debug event types is shown in...

Page 339: ...ccess with an address that meets the criteria specified in DBCR0 DBCR2 DAC1 and DAC2 Data address compares may specify user supervisor mode and data space MSR DS along with an effective address masked effective address or range of effective addresses for comparison This event can occur and be recorded in DBSR regardless of the setting of MSR DE Two address compare values DAC1 and DAC2 are provided...

Page 340: ...2 control bits If data address compare debug events are used to control or modify operation of the debug counter linking is also available even though DBCR0 may not have enabled IAC or DAC events Also instruction address compare events that are linked may still affect the debug counter if enabled to and may be used to either trigger a counter or be counted in contrast to being blocked from affecti...

Page 341: ...bug interrupt is taken with SRR0 pointing to the instruction following the instruction that generated the SPEFPU round exception and DSRR0 points to the round exception handler In addition to occurring when DBCR0 IDM 1 this circumstance can also occur when DBCR0 EDM 1 Note Instruction complete debug events are not generated by the execution of an instruction that sets MSR DE while DBCR0 ICMP 1 nor...

Page 342: ...n debug event occurs the DBSR CRET bit is set to record the debug exception If MSR DE 0 and DBCR0 EDM 0 at the time of the execution of the rfci that is before the MSR is updated by the rfci DBSR IDE is also set to record the imprecise debug event If MSR DE 1 at the time of the execution of the rfci a debug interrupt occurs provided no higher priority exception is enabled to cause an interrupt Deb...

Page 343: ...events are blocked and watchpoints are blocked Due to clock domain design the CPU clock m_clk must be active for writes to be performed to debug registers other than the OnCE command register OCMD the OnCE control register OCR or DBCR0 EDM Register read data is synchronized back to the j_tclk clock domain The OnCE control register provides the capability of signaling the system level clock control...

Page 344: ...nCE TAP controller and associated enabling logic are designed to allow concatenation with an existing JTAG controller if one is present in the system Thus the core module can be easily integrated with existing JTAG designs or as a stand alone controller To enable full OnCE operation the jd_enable_once input signal must be asserted In some system integrations this is automatic since the input will ...

Page 345: ...o debug mode and scanning instructions and data into and out of the core CPU scan chain CPUSCR execution of scanned instructions by the core is used as the method for accessing required data Memory locations may be read by scanning a load instruction into the core that references the desired memory location executing the load instruction and then scanning out the result of the load Other resources...

Page 346: ...red before executing each Go Exit or Go NoExit command 9 5 2 JTAG OnCE Signals The JTAG OnCE interface is used to transfer OnCE instructions and data to the OnCE control block Depending on the resource being accessed the CPU may need to be placed in debug mode For resources outside the CPU block and contained in the OnCE block the processor is not disturbed and may continue execution If a processo...

Page 347: ... sections describe additional OnCE interface signals to other external blocks such as a Nexus controller and external blocks that may need information pertaining to debug operation Table 9 4 OnCE Internal Interface Signals Signal Name I O Description CPU Debug Request dbg_dbgrq O The dbg_dbgrq signal is set by the OnCE control logic to request the CPU to enter the debug state It may be set for a n...

Page 348: ... operation to an external command controller when output The assertion of this pin by a command controller causes the CPU core to finish the current instruction being executed save the instruction pipeline information enter debug mode and wait for commands to be entered If DE_b was used to enter debug mode DE_b must be negated after the OnCE controller responds with an acknowledge and before sendi...

Page 349: ..._on is used to indicate that the CPU s m_clk input is active This input signal is expected to be driven by system logic external to the core is synchronized to the j_tclk scan clock clock domain and presented as a status flag on the j_tdo output during the Shift IR state External firmware may use this signal to ensure proper scan sequences occur to access debug resources in the m_clk clock domain ...

Page 350: ...l on the jd_mclk_on input signal after capture by j_tclk 0 Inactive state 1 Active state 1 ERR Error Used to indicate that an error condition occurred during attempted execution of the last single stepped instruction Go NoExit with CPUSCR or no register selected in OCMD and that the instruction may not have executed properly This can occur if an interrupt all classes including external critical ma...

Page 351: ...ugh the PC FIFO pointer is only guaranteed to be updated when R W 1 In addition it is ignored for all bypass operations When performing writes most registers are sampled in the Capture DR state into a 32 bit shift register and subsequently shifted out on j_tdo during the first 32 clocks of Shift DR 1 GO Go If the GO bit is set the chip executes the instruction which resides in the IR register in t...

Page 352: ... select Defines which register is the source for the read or the destination for the write operation Table 9 9 indicates the OnCE register addresses Attempted writes to read only registers are ignored 000 0000 000 0001 Reserved 000 0010 JTAG ID read only 000 0011 000 1111 Reserved 001 0000 CPU scan register CPUSCR 001 0001 No register selected bypass 001 0010 OnCE control register OCR 001 0011 001...

Page 353: ...et 0x0000_0000 on m_por j_trst_b or entering test logic reset state Figure 9 7 OnCE Control Register Table 9 8 OnCE Control Register Bit Definitions Bits Name Description 0 7 Reserved should be cleared 8 I_DMDIS Instruction side debug MMU disable control bit May be used to control whether the MMU is enabled or disabled during a debug session for instruction accesses 0 MMU not disabled for debug se...

Page 354: ...ata accesses during a debug session 21 D_DM Data side debug TLB M attribute bit Provides the M attribute bit for data accesses when the MMU is disabled for data accesses during a debug session 22 D_DG Data side debug TLB G attribute bit Provides the G attribute bit for data accesses when the MMU is disabled for data accesses during a debug session 23 D_DE Data side debug TLB E attribute bit Provid...

Page 355: ... performed until consistent values have been obtained on consecutive reads Table 9 9 lists access requirements for OnCE registers Table 9 9 OnCE Register Access Requirements Register Name Access Requirements Notes jd_en_once to be Set DBCR0 EDM 1 m_clk active for Write Access CPU to be Halted for Read Access CPU to be Halted for Write Access Enable_OnCE N N N N Bypass N N N N N CPUSCR Y Y Y Y Y DA...

Page 356: ...ontrol CDACNTL Y N Y Y Y CPU must be in debug mode with clocks running Cache debug access data CDADATA Y N Y Y Y CPU must be in debug mode with clocks running Nexus3 Acces s Y N N N N External GPRs Y N N N N LSRL Select Y N System test logic implementation determines LSRL functionality 1 Writes to these registers while the CPU is running may have unpredictable results due to the pipelined nature o...

Page 357: ...s in the debug scan chain are undefined and the external debug control module is responsible for properly initializing the chain before debug mode is exited In particular interrupt processing associated with reset may not be performed when debug mode is exited thus the debug controller must initialize PC MSR and IR to the image that the processor would have obtained in performing reset exception p...

Page 358: ...uction opcode selected by debug control software By selecting appropriate instructions and controlling the execution of those instructions the results of execution may be used to examine or change memory locations and processor registers The debug control module external to the processor core controls execution by providing a single step capability Once the debug session is complete and normal pro...

Page 359: ...in the restored CPUSCR will determine whether the CPU re enters the waiting state on a go exit 0 CPU was not in the waiting state when debug mode was entered 1 CPU was in the waiting state when debug mode was entered 16 19 PCOFST PC offset field Indicates whether the value in the PC portion of the CPUSCR must be adjusted before exiting debug mode Due to the pipelined nature of the CPU the PC value...

Page 360: ...are 2 event occurred on the fetch of this instruction 1 An instruction address compare 2 event occurred on the fetch of this instruction 26 IRSTAT4 IR status bit 4 Indicates an instruction address compare 3 event status for the IR 0 No instruction address compare 3 event occurred on the fetch of this instruction 1 An instruction address compare 3 event occurred on the fetch of this instruction 27 ...

Page 361: ...resent when the chip entered debug mode It is affected by the operations performed during debug mode and must be restored by the external command controller when the CPU returns to normal mode PC normally points to the instruction contained in the IR portion of CPUSCR If debug firmware wishes to redirect program flow to an arbitrary location the PC and IR should be initialized to correspond to the...

Page 362: ...of the machine state register this register is used This register is affected by the operations performed during debug mode and must be restored by the external command controller when returning to normal mode Chapter 2 Register Model further describes the MSR 9 5 9 Instruction Address FIFO Buffer PC FIFO To assist debugging and keep track of program flow a first in first out FIFO buffer stores th...

Page 363: ...ncremented as FIFO reads are performed The first FIFO read obtains the oldest address and the following FIFO read returns the other addresses from the oldest to the newest the order of execution Updates to the FIFO are frozen whenever the OCMD register contains a command whose RS 0 6 field points to the PC FIFO 010 1101 to allow firmware to read the contents of the PC FIFO without placing the CPU ...

Page 364: ...s are enabled in DBCR0 Watchpoints may occur whenever an associated event would have been posted in the debug status register if enabled No explicit enable bits are provided for watchpoints they are always enabled by definition except during a debug session If not desired the base address values for these events may be programmed to an unused system address MSR DE has no effect on watchpoint gener...

Page 365: ...show one possible scenario for a debugger wishing to use the external debug facilities This simplified flow shows basic operations and does not cover all potential methods in depth Enable external debug mode and initialize debug registers 1 To enable OnCE operation the debugger should ensure that the jd_en_once is set 2 Write a value to OCR in which OCR DR and OCR WKUP are set The TAP controller m...

Page 366: ...e OSR with no register selected GO cleared and determines that the PCU has re entered the debug state and that no ERR condition occurred To return the CPU to normal operation without disabling external debug mode 1 OCR DMDIS and OCR DR should be cleared leaving OCR WKUP set 2 The debugger restores the CPUSCR with a previously saved value of the CPUSCR with appropriate modification of the PC and IR...

Page 367: ...velopment features supported are program trace data trace watchpoint messaging ownership trace and read write access through the JTAG interface The Nexus3 module also supports two class 4 features watchpoint triggering and processor overrun control 10 1 2 Terms and Definitions Table 10 1 contains a set of terms and definitions associated with the Nexus3 module Table 10 1 Terms and Definitions Term...

Page 368: ...data input output Configurable min max message data out pins nex_mdo n 0 One or two message start end out pins nex_mseo_b 1 0 One read write ready pin nex_rdy_b JTAG IR and DR sequence JTAG instruction register IR scan to load an opcode value for selecting a development register The JTAG IR corresponds to the OnCE command register OCMD The selected development register is then accessed through a J...

Page 369: ...e port control register at the SoC level in multiple Nexus implementations For single Nexus implementations this configuration is controlled by DC1 within the e200z3 Nexus3 module In either implementation full port mode FPM maximum number of MDO pins or reduced port mode RPM minimum number of MDO pins is supported This setting should not be changed while the system is running NOTE The configuratio...

Page 370: ...i j_tms j_tclk j_trst_b nex_evto_b nex_rdy_b nex_evti_b nex_mseo1_b N 1 nex_aux_req 1 0 npc_aux_grant 2 Note The nex_aux_req 1 0 npc_aux_grant and nex_aux_busy signals are used for inter module nex_aux_busy communication in a multiple Nexus environment They are not pins on the SoC ext_multi_nex_sel Registers DMA Registers OnCE Debug Breakpoint Watchpoint Control Memory Control Control Status Regis...

Page 371: ...ached by the assertion of the j_trst_b pin or by cycling through the state machine using the j_tms pin The Nexus module can also be disabled if a power on reset POR event occurs If the Nexus3 module nex_mseo0_b nex_mcko Zen Virtual Bus AHB System Bus Nexus2 Block Nexus1 Block w in Zen CPU I O Logic OnCE Debug breakpoint Watchpoint control DMA Read Write Instruction Snoop nex_mdo N 0 j_tdo j_tdi j_...

Page 372: ... Packet Size Bits Packet Type Packet Description Debug status 6 6 Fixed TCODE number 0 0x00 4 4 Fixed Source processor identifier multiple Nexus configuration 8 8 Fixed Debug status register DS 31 24 Ownership trace message 6 6 Fixed TCODE number 2 0x02 4 4 Fixed Source processor identifier multiple Nexus configuration 32 32 Fixed Task process ID tag Program trace Direct branch message 6 6 Fixed T...

Page 373: ...ce processor identifier multiple Nexus configuration 1 8 Variable Number of sequential instructions executed since last taken branch 1 32 Variable Full target address leading zeros truncated Data trace Data write message with synchronization 6 6 Fixed TCODE number 13 0x0D 4 4 Fixed Source processor identifier multiple Nexus configuration 3 3 Fixed Data size Refer to Table 10 6 1 32 Variable Full a...

Page 374: ...tion 10 7 1 Branch Trace Messaging BTM Program trace Indirect branch history message with synchronization 6 6 Fixed TCODE number 29 0x1D See note below 4 4 Fixed Source processor identifier multiple Nexus configuration 1 8 Variable Number of sequential instructions executed since last taken branch 1 32 Variable Full target address leading zero 0 truncated 1 32 Variable Branch predicate instruction...

Page 375: ...0111 Reserved 11000 BTM lost due to collision with higher priority message 11001 11111 Reserved Table 10 4 Resource Code Encodings TCODE 27 Resource Code RCODE Description 0000 Program trace instruction counter reached 255 and was reset 0001 Program trace branch predicate instruction history This type of packet is terminated by a stop bit set after the last history bit Table 10 5 Event Code Encodi...

Page 376: ...3 Nexus2 register access NOTE Nexus3 Nexus2 registers and output signals are numbered using bit 0 as the least significant bit This bit ordering is consistent with the ordering defined by the IEEE ISTO 5001 standard Table 10 7 shows the register map for the Nexus3 Nexus2 module 010 Word 4 bytes 011 Double word 8 bytes 100 String 3 bytes 101 111 Reserved Table 10 7 Nexus3 Nexus2 Register Map Nexus ...

Page 377: ...address1 DTEA1 0x12 R W 0x24 0x25 Data trace end address2 DTEA2 0x13 R W 0x26 0x27 Reserved 0x14 0x3F 0x28 0x7E 0x29 0x7F 1 The CSC and PCR registers are shown in this table as part of the Nexus programmer s model They are only present at the top level SoC Nexus3 Nexus2 controller in a multiple Nexus implementation not in the e200z3 Nexus3 Nexus2 module The SoC s CSC register is readable through N...

Page 378: ...EX Figure 10 4 Port Configuration Register Table 10 9 PCR Field Descriptions Bits Name Description 31 OPC Output port mode control 0 Reduced port mode configuration minimum number of nex_mdo n 0 pins defined by SOC 1 Full port mode configuration maximum number of nex_mdo n 0 pins defined by SOC 30 Reserved 29 MCK_EN MCKO clock enable See note below 0 nex_mcko is disabled 1 nex_mcko is enabled 28 2...

Page 379: ...f nex_mdo n 0 pins defined by SOC 1 Full port mode configuration maximum number of nex_mdo n 0 pins defined by SOC 30 29 MCK_DIV MCKO clock divide ratio See note below 00 nex_mcko is 1x processor clock freq 01 nex_mcko is 1 2x processor clock freq 10 nex_mcko is 1 4x processor clock freq 11 nex_mcko is 1 8x processor clock freq 28 27 EOC EVTO control 00 nex_evto_b upon occurrence of watchpoints co...

Page 380: ...trace 1XX Program trace enabled X1X Data trace enabled not supported in Nexus2 reserved in e200z335 XX1 Ownership trace enabled 31 24 23 0 Field EWC Reset All zeros R W Read Write Number 0x3 Figure 10 6 Development Control Register 2 DC2 Table 10 11 DC2 Field Descriptions Bits Name Description 31 24 EWC EVTO Watchpoint Configuration 00000000No watchpoints trigger nex_evto_b 1xxxxxxxWatchpoint 0 IA...

Page 381: ...d or during runtime RWCS also provides read write access status information see Table 10 14 31 30 28 27 26 25 24 0 Field DBG LPC LPC CHK Reset All zeros R W Read only Number 0x4 Figure 10 7 Development Status Register DS Table 10 12 DS Field Descriptions Bits Name Description 31 DBG e200z3 CPU debug mode status 0 CPU not in debug mode 1 CPU in debug mode jd_debug_b signal asserted 30 28 LPS e200z3...

Page 382: ...rd only in burst mode 100 111 Reserved default to word 26 24 MAP MAP select 000 Primary memory map 001 111 Reserved 23 22 PR Read write access priority 00 Lowest access priority 01 Reserved default to lowest priority 10 Reserved default to lowest priority 11 Highest access priority 21 16 Reserved 15 2 CNT Access control count Number of accesses of word size SZ 1 ERR Read write access error See Tab...

Page 383: ...able 10 15 shows the proper placement of data into the RWD Note that double word transfers require two passes through RWD 31 0 Field Read Write Data Reset All zeros R W Read Write Number 0x9 Figure 10 9 Read Write Access Data Register RWD Table 10 15 RWD data placement for Transfers Transfer Size and Byte Offset RWA 2 0 RWCS SZ RWD 31 24 23 16 15 8 7 0 Byte x x x 0 0 0 X Half x x 0 0 0 1 X X Word ...

Page 384: ...yte 001 0 0 1 AHB 15 8 Byte 010 0 1 0 AHB 23 16 Byte 011 0 1 1 AHB 31 24 Byte 100 1 0 0 AHB 39 32 Byte 101 1 0 1 AHB 47 40 Byte 110 1 1 0 AHB 55 48 Byte 111 1 1 1 AHB 63 56 Half 000 0 0 0 AHB 15 8 AHB 7 0 Half 010 0 1 0 AHB 31 24 AHB 23 16 Half 100 1 0 0 AHB 47 40 AHB 39 32 Half 110 1 1 0 AHB 63 56 AHB 55 48 Word 000 0 0 0 AHB 31 24 AHB 23 16 AHB 15 8 AHB 7 0 Word 100 1 0 0 AHB 63 56 AHB 55 48 AHB...

Page 385: ... watchpoint 0 IAC1 from Nexus1 010 Use watchpoint 1 IAC2 from Nexus1 011 Use watchpoint 2 IAC3 from Nexus1 100 Use watchpoint 3 IAC4 from Nexus1 101 Use watchpoint 4 DAC1 from Nexus1 110 Use watchpoint 5 DAC2 from Nexus1 111 Use watchpoint 6 or 7 DCNT1 or DCNT2 from Nexus1 28 26 PTE Program trace end control 000 Trigger disabled 001 Use watchpoint 0 IAC1 from Nexus1 010 Use watchpoint 1 IAC2 from ...

Page 386: ... DTE Data trace end control not in e200z335 000 Trigger disabled 001 Use watchpoint 0 IAC1 from Nexus1 010 Use watchpoint 1 IAC2 from Nexus1 011 Use watchpoint 2 IAC3 from Nexus1 100 Use watchpoint 3 IAC4 from Nexus1 101 Use watchpoint 4 DAC1 from Nexus1 110 Use watchpoint 5 DAC2 from Nexus1 111 Use watchpoint 6 or 7 DCNT1 or DCNT2 from Nexus1 19 0 Reserved should be cleared 31 30 29 28 27 8 7 6 5...

Page 387: ...TEA 7 RC1 Range control 1 0 Condition trace on address within range 1 Condition trace on address outside of range 6 RC2 Range control 2 0 Condition trace on address within range 1 Condition trace on address outside of range 5 4 Reserved should be cleared 3 DI1 Data access instruction access trace 1 0 Condition trace on data accesses 1 Condition trace on instruction accesses 2 0 Reserved should be ...

Page 388: ...ng writing of a Nexus3 Nexus2 register then requires two passes through the data scan path of the JTAG state machine 12 see Section 10 15 IEEE 1149 1 JTAG RD WR Sequences 1 The first pass through the DR selects the Nexus3 Nexus2 register to be accessed by providing an index see Table 10 7 and the direction read write This is achieved by loading an 8 bit value into the JTAG data register DR This re...

Page 389: ...xus task process ID data is handled in one of the following two ways in order to maintain IEEE ISTO 5001 compliance 1 If the process ID register exists it is updated by the operating system software to provide task process ID information The contents of this register are replicated on the pins of the processor and connected to Nexus The process ID register value can be accessed using the mfspr mts...

Page 390: ...OVC can be set to delay the CPU in order to alleviate but not eliminate potential overrun situations Error information is messaged out in the format shown in Figure 10 17 10 6 4 OTM Flow Ownership trace messages are generated when the operating system writes to the e200z3 process ID register PID0 or the memory mapped ownership trace register OTR The following flow describes the OTM process The pro...

Page 391: ... following information Messaging for taken indirect branches and exceptions includes how many sequential instructions were executed since the last predicate instruction taken indirect branch or exception the unique portion of the branch target address or exception vector address and a branch predicate instruction history field Each bit in the history field represents a direct branch or predicated ...

Page 392: ...m Trace Messages Program tracing can utilize either branch history messages DC1 PTM 1 or traditional direct indirect branch messages DC1 PTM 0 Branch history saves bandwidth and keeps consistency between methods of program trace yet may lose temporal order between BTM messages and other types of messages Since direct branches are not messaged but are instead included in the history field of the in...

Page 393: ... is used in conjunction with the branch history messages The resource full message is generated when the internal branch predicate history buffer is full If synchronization is needed at the time this message is generated the synchronization is delayed until the next branch trace message that is not a resource full message For history buffer overflow the resource full message transmits a resource c...

Page 394: ... significant byte in the development status register Debug status information is sent out in the format shown in Figure 10 22 10 7 2 6 Program Correlation Messages Program correlation messages PCMs are used to correlate events to the program flow that may not be associated with the instruction stream The following events will result in a PCM when program trace is enabled When the CPU enters debug ...

Page 395: ...istory mode when a direct branch results in an execution mode switch into or out of a sequence of VLE instructions a PCM is generated The PCM effectively breaks up any running history information between the two modes of operation so that the history information can be processed by the development tool in the proper context Program correlation is messaged out in the format shown in Figure 10 23 10...

Page 396: ... in nex_evti_b signal if the EIC bits within the DC1 register have enabled this feature Upon direct indirect branch after the sequential instruction counter has expired indicating 255 instructions have occurred between branches Upon direct indirect branch after a BTM message was lost due to an attempted access to a secure memory location for SOCs with security Upon direct indirect branch after a B...

Page 397: ...urs periodically after 255 program trace messages have been queued A direct indirect branch with synchronization message is queued The periodic program trace message counter then resets Event in If the Nexus module is enabled assorting nex_evti_b initiates a direct indirect branch with synchronization message upon the next direct indirect branch if program trace is enabled and the EIC bits of the ...

Page 398: ...t address For the example given in Figure 10 27 assume the previous address A1 0x0003FC01 and the new address A2 0x0003F365 10 7 3 3 Execution Mode Indication In order for a development tool to properly interpret instruction count and history information it must be aware of the execution mode context of that information VLE instructions will be interpreted differently from non VLE instructions Pro...

Page 399: ...on whose predicate condition executed as false as well as on branches not taken This includes indirect as well as direct branches not taken For the evsel instruction two bits are shifted in corresponding to the low element shifted in first and the high element shifted in second 10 7 3 5 Sequential Instruction Count I CNT The I CNT packet is present in all BTM messages For traditional branch messag...

Page 400: ...00 01 00 00 00 00 00 00 10 01 01 10 10 TCODE 4 Source processor 0000 Number of sequential instructions 128 Relative address 0xA5 00 MCKO MSEO_B MDO 1 0 00 11 01 00 00 00 01 01 10 10 01 01 10 TCODE 28 Source processor 0000 Number of sequential instructions 0 Relative address 0xA5 Branch history 010100101 w stop 10 00 MCKO MSEO_B MDO 1 0 Direct Branch Error 11 00 00 00 00 11 00 00 10 00 00 00 01 DBM...

Page 401: ...00z3 virtual data bus This allows for data visibility for e200z3 processors that incorporate a data cache Only e200z3 CPU initiated accesses are traced No DMA accesses to the AHB system bus are traced Data trace messaging can be enabled in one of two ways Setting DC1 TM to enable data trace Using WT DTS to enable data trace on watchpoint hits e200z3 watchpoints are configured within the Nexus1 mod...

Page 402: ...nce emptied an error message is queued The error encoding indicates which types of messages attempted to be queued while the FIFO was being emptied If only a DTM attempts to enter the queue while it is being emptied the error message incorporates the data trace only error encoding 00010 If both OTM and DTM attempt to enter the queue the error message incorporates the OTM and data trace error encod...

Page 403: ...the DC1 register have enabled this feature Upon data trace write read after the previous DTM message was lost due to an attempted access to a secure memory location for SOC s with security Upon data trace write read after the previous DTM message was lost due to a collision entering the FIFO between the DTM message and any of the following watchpoint message ownership trace message branch trace me...

Page 404: ...ror message occurs when a new message cannot be queued due to the message queue being full The FIFO discards messages until it has completely emptied the queue Once emptied an error message is queued The error encoding indicates which type s of messages attempted to be queued while the FIFO was being emptied The next DTM message in the queue will be a data write read with synchronization message P...

Page 405: ...r a misaligned access that crosses a 64 bit boundary the access is broken into two accesses If both accesses are within the data trace range two DTMs are sent one with a size encoding indicating the size of the original access that is word and one with a size encoding for the portion that crossed the boundary that is 3 bytes See Table 3 10 for examples of misaligned accesses Table 10 26 e200z3 Bus...

Page 406: ...a Trace Data Write Message Figure 10 37 Data Trace Data Read with Synchronization Message Figure 10 38 Error Message Data Trace Only Encoded 10101000 00000101 00010100 11101111 11 00 00 01 00 TCODE 5 Source processor 0000 Data size 010 half word Relative address 0xA5 Write data 0xBEEF 11 10111110 MCKO MSEO_B 1 0 MDO 7 0 11000000 00001110 01011001 11010001 11 00 TCODE 14 Source processor 0000 Data ...

Page 407: ... Support for details on watchpoint initialization When these watchpoints occur a watchpoint event signal from the Nexus1 module causes a message to be sent to the queue to be messaged out This message includes the watchpoint number indicating which watchpoint caused the message The occurrence of any of the e200z3 defined watchpoints can be programmed to assert the event out nex_evto_b pin for one ...

Page 408: ...t is being emptied the error message incorporates error encoding 01000 NOTE DC1 OVC can be set to delay the CPU in order to alleviate but not eliminate potential overrun situations Error information is messaged out in the format shown in Figure 10 40 10 9 4 Watchpoint Timing Diagram 2 MDO 1 MSEO Configuration Figure 10 41 Watchpoint Message and Watchpoint Error Message 0100_0000 e200z3 watchpoint ...

Page 409: ... the steps that are required to access memory mapped resources NOTE Read write access can only access memory mapped resources when system reset is de asserted and clocks are running Misaligned accesses are not supported in the e200z3 Nexus3 Nexus2 module 10 10 1 Single Write Access NOTE In the first three steps the registers are initialized using the access method outlined in Section 10 5 Nexus3 N...

Page 410: ... then asserts the nex_rdy_b pin This indicates that the device is ready for the next access 3 Repeat step 3 in Section 10 10 1 Single Write Access until the internal CNT value is zero When this occurs RWCS DV is cleared to indicate the end of the block write access 10 10 3 Block Write Access Burst Mode 1 For a burst block write access follow steps 1 and 2 outlined in Section 10 10 1 Single Write A...

Page 411: ...x0000 or 0x0001 performs a single access 3 The Nexus block then arbitrates for the AHB system bus and the read data is transferred from the AHB to the RWD register When the transfer is completed without error ERR 0 Nexus asserts the nex_rdy_b pin see Table 10 31 for details on nex_rdy_b and sets RWCS DV This indicates that the device is ready for the next access 4 The data can then be read from RW...

Page 412: ...r a burst block read access follow steps 1 and 2 outlined in Section 10 10 4 Single Read Access to initialize the registers using a value of four double words for the CNT field and an SZ field indicating 64 bit access in RWCS 2 The Nexus block then arbitrates for the AHB system bus and the burst read data is transferred from the AHB to the data buffer RWD register For each access within the burst ...

Page 413: ...ndled as described above 2 If a block access is in progress all cycles are not completed and the RWCS register is written The original block access is terminated at the boundary of the nearest completed access a If RWCS AC is set the next read write access begins and the RWD can be written to read from b If RWCS AC is cleared the read write access is terminated at the nearest completed access This...

Page 414: ...ence the OnCE controller state machine j_tms is sampled on the rising edge of j_tclk j_tclk I Test clock Input pin used to synchronize the test logic and control register access through the JTAG OnCE port j_trst_b I Test reset Input pin used to asynchronously initialize the JTAG OnCE controller Table 10 31 Nexus3 Nexus2 Auxiliary Pins Auxiliary Pin I O Description of Auxiliary Pins nex_mcko O Mess...

Page 415: ...n messages provided program trace and data trace are enabled and EIC 00 Debug request to e200z3 Nexus1 module provided EIC 01 and this feature is implemented Table 10 32 Nexus Port Arbitration Signals Nexus Port Arbitration Pins Input Output Description of Arbitration Pins nex_aux_req 1 0 O Nexus auxiliary request Output signals indicating to an SoC level Nexus arbiter a request for access to the ...

Page 416: ...acket is 2x the number of nex_mdo n 0 pins This ensures that a false end of message state is not entered by emitting two consecutive 1s on nex_mseo_b before the actual end of message End of variable length packet 0 1 0 00 01 Message transmission 0s 00s Idle no message 1s 11s Table 10 33 MSEO Pin s Protocol continued nex_mseo_b Function Single nex_mseo_b data serial Dual nex_mseo_b 1 0 data Normal ...

Page 417: ...e dual pin option also allows for consecutive end packet states This can be an advantage when small variable sized packets are transferred NOTE The end message state may also indicate the end of a variable length packet as well as the end of the message when using the dual pin option Normal Transfer End Message nex_mseo_b 1 0 11 nex_mseo_b 1 0 11 nex_mseo_b 1 0 00 nex_mseo_b 1 0 00 nex_mseo_b 1 0 ...

Page 418: ...tration In a multiple Nexus environment the Nexus3 Nexus2 module must arbitrate for the shared Nexus port at the SoC level The request scheme is implemented as a 2 bit request with various levels of priority The priority levels are defined in Table 10 34 below The Nexus3 Nexus2 module receives a 1 bit grant signal npc_aux_grant from the SoC level arbiter When a grant is received the Nexus3 Nexus2 ...

Page 419: ...2 0 Normal transfer 8 I5 I4 1 End packet 9 A1 A0 0 Normal transfer 10 A3 A2 0 Normal transfer 11 A5 A4 0 Normal transfer 12 A7 A6 1 End packet Note During clock 12 the nex_mdo n 0 pins are ignored in the single MSEO case 13 0 0 1 End message 14 T1 T0 0 Start message Table 10 36 Indirect Branch Message Example 8 MDO 2 MSEO 1 1 T0 and S0 are the least significant bits where Tx TCODE number fixed Sx ...

Page 420: ...packet 7 0 0 1 End message Table 10 38 Direct Branch Message Example 8 MDO 2 MSEO 1 1 T0 and I0 are the least significant bits where Tx TCODE number fixed Sx Source processor fixed Ix Number of instructions variable Ax Unique portion of the address variable Clock nex_mdo 7 0 nex_mseo_b 1 0 State 0 X X X X X X X X 1 1 Idle or end of last message 1 S1 S0 T5 T4 T3 T2 T1 T0 0 0 Start message 2 0 0 0 0...

Page 421: ...S2 0 1 End packet 3 D7 D6 D5 D4 D3 D2 D1 D0 1 1 End packet end message Table 10 41 Accessing Internal Nexus3 Nexus2 Registers through JTAG OnCE Step TMS Pin Description 1 1 IDLE SELECT DR_SCAN 2 0 SELECT DR_SCAN CAPTURE DR Nexus command register value loaded in shifter 3 0 CAPTURE DR SHIFT DR 4 0 7 TCK clocks issued to shift in direction RD WR bit and first 6 bits of Nexus register address 5 1 SHI...

Page 422: ... command write to read write control status register RWCS 4 37 Write RWCS initialize read access mode and CNT value data input on TDI 5 Wait for falling edge of nex_rdy_b pin 6 13 Nexus command read read write access data register RWD 7 37 Read RWD data output on TDO 8 If CNT 0 go back to Step 5 Table 10 43 Accessing Memory Mapped Resources Writes Step TCLK clocks Description 1 13 Nexus command wr...

Page 423: ...end signal Changed from Indicates whether a p_extint_b or p_critint_b interrupt request or an enabled timer facility interrupt was recognized internally by the core is enabled by the appropriate MSR bit and is asserted combinationally from the interrupt request inputs to Indicates whether a p_extint_b or p_critint_b interrupt request or an enabled timer facility interrupt was recognized internally...

Page 424: ...Revision History e200z3 Power Architecture Core Reference Manual Rev 2 A 2 Freescale Semiconductor ...

Page 425: ...e transactions are indivisible The PowerPC architecture implements atomic accesses through the lwarx stwcx instruction pair B Biased exponent An exponent whose range of values is shifted by a constant bias Typically a bias is provided to allow a range of positive values to express a range that includes both positive and negative values Big endian A byte ordering method in memory where the address ...

Page 426: ...one page In PowerPC processors cache coherency is maintained on a cache block basis Note that the term cache block is often used interchangeably with cache line Cache coherency An attribute wherein an accurate and common view of memory is provided to all devices that share the same memory system Caches are coherent if a processor performing a read from its cache is supplied with data corresponding...

Page 427: ...format s minimum and whose explicit or implicit leading significand bit is zero E Effective address EA The 32 bit address specified for a load store or an instruction fetch This address is then submitted to the MMU for translation to either a physical memory address or an I O address Exception A condition that if enabled generates an interrupt Execution synchronization A mechanism by which all ins...

Page 428: ...e instructions not defined by the PowerPC architecture In addition for 32 bit implementations instructions that are defined only for 64 bit implementations are considered to be illegal instructions For 64 bit implementations instructions that are defined only for 32 bit implementations are considered to be illegal instructions Implementation A particular processor that conforms to the PowerPC arch...

Page 429: ...od in memory where the address n of a word corresponds to the least significant byte In an addressed memory word the bytes are ordered left to right 3 2 1 0 with 3 being the most significant byte See Big endian M Mantissa The decimal part of logarithm Memory access ordering The specific order in which the processor performs load and store memory accesses and the order in which those accesses compl...

Page 430: ...instructions to be issued and completed in an order that differs from their sequence in the instruction stream Overflow An condition that occurs during arithmetic operations when the result cannot be stored accurately in the destination register s For example if two 32 bit numbers are multiplied the result may not be representable in 32 bits Because 32 bit registers cannot represent this sum an ov...

Page 431: ...am is stopped at the decode stage and executing instructions are allowed to complete to create a controlled context for instructions that may be affected by out of order parallel execution See Context synchronization Quiet NaN A type of NaN that can propagate through most arithmetic operations without signaling interrupts A quiet NaN is used to represent the results of certain invalid operations s...

Page 432: ...e term set may also be used to generally describe the updating of a bit or bit field Set n A subdivision of a cache Cacheable data can be stored in a given location in one of the sets typically corresponding to its lower order address bits Because several memory locations can map to the same location cached data is typically placed in the set whose cache block corresponding to that address was use...

Page 433: ...r example when instructions are dispatched they are assigned a place in the CQ at the same time they are passed to the execute stage They can be said to occupy both the complete and execute stages in the same clock cycle Stall An occurrence when an instruction cannot proceed to the next stage Static branch prediction Mechanism by which software for example compilers can hint to the machine hardwar...

Page 434: ...ecture that describes the memory model for an environment in which multiple devices can access memory defines aspects of the cache model defines cache control instructions and defines the time base facility from a user level perspective Implementations that conform to the PowerPC VEA also adhere to the UISA but may not necessarily adhere to the OEA Virtual address An intermediate address used in t...

Page 435: ... 9 32 Carry bit for integer operations 2 10 Completion queue CQ Glossary 3 Context switching registers 2 60 Conventions notational 1 xxix terminology 1 xxx Core complex interface internal signal definitions 7 4 CPUCSR CPU status and control scan chain reg 9 24 CR condition register 2 11 2 14 CR setting for compare instructions 2 13 CR setting for integer instructions 2 12 CR setting for store cond...

Page 436: ...sters 10 20 DTSA1 2 data trace start address 1 2 reg s 10 20 E e200z6 overview 1 1 auxiliary processing units APUs machine check rfmci instruction 1 6 single precision floating point SPFP instructions 1 6 block diagram 1 2 comparisons with legacy PowerPC devices 1 13 exception handling 1 14 instruction set compatibility 1 13 little endian mode 1 15 memory management unit MMU and TLBs 1 14 reset op...

Page 437: ...P single precision floating point APUs floating point 3 14 3 15 stwcx 3 5 4 32 unsupported 3 2 Integer exception register XER 2 10 Interrupt classes categories 1 8 Interrupt handling classes of interrupts 4 2 critical non critical 4 2 precise imprecise 4 2 synchronous asynchronous interrupts 4 2 definition 4 1 interrupt processing 4 30 interrupt types alignment interrupt 4 15 auxiliary processor u...

Page 438: ...ory management overview 1 14 Memory management unit MMU address space 5 4 address translation address space 5 4 effective to real translation 5 2 field comparisons 5 5 page size effective address bits compared 5 5 page size real address generation 5 5 translation flow 5 3 5 4 virtual addresses 5 4 entry compare process 5 5 debug implications 5 15 effective addresses 5 4 features 5 1 MMU assist reg...

Page 439: ...n count I CNT 10 32 program trace timing diagrams 10 33 10 34 using branch history messages 10 25 using tranditional program trace messages 10 25 data trace messaging DTM message formats 10 34 10 37 data read messages 10 35 data trace synchronization messages 10 36 data write messages 10 34 DTM overflow error messages 10 35 operation data access instruction access data tracing 10 38 data trace win...

Page 440: ...14 link register LR 2 14 BTB branch unit control and status BUCSR 2 51 cache control L1 cache configuration L1CFG0 2 51 context switching fast context control register CTXCR 2 60 debug 2 33 2 47 9 4 control state register CTL 9 25 CPU status and control scan chain CPUSCR 9 24 data address compare DAC1 DAC4 2 34 debug control and status registers DBCR0 DBCR3 2 34 2 46 debug counter register DBCNT 2...

Page 441: ...rfci 4 32 rfdi 3 6 4 32 rfi 4 32 RWA read write access address register 10 17 RWCS read write access control status register 10 14 RWD read write access data register 10 16 S Scan chain 9 24 Signal processing engine SPE APU registers accumulator 2 18 SPEFSCR 2 15 Signals core signal definitions 7 4 debug OnCE controller signals 9 13 external 9 14 internal 9 14 Nexus3 interface 10 46 protocol 10 48...

Page 442: ...atures programming model 5 1 miss exception not taken 5 8 registers 5 2 True little endian pages 2 57 TSR timer status register 2 29 U Unsupported instructions and instruction forms 3 2 User instruction set architecture UISA description 1 xxvii USPRG0 user SPR 2 26 W Watchdog timer watchdog timer interrupt 4 19 see also Interrupt handling Watchpoint messaging see Nexus3 module Watchpoint signaling...

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