Overview
MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3
Freescale Semiconductor
1-9
signed fractional operands, and a complete set of instructions to process these data types. The MAC
provides support for execution of DSP operations within the context of a single processor at a minimal
hardware cost.
1.2.2
Integrated Debug Module
The ColdFire processor core debug interface is provided to support system debugging in conjunction with
low-cost debug and emulator development tools. Through a standard debug interface, users can access
debug information and real-time tracing capability is provided on 100-lead packages. This allows the
processor and system to be debugged at full speed without the need for costly in-circuit emulators.
The on-chip breakpoint resources include a total of nine programmable 32-bit registers: an address and an
address mask register, a data and a data mask register, four PC registers, and one PC mask register. These
registers can be accessed through the dedicated debug serial communication channel or from the
processor’s supervisor mode programming model. The breakpoint registers can be configured to generate
triggers by combining the address, data, and PC conditions in a variety of single- or dual-level definitions.
The trigger event can be programmed to generate a processor halt or initiate a debug interrupt exception.
The MCF5213 implements revision B+ of the ColdFire Debug Architecture.
The MCF5213’s interrupt servicing options during emulator mode allow real-time critical interrupt service
routines to be serviced while processing a debug interrupt event, thereby ensuring that the system
continues to operate even during debugging.
To support program trace, the V2 debug module provides processor status (PST[3:0]) and debug data
(DDATA[3:0]) ports. These buses and the PSTCLK output provide execution status, captured operand
data, and branch target addresses defining processor activity at the CPU’s clock rate. The MCF5213
includes a new debug signal, ALLPST. This signal is the logical ‘AND’ of the processor status (PST[3:0])
signals and is useful for detecting when the processor is in a halted state (PST[3:0] = 1111).
The full debug/trace interface is available only on the 100-pin packages. However, every product features
the dedicated debug serial communication channel (DSI, DSO, DSCLK) and the ALLPST signal.
1.2.3
JTAG
The MCF5213 supports circuit board test strategies based on the Test Technology Committee of IEEE and
the Joint Test Action Group (JTAG). The test logic includes a test access port (TAP) consisting of a 16-state
controller, an instruction register, and three test registers (a 1-bit bypass register, a 256-bit boundary-scan
register, and a 32-bit ID register). The boundary scan register links the device’s pins into one shift register.
Test logic, implemented using static logic design, is independent of the device system logic.
The MCF5213 implementation can do the following:
•
Perform boundary-scan operations to test circuit board electrical continuity
•
Sample
MCF5213
system
pins
during
operation and transparently shift out the result
in the
boundary scan register
•
Bypass the MCF5213 for a given circuit board test by effectively reducing the
boundary-scan
register to a single bit
•
Disable the output drive to pins during circuit-board testing
