Pulse-Width Modulation (PWM) Module
MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3
24-6
Freescale Semiconductor
24.2.5
PWM Center Align Enable Register (PWMCAE)
The PWMCAE register contains four control bits for the selection of center-aligned outputs or left-aligned
outputs for each PWM channel. Write these bits only when the corresponding channel is disabled. See
Section 24.3.2.5, “Left-Aligned Outputs”
Section 24.3.2.6, “Center-Aligned Outputs”
for a more
detailed description of the PWM output modes.
24.2.6
PWM Control Register (PWMCTL)
The PWMCTL register provides various control of the PWM module. Change the CON
n(n+1)
bits only
when both corresponding channels are disabled. See
Section 24.3.2.7, “PWM 16-Bit Functions”
for a
more detailed description of the concatenation function.
3
Reserved, should be cleared.
2–0
PCKA
Clock A prescaler select. These three bits control the rate of Clock A which can be used for PWM channels 1 and 5.
IPSBAR
Offset:
0x1B_0004 (PWMCAE)
Access: User Read/Write
7
6
5
4
3
2
1
0
R
CAE7
0
CAE5
0
CAE3
0
CAE1
0
W
Reset:
0
0
0
0
0
0
0
0
Figure 24-6. PWM Center Align Enable Register (PWMCAE)
Table 24-6. PWMCAE Field Descriptions
Field
Description
7,5,3,1
CAE
n
Center align enable for channel
n
. The even-numbered channels’ center align enable has no effect when the
corresponding PWMCTL[CON
n(n+1)
] bit is set. For example, if PWMCTL[CON01] equals 1, PWMCAE[CAE0] has
no affect.
0 Channel
n
operates in left-aligned output mode
1 Channel
n
operates in center-aligned output mode
6,4,2,0
Reserved, should be cleared.
Table 24-5. PWMPRCLK Field Descriptions (continued)
Field
Description
PCKA
Clock A Rate
000
Internal bus clock
÷
2
0
001
Internal bus clock
÷
2
1
...
...
111
Internal bus clock
÷
2
7
