Pulse-Width Modulation (PWM) Module
MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3
24-4
Freescale Semiconductor
24.2.3
PWM Clock Select Register (PWMCLK)
Each PWM channel has the capability of selecting one of two clocks. For channels 1 and 5, the clock
choices are clock A or SA. For channels 3 and 7, the choices are clock B or SB. The clock selection is done
with the below PWMCLK[PCLK
n
] control bits. If a clock select is changed while a PWM signal is being
generated, a truncated or stretched pulse can occur during the transition.
IPSBAR
Offset:
0x1B_0001 (PWMPOL)
Access: User Read/Write
7
6
5
4
3
2
1
0
R
PPOL7
0
PPOL5
0
PPOL3
0
PPOL1
0
W
Reset:
0
0
0
0
0
0
0
0
Figure 24-3. PWM Polarity Register (PWMPOL)
Table 24-3. PWMPOL Field Descriptions
Field
Description
7,5,3,1
PPOL
n
PWM channel
n
polarity.
0 PWM channel
n
output is low at the beginning of the period, then goes high when the duty count is reached
1 PWM channel
n
output is high at the beginning of the period, then goes low when the duty count is reached
6,4,2,0
Reserved, should be cleared.
IPSBAR
Offset:
0x1B_0002 (PWMCLK)
Access: User Read/Write
7
6
5
4
3
2
1
0
R
PCLK7
0
PCLK5
0
PCLK3
0
PCLK1
0
W
Reset:
0
0
0
0
0
0
0
0
Figure 24-4. PWM Clock Select Register (PWMCLK)
