DMA Timers (DTIM0–DTIM3)
MCF5213 ColdFire® Integrated Microcontroller Reference Manual, Rev. 3
Freescale Semiconductor
19-7
19.2.5
DMA Timer Capture Registers (DTCR
n
)
Each DTCR
n
latches the corresponding DTCN
n
value during a capture operation when an edge occurs on
DT
n
IN, as programmed in DTMR
n
. The internal bus clock is assumed to be the clock source. DT
n
IN
cannot simultaneously function as a clocking source and as an input capture pin. Indeterminate operation
results if DT
n
IN is set as the clock source when the input capture mode is used.
19.2.6
DMA Timer Counters (DTCN
n
)
The current value of the 32-bit DTCNs can be read at anytime without affecting counting. Any write to
DTCN
n
clears it. The timer counter increments on the clock source rising edge (internal bus clock divided
by 1, internal bus clock divided by 16, or DT
n
IN).
IPSBAR
Offset:
0x
04
04
(
DTRR0
)
0x
044
4
(
DTRR1
)
0x
048
4
(
DTRR2
)
0x
04C
4
(
DTRR3
)
Access: User read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
R
REF (32-bit reference value)
W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Figure 19-5. DTRR
n
Registers
Table 19-5. DTRR
n
Field Descriptions
Field
Description
31–0
REF
Reference value compared with the respective free-running timer counter (DTCN
n
) as part of the output-compare
function.
IPSBAR
Offset:
0x
04
08
(
DTCR0
)
0x
044
8
(
DTCR1
)
0x
048
8
(
DTCR2
)
0x
04C
8
(
DTCR3
)
Access: User read-only
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
R
CAP (32-bit capture counter value)
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 19-6. DTCR
n
Registers
Table 19-6. DTCR
n
Field Descriptions
Field
Description
31–0
CAP
Captures the corresponding DTCN
n
value during a capture operation when an edge occurs on DT
n
IN, as
programmed in DTMR
n
.
