Clock Module
MCF5213 ColdFire® Integrated Microcontroller Reference Manual
,
Rev. 3
Freescale Semiconductor
6-9
6.7.1.3
Low-Power Divider Register (LPDR)
The LPDR contains a 4-bit field that divides down the system clock (regardless if the reference clock or
PLL clock is driving the system clock) by a factor of 2
n
(where n is a number from 0 to 15 represented by
the 4 bit field). The clock change takes effect with the next rising edge of the system clock.
2
LOCS
Sticky indication of whether a loss-of-clock condition has occurred at any time since exiting reset in normal
PLL
and 1:1 PLL
mode
s
.
• LOCS = 0 when the system clocks are operating normally.
• LOCS = 1 when system clocks have failed due to a reference failure or PLL failure.
After entering stop mode with FWKUP set and the PLL and oscillator intentionally disabled
(STPMD[1:0] = 11), the PLL exits stop mode in the SCM while the oscillator starts up. During this time,
LOCS is temporarily set regardless of LOCEN. It is cleared after the oscillator comes up and the PLL is
attempting to lock.
If a read of the LOCS flag and a loss-of-clock condition occur simultaneously, the flag does not reflect the
current loss-of-clock condition.
A loss-of-clock condition can be detected only if LOCEN = 1 or the oscillator has not yet returned from exit
from stop mode with FWKUP = 1.
0 Loss-of-clock not detected since exiting reset
1 Loss-of-clock detected since exiting reset or oscillator not yet recovered from exit from stop mode with
FWKUP = 1
Note:
The LOCS flag is always 0 in external clock mode.
1–0
Reserved, should be cleared.
IPSBAR
Offset: 0x12_0007 (LPDR)
Access: Supervisor read/write
7
6
5
4
3
2
1
0
R
—
—
—
—
LPD3
LPD2
LPD1
LPD0
W
Reset:
0
0
0
0
0
0
0
0
Figure 6-4. Low-Power Divider Register (LPDR)
Table 6-7. LPDR Field Descriptions
Field
Description
7–4
Reserved, should be cleared.
3–0
LPD
Low-Power Divider. This field is used to divide down the system clock by a factor of 2
LPD
.
Table 6-6. SYNSR Field Descriptions (continued)
Field
Description
