MMCCMB2103UM/D
User’s Manual
52
Connector Information
99
SGTA_b
ETK TRANSFER ACKNOWLEDGE — Active-low output indicating completion
of a data transfer, for either a read or a write cycle.
106
SHS_b
SHOW CYCLE STROBE — Output signal indicating that address and data are
valid.
109
RESET_b
RESET IN – Active-low input signal that starts a system reset: a reset of the
processor and most peripherals. This signal does not affect the debug module
(which the system provides via the TRST* line).
113
RSTOUT_b
RESET OUT – Active-low output signal, controlled by the processor, that resets
external components. Activation of any internal reset sources asserts this line.
116
CLKOUT
CLOCK OUTPUT — An external, low-frequency clock source from the
processor.
125
SGTCK
ETK TEST CLOCK – Input signal that synchronizes the JTAG test logic.
126
SGTMS
ETK TEST MODE SELECT – Input signal that sequences the JTAG test
controller's state machine, sampled on the rising edge of the TCK signal.
129
SGTDI
ETK TEST DATA INPUT – Serial input signal for JTAG test instructions and
data, sampled on the rising edge of the TCK signal.
130
SGTDO
ETK TEST DATA OUTPUT – Serial output signal for JTAG test instructions and
data. Tri-stateable and actively driven in the Shift-IR and Shift-DR controller
states, this signal changes on the falling edge of the TCK signal.
133
SGTRST_b
ETK TEST RESET – Active-low input signal that asynchronously initializes the
test controller.
Table 4-5 ETK Connector J5 Signal Descriptions (Continued)
Pin
Mnemonic
Signal
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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