Freescale Semiconductor CMB2103, User Manual

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MMCCMB2103UM/D
User’s Manual
48
Connector Information
Table 4-4 MAPI Connector P4/J4 Signal Descriptions
Pin Mnemonic Signal
100 VDD5V +5-volt power.
99, 2, 1 VDD3V +3.3-volt power.
98, 94 CSE1, CSE0 EMULATION CHIP SELECTS (lines 1, 0) — Emulation-mode output chip-select
signals.
97, 96, 93, 83,
76, 75, 58, 57,
40, 39, 28, 27,
16, 15
GND GROUND
95 CLKOUT CLOCK OUTPUT — An external, low-frequency clock source from the
processor.
92, 90, 85, 74 —
67, 65, 42
PTJ4[x] Pass Through
91, 89, 87 CS_b[3] —
CS_b[1]
CHIP SELECTS (lines 3—1) — Active-low output lines that provide chip selects
to external devices.
88 OE_b OUTPUT ENABLE — Active-low output that indicates that a bus access is a
read access; enables slave devices to drive the data bus.
86, 84, 82, 80 EB_b[0] —
EB_b[3]
(not in exact
order)
ENABLE BYTES 0, 1, 3, 2 — Active-low outputs active during an operation to
corresponding data bits (D31-D24 for enable byte 0, D23-D16 for enable byte 1,
D15-D8 for enable byte 2, D7-D0 for enable byte 3).
81 RW_b READ/WRITE ENABLE — Active-low signal indicating that the current bus
access is a write access. Otherwise, the current bus access is a read access.
79 SHS_b SHOW CYCLE STROBE — Output signal indicating that address and data are
valid.
78 TEA_b TRANSFER ERROR ACKNOWLEDGE — Active-low input that indicating that a
bus transfer error has occurred.
77 TA_b TRANSFER ACKNOWLEDGE — Active-low output indicating completion of a
data transfer, for either a read or a write cycle.
66, 64 — 59,
56—43, 41
ADDR[22] —
ADDR[0]
(not in exact
order)
ADDRESS BUS (lines 22—0) — Output lines for addressing external devices.
These lines change state only during external-memory accesses.
38—29, 26—17,
14—3
DATA[31] —
DATA[0]
(not in exact
order)
DATA BUS (lines 31–0) — Bi-directional data lines for accessing external
memory. A hardware reset or no external-bus activity hods these lines in their
previous logic state.
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Freescale Semiconductor, Inc.
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