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SGA10GD

Dual 10Gbps PCI Expressx8

Ethernet adapter

REFERENCE MANUAL

Ver.: 2009.09.29., Ver. 1.1

(C) BUDAPEST UNIVERSITY OF TECHNOLOGY AND ECONOMICS

DEPARTMENT OF TELECOMMUNICATIONS AND MEDIA

INFORMATICS

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Summary of Contents for SGA10GD

Page 1: ...SGA10GD Dual 10Gbps PCI Expressx8 Ethernet adapter REFERENCE MANUAL Ver 2009 09 29 Ver 1 1 C BUDAPEST UNIVERSITY OF TECHNOLOGY AND ECONOMICS DEPARTMENT OF TELECOMMUNICATIONS AND MEDIA INFORMATICS 1...

Page 2: ...t 8 2 4 PCI Express x8 endpoint 10 2 5 DDR2 SODIMM RAM 12 2 6 Feature Connector 14 2 7 FPGA Programming 16 2 7 1 Programming through JTAG 16 2 7 2 Programming from FLASH 16 2 7 3 Partial reconfigurati...

Page 3: ...s below show the major on board components Top side components 1 Dual 10 Gigabit sec XFP receptacle 2 DDR2 RAM SODIMM Receptacle 1 8V Notebook RAM 3 PCI Express x8 Edge Connector 4 Platform FLASH with...

Page 4: ...ress PCI SIG PCI Express Base Specification Revision 1 0a PCI SIG PCI Express Card Electromechanical Specification Revision 1 0a DDR2 Dual DataRate II SDRAM and Modules JEDEC JESD79 2D DDR2 SDRAM SPEC...

Page 5: ...e two types of devices XC5VLX110T 2FF1136C for SGA10GD board XC5VLX50T 1FF1136C for SGA10GDL board The main characteristics of the devices are shown in the table below XC5VLX110TXC5VLX50T Array metric...

Page 6: ...n run at 550MHz internal clock speed Two SGA10GD models can be produced depending on the insertion of FPGA type as shown below Model FPGA SGA10GD XC5VLX110T SGA10GDLXC5VLX50T The following sections de...

Page 7: ...93 DDR2 Reference voltage AVCC1 1 03 FPGA MGT MGT s core voltage AVCPLL1V2 1 23 FPGA MGT MGT s PLL supply VCC5 5 XFP aux XPF aux power VCC1V2 1 222XFP XAUI XFP XAUI converter Main supply 2 2 Clock sou...

Page 8: ...2 HSTDP 1 029 G12 HSTDN 0 028 F12 HSTDN 1 028 F12 HSRDP 0 018 C12 HSRDP 1 018 C12 HSRDN 0 017 B12 HSRDN 1 017 B12 HSTCLKP 0 024 G12 HSTCLKP 1 024 G12 HSTCLKN 0 025 F12 HSTCLKN 1 025 F12 GND 001 GND 00...

Page 9: ...UAH10 TTXON 0 TX enable AL11 TTXON 1 TX enable AG11 RXDP 0 0 XAUI RX lane 0 D1 RXDP 1 0 XAUI RX lane 0 T1 RXDN 0 0 C1 RXDN 1 0 R1 RXDP 0 1 XAUI RX lane 1 A3 RXDP 1 1 XAUI RX lane 1 N1 RXDN 0 1 A2 RXDN...

Page 10: ...WR 12 VOLTS B3 To PWR GND A4 GND B4 JTAG_TCK A5 SMCLK B5 JTAG_TDI A6 SMDAT B6 JTAG_TDO A7 GND B7 JTAG_TMS A8 3 3 VOLTS B8 3 3 VOLTS A9 JTAG_TRST_N B9 3 3 VOLTS A10 3 3 VAUX B10 PXPERST A11 PCIE_WAKE_N...

Page 11: ...D B49 RXPOLARITY attribute for the MGT has to be changed TXPOLARITY attribute for the MGT has to be changed Although the PCI identification codes are FPGA core dependeant defaults are the following Ve...

Page 12: ...interface signals SODIMM connector pin assignments and the associated FPGA pin assignments Signal Front DIMM FPGA Signal Back DIMM FPGA VCC0V9 001 GND 002 GND 003 DQ 4 004 H29 DQ 0 005 L29 DQ 5 006 G...

Page 13: ...6 BA 1 106 W31 BA 0 107 V27 RAS_N 108 AA31 WE_N 109 V28 CS_N 0 110 Y31 VCC1V8 111 VCC1V8 112 CAS_N 113 Y29 ODT 0 114 T34 CS_N 1 115 AA29 A 13 116 AB31 VCC1V8 117 VCC1V8 118 ODT 1 119 V30 NC CSN 3 120...

Page 14: ...inly for historical reason a 40 pins BERG type Feature Connector designated as J5 is used for SGA10GD The table below shows the pinout assignment for FPGA cores implementing IDE HDD applications Signa...

Page 15: ...TRX 0 21 J16 GND 22 NC 23 K16 GND 24 RRX 0 25 L16 GND 26 NC 27 H17 NC 28 K22 RRX 1 29 J17 GND 30 TRX 1 31 H18 NC 32 G23 TRX 2 33 K18 GND 34 RRX 2 35 H19 NC 36 H23 TRX 3 37 J19 NC 38 L19 RRX 3 39 K19 G...

Page 16: ...d as J7 on board as shown in the figure below 2 7 2 Programming from FLASH From the Platform FLASH designated as U11 the FPGA can be loaded automatically If J4 jumper is open it happens one time durin...

Page 17: ...tial reconfiguration of the FPGA TRANSIENT cores can be loaded that way J6 jumper controls HSWAPEN 2 8 Status LEDs There are two status LEDs assigned to an interface on board One red colored LOS Loss...

Page 18: ...the Platform Flash when the OS restarts or the reset button is pushed on the PC Using the Microsoft Windows XP operating system SGA10GD is found as a new hardware with the following ID s Vendor 15C6...

Page 19: ...ce of core by using the data bits column for a given clock rate Signal f MHz FPGA Res Core D bits Source core_clk250 00 1 PLL_ADV pciex8n a Slot clock 100MHz user_clk125 00 see above pciex864 Slot clo...

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