Fluke NetDAQ 2640A, Service Manual

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Theory of Operation
Detailed Circuit Description
2
2-25
Digital and Alarm Output Drivers 2-45.
Since the 11 Digital Output and Alarm Output Drivers are identical in design, the
following example description references only the components that are used for the
Master Alarm Output (AO<2>).
The Microprocessor controls the state of the Master Alarm Output Driver by writing to
the Alarm Output register in the FPGA (A1U31) to set the level of output A1U31-61.
When A1U31-61 is set high, the output of the open-collector Darlington driver
(A1U17-14) sinks current through current-limiting resistor A1R60. When A1U31-61 is
set low, the driver output turns off and is pulled up by A1Z2 and/or the voltage of the
external device that the output is driving. If the driver output is driving an external
inductive load, the internal flyback diode (A1U17-9) conducts the energy into MOV
A1RV1 to keep the driver output from being damaged by excessive voltage. Capacitor
A1C56 ensures that the instrument meets electromagnetic interference (EMI) and
electromagnetic compatibility (EMC) performance requirements.
Totalizer Input 2-46.
The Totalizer Input circuit consists of Input Protection, a Digital Input Buffer circuit,
and a Totalizer Debouncing circuit. The Digital Input Buffer for the totalizer is protected
from electrostatic discharge (ESD) damage by A1R49 and A1C43. Refer to the detailed
description of the Digital Input Buffer circuit for more information.
The Totalizer Debounce circuit in the FPGA (A1U31) allows the Microprocessor to
select totalizing of either the input signal or the debounced input signal. The buffered
Totalizer Input signal (TOTI*) goes into the FPGA at A1U31-12. Inside the FPGA, the
totalizer signal is routed to a 16-bit counter in the FPGA. The counter can be read at any
time by the microprocessor. When the 16-bit counter overflows, the microprocessor is
interrupted by the Totalizer Interrupt signal (TOTINT*) that comes from A1U31-8. The
microprocessor uses this interrupt (A1U1-97) to increment a software counter.
The actual debouncing of the input signal is accomplished by A1U31. Counters divide
the 15.36-MHz system clock down to 128 kHz for the debouncing circuit. An EXOR
gate compares the input signal (TOTI*) and the latched output of the debouncer. If these
signals differ, the EXOR gate output goes high, enabling the debouncer. If the input
remains stable for 1.75 milliseconds, the debouncer output changes state. If the input
does not remain stable for 1.75 milliseconds, the debouncer output does not change state.
If the Microprocessor selected totalizing of the debounced input signal, the debouncer
output is connected to the 16-bit counter inside the FPGA.
External Trigger Circuits 2-47.
The External Trigger Input circuit can be configured by the Microprocessor to interrupt
on a rising or falling edge of the TGIN* input (A1J6-2) or to not interrupt on any
transitions of the TGIN* input. The falling edge of the TGIN* input is used by the
instrument firmware as an indication to start scanning, and the rising edge is used as an
indication to stop scanning.
The External Trigger Input is pulled up to +5V dc by A1Z2 and is protected from
electrostatic discharge (ESD) damage by A1R58, A1C54, A1Z3, and A1CR15. Capacitor
A1C54 helps ensure that the instrument meets EMI/EMC performance requirements.