9100A-017
7-19
the line on the vector would provide the edge necessary to sat-
isfy the WAIT. If the controlling signal was not at the desired
level, vector driving would halt until the signal was set to the
correct level.
Figure 7-3. Using WAIT to Check for a Level (Method 1)
Another method would “AND” the controlling signal with the
Vector Output I/O Module INT CLK line (See Figure 7-4). This
method would provide an edge when the controlling signal was
satisfied.
Figure 7-4. Using WAIT to Check for a Level (Method 2)
TIMING SETS
7.18.
The Vector Output I/O Module does not require the use of timing
sets for most applications because of its pattern depth of 8192
vectors and loading time of 3 seconds for an 8K vector file.
However, to reduce programming time or the number of vector
files necessary, two Vector Output I/O Modules can be used to
provide timing sets.
One module would contain a vector file of the basic timing sets;
that is, the control signal vectors required to perform the read-
cycle, writecycle, or other cycles. The vector file would contain
a LOOP statement enclosing the cycle information set to the
Summary of Contents for 9100A Series
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Page 83: ...A 1 Appendix A New TL 1 Commands ...
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Page 87: ...clockfreq 3 For More Information The Overview Of TL 1 section of the Programmer s Manual ...
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Page 91: ...drivepoll 3 For More Information The Overview Of TL 1 section of the Programmer s Manual ...
Page 92: ...drivepoll 4 ...
Page 104: ...vectordrive 4 ...
Page 107: ...vectorload 3 For More Information The Overview Of TL 1 section of the Programmer s Manual ...
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