Functional Description
CPB902
C P B 9 0 2 U s e r M a n u a l
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4.2
Address Mapping
4.2.1
Memory Addressing
Table 4.1:
Memory Address Mapping
Address Range
Size
Description
00000h – 09FFFh
640 KB
System memory
A0000h – BFFFFh
128 KB
Video memory
C0000h –
С
7FFFh
32 KB
Display BIOS memory
C8000h – EFFFh
160 KB
BIOS extensions
16K blocks can be copied into system memory.
See Shadow Configuration (
) for details.
F0000h – FFFFFh
64 KB
System BIOS area
10000h – 4FFFFFFh
127 KB
Extended system memory
FE0000h – FFFFFFh
128 KB
System BIOS area
4.2.2
I/O Addressing
Table 4.2:
I/O Address Space
Address Range
Function
000h – 0A7h
System I/O ports
0A8h – 0AFh
System I/O ports
0B0h – 0FFh
System I/O ports
100h – 107h
COM3 (default)
108h – 10Fh
COM4 (default)
110h – 117h
COM5 (default)
118h – 11Fh
COM6 (default)
120h – 141h
Reserved
142h
COM3-COM6 ID register (default)
143h – 2F7h
Reserved (alternative address space for COM3-COM6 and LPT1)
2F8h – 2FFh
COM2
300h – 31Fh
System and user I/O ports (FPGA)
370h – 377h
System I/O ports (SIO)
378h – 37Bh
LPT1 (default range; 278h address is allowed, unless allocated for COM3-COM6)
3F0h – 3F7h
FDD controller
3F8h – 3FFh
COM1
CF8h – CFFh
Host PCI controller configuration registers
