FabiaTech Corporation
ADVANCED CHIPSET SETUP
This section describes the configuration of the board’s chipset features.
VGA Frame Buffers Size (KB)
This field is share memory architecture (SMA) for frame buffer memory. SMA allows
system memory to be efficiently share by the host CPU and allocated depending
on user preference, application requirements, and total size of system memory.
Available Options: None, 128KB~4096KB
Default setting: 4096KB
ISA Authorized To Write to IPC
This field is controls the timing of the DMA controller, and also the number of wait
state for write register to IPC.
Available Options: Disabled, Enabled
Default setting: Disabled
IPC Wait State Cycle
This field is specifying the number of ISA clock wait state for read/write to IPC.
Available Options: 1, 2, 3, and 4
Default setting: 4
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Summary of Contents for PC104
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