Test Setup - Test Configurator, Timer, and System
Power Blazer
171
Clock
Line Coding
, available with DS1 and E1, allows the selection of the
interface line coding.
For DS1:
AMI
and
B8ZS
(default).
For E1:
AMI
and
HDB3
(default).
Framing
, available with DS1 and E1, allows the selection of the
interface framing.
For DS1:
SF
,
SLC-96
, and
ESF
(default).
For E1:
PCM30
(default),
PCM30 CRC-4
,
PCM31
, and
PCM31 CRC-4
.
REF OUT
Source
, available with CFP4 and QSFP28 transceivers, allows selecting the
source clock that will be used for transmission (TX) on the
REF OUT
port:
TX MCLK
(default for CFP4),
Internal 1/8
,
Internal 1/40
,
Internal 1/160
(default for QSFP28).
TX MCLK
is a clock derived from the inserted
transceiver and its frequency is based on the setting of the
Summary of Contents for Power Blazer 88200NGE
Page 1: ...www EXFO com User Guide 88000 Series Power Blazer HIGH SPEED MULTISERVICE TEST MODULE...
Page 14: ......
Page 20: ......
Page 64: ...Test Setup Test Applications 54 88000 Series OTN BERT...
Page 71: ...Test Setup Test Applications Power Blazer 61 SONET SDH BERT For SDH BERT...
Page 76: ...Test Setup Test Applications 66 88000 Series SONET SDH DSn PDH BERT For SDH...
Page 620: ......
Page 726: ......
Page 752: ......
Page 756: ......
Page 768: ......
Page 886: ...0 5 1 5 48 5 0 176 W d y K y K D...