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Exar

Corporation 48720 Kato Road, Fremont CA, 94538

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(510) 668-7000

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FAX (510) 668-7017

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www.exar.com

XRT86VX38

8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION

2011

REV. 1.0.3

GENERAL DESCRIPTION

The XRT86VX38 is an eight-channel 1.544 Mbit/s or
2.048 Mbit/s DS1/E1/J1 framer and Long-haul/Short-

hual LIU integrated solution featuring R

3

technology

(Relayless, Reconfigurable, Redundancy) and BITS
Timing element. The physical interface is optimized
with internal impedance, and with the patented pad
structure, the XRT86VX38 provides protection from
power failures and hot swapping.

The XRT86VX38 contains an integrated DS1/E1/J1
framer and LIU which provide DS1/E1/J1 framing and
error accumulation in accordance with ANSI/ITU_T
specifications. Each framer has its own framing
synchronizer and transmit-receive slip buffers. The
slip buffers can be independently enabled or disabled
as required and can be configured to frame to the
common DS1/E1/J1 signal formats.

Each Framer block contains its own Transmit and
Receive T1/E1/J1 Framing function. There are 3
Transmit HDLC controllers per channel which
encapsulate contents of the Transmit HDLC buffers
into LAPD Message frames. There are 3 Receive
HDLC controllers per channel which extract the
payload content of Receive LAPD Message frames

from the incoming T1/E1/J1 data stream and write the
contents into the Receive HDLC buffers. Each framer
also contains a Transmit and Overhead Data Input
port, which permits Data Link Terminal Equipment
direct access to the outbound T1/E1/J1 frames.
Likewise, a Receive Overhead output data port
permits Data Link Terminal Equipment direct access
to the Data Link bits of the inbound T1/E1/J1 frames.

The XRT86VX38 fully meets all of the latest T1/E1/J1
specifications: ANSI T1/E1.107-1988, ANSI T1/
E1.403-1995, ANSI T1/E1.231-1993, ANSI T1/
E1.408-1990, AT&T TR 62411 (12-90) TR54016, and
ITU G-703, G.704, G706 and G.733, AT&T Pub.
43801, and ETS 300 011, 300 233, JT G.703, JT
G.704, JT G706, I.431. Extensive test and diagnostic
functions include Loop-backs, Boundary scan,
Pseudo Random bit sequence (PRBS) test pattern
generation, Performance Monitor,

Bit Error Rate

(BER) meter, forced error insertion, and LAPD
unchannelized data payload processing according to
ITU-T standard Q.921.

.

APPLICATIONS AND FEATURES (NEXT PAGE)

F

IGURE

1. XRT86VX38 E

IGHT

C

HANNEL

DS1 (T1/E1/J1) F

RAMER

/LIU C

OMBO

Performance

Monitor

PRBS

Generator &

Analyser

HDLC/LAPD

Controllers

LIU &

Loopback

Control

DMA

Interface

Signaling &

Alarms

JTAG

WR

ALE_AS

RD

RDY_DTACK



P

Select

A[11:0]

D[7:0]

Microprocessor

Interface

4

3

Tx Serial

Clock

Rx Serial

Clock

8kHz sync

OSC

Back Plane

1.544-16.384 Mbit/s

Local PCM

Highway

ST-BU

S

2-Frame

Slip Buffer

Elastic Store

Tx Serial

Data In

Tx LIU

Interface

2-Frame

Slip Buffer

Elastic Store

Rx LIU

Interface

Rx Framer

Rx Serial
Data Out

RTIP

RRING

TTIP

TRING

External Data

Link Controller

Tx Overhead In

Rx Overhead Out

XRT86VX38

Tx Framer

LLB

LB

System (Terminal) Side

Line Side

1:1 Turns Ratio

1:2 Turns Ratio

Memory

Intel/Motorola µP

Configuration, Control &

Status Monitor

RxLOS

TxON

INT

1
2
3
...
»

Summary of Contents for XRT86VX38

Page 1: ...Overhead Data Input port which permits Data Link Terminal Equipment direct access to the outbound T1 E1 J1 frames Likewise a Receive Overhead output data port permits Data Link Terminal Equipment dire...

Page 2: ...l Bits for E1 on the Transmit Path Supports SSM Synchronous Messaging Extraction BOC for T1 National Bits for E1 on the Receive Path Supports BITS timing generation on the Transmit Outputs Supports BI...

Page 3: ...N Frame non signaling Direct access to D and E channels for fast transmission of data link information Full BERT Controller for generation and detection on system and line side of the chip PRBS QRSS...

Page 4: ...Hex Address 0xN11E 45 Table 30 Transmit Interface Control Register TICR Hex Address 0xN120 46 Table 31 Transmit Interface Speed When Multiplexed Mode is Disabled TxMUXEN 0 48 Table 32 Transmit Interf...

Page 5: ...User Code Register 0 23 TUCR 0 23 Hex Address 0xN320 to 0xN337 97 Table 89 Transmit Signaling Control Register 0 23 TSCR 0 23 Hex Address 0xN340 to 0xN357 98 Table 90 Receive Channel Control Register...

Page 6: ...20 154 Table 146 Receive Loopback Code 5 Interrupt Enable Register RLCIER5 Hex Address 0xNB21 155 Table 147 Receive Loopback Code 6 Interrupt and Status Register RLCISR6 Hex Address 0xNB22 156 Table 1...

Page 7: ...Table 179 LIU Global Control Register 1 LIUGCR1 Hex Address 0x0FE1 193 Table 180 LIU Global Control Register 2 LIUGCR2 Hex Address 0x0FE2 194 Table 181 LIU Global Control Register 3 LIUGCR3 Hex Addres...

Page 8: ...0xN10B Receive Signaling Data Link Select Register RSDLSR 0xN10C Receive Signaling Change Register 0 RSCR0 0xN10D Receive Signaling Change Register 1 RSCR1 0xN10E Receive Signaling Change Register 2...

Page 9: ...n Code Register Code 2 RLDCR2 0xN12F Reserved E1 mode only 0xN130 0xN13F Transmit LoopCode Generation Switch TLCGS 0xN140 Loopcode Timer Select LCTS 0xN141 Transmit SPRM and NPRM Control Register TSPR...

Page 10: ...ansmit FDL Register TFDLR 0xN175 SSM Transmit Byte Count Register TBCR 0xN176 Receive DS 0 Monitor Registers RDS0MR 0xN15F 0xN1CF Transmit DS 0 Monitor Registers TDS0MR 0xN1D0 0xN1EF Device ID Registe...

Page 11: ...RCOAC 0xN90B LAPD Frame Check Sequence Error counter 1 LFCSEC1 0xN90C PRBS bit Error Counter MSB PBECU 0xN90D PRBS bit Error Counter LSB PBECL 0xN90E Transmit Slip Counter TSC 0xN90F Excessive Zero Vi...

Page 12: ...NB19 Receive Loopback code 2 Interrupt and Status Register RLCISR2 0xNB1A Receive Loopback code 2 Interrupt Enable Register RLCIER2 0xNB1B Receive Loopback code 3 Interrupt and Status Register RLCISR3...

Page 13: ...IU Channel Control Interrupt Status Register LIUCCISR 0x0FN6 LIU Channel Control Cable Loss Register LIUCCCCR 0x0FN7 LIU Channel Control Arbitrary Register 1 LIUCCAR1 0x0FN8 LIU Channel Control Arbitr...

Page 14: ...XRT86VX38 10 8 CHANNEL T1 E1 J1 FRAMER LIU COMBO T1 REGISTER DESCRIPTION REV 1 0 3 LIU Global Control Register 5 LIUGCR5 0x0FEA Reserved 0x0FEB 0x0FFF TABLE 1 REGISTER SUMMARY FUNCTION SYMBOL HEX...

Page 15: ...chronize its transmit output frame alignment with the 8kHz signal that is derived from the MCLK PLL as described below 0 Disables the Sync all Transmit Framers to 8kHz feature 1 Enables the Sync all T...

Page 16: ...can be programmed as input or output depending on the setting of SYNC INV bit in Register Address 0xN109 bit 4 Please see Register Description for the Synchronization Mux Register SMR 0xN109 Table 10...

Page 17: ...to select any of the following loop back modes for the framer section For LIU loopback modes see the LIU configuration registers 3 2 Reserved R W 0 Reserved LB 1 0 TYPES OF LOOPBACK SELECTED 00 Norma...

Page 18: ...isables the B8ZS encoder NOTE When B8ZS encoder is disabled AMI line code is used 0 Decode AMI B8ZS R W 0 Decode AMI or B8ZS HDB3 Line Code Select This bit enables or disables the B8ZS HDB3 decoder on...

Page 19: ...PIO0_3 GPIO0_2 GPIO0_1 GPIO0_0 within this register 3 0 GPIO0_3 GPIO0_2 GPIO0_1 GPIO0_0 R W 0000 GPIO0_3 GPIO0_2 GPIO0_1 GPIO0_0 Control The exact function of this bit depends upon whether General Pur...

Page 20: ...PIO1_3 GPIO1_2 GPIO1_1 GPIO1_0 within this register 3 0 GPIO1_3 GPIO1_2 GPIO1_1 GPIO1_0 R W 0000 GPIO1_3 GPIO1_2 GPIO1_1 GPIO1_0 Control The exact function of this bit depends upon whether General Pur...

Page 21: ...e the Transmit T1 Framer block to transmit CRC errors within the outbound T1 data stream as depicted below 0 Disables CRC error transmission on the outbound T1 stream 1 Enables CRC error transmission...

Page 22: ...Disables FASTSYNC feature 1 Enables FASTSYNC feature 2 0 FSl 2 0 R W 000 T1 Framing Mode Select 2 0 These three bits permit the user to select the exact T1 framing format that the channel is to operat...

Page 23: ...r ESF and SF 2 Minimum one second delay between termination of the first RAI and the initiation of the subsequent RAI is NOT enforced 3 YEL 0 and YEL 1 bits see description of bits 5 4 of this registe...

Page 24: ...mitted for 255 patterns of 1111_1111_0000_0000 approximately 1 second 2 If YEL 0 bit is set high for a duration longer than the time required to transmit 255 patterns of 1111_1111_0000_0000 on the 4 k...

Page 25: ...d for 255 patterns approximately 1 second 2 If ALARM_ENB bit is set high for a duration longer than the time required to transmit 255 patterns of 1111_1111_0000_0000 on the 4 kbit s data link M1 M12 R...

Page 26: ...IS Patterns that the Receive T1 Framer block must detect before it will declare the AIS defect condition TABLE 7 ALARM GENERATION REGISTER AGR HEX ADDRESS 0XN108 BIT FUNCTION TYPE DEFAULT DESCRIPTION...

Page 27: ...he TxMSYNC signal NOTE This bit is not used in base rate 1 544MHz Clock mode 5 MSYNC R W O Transmit Super Frame Boundary This bit provides an option to use the transmit single frame boundary TxSYNC as...

Page 28: ...high This bit can also be used to select the direction of the transmit single frame boundary TxSYNC and multi frame boundary TxMSYNC depending on whether TxSERCLK is chosen as the timing source for t...

Page 29: ...data stream This bit is ignored if CRC Multiframe Alignment is disabled 0 Framing Bits Source Select R W 0 Framing Bits Source Select This bit is used to specify the source for the Framing bits that w...

Page 30: ...00 Transmit D E TimeSlot Source Select 1 0 These two bits specify the source for transmit D E time slots The table below shows the different sources from which D E time slots can be inserted TXDLBW 1...

Page 31: ...SDLSR HEX ADDRESS 0XN10A BIT FUNCTION TYPE DEFAULT DESCRIPTION OPERATION TXDL 1 0 SOURCE FOR DATA LINK BITS 00 Transmit LAPD Controller 1 SLC96 Buffer The Data Link bits are inserted from the Transmit...

Page 32: ...eceive T1 Framer block will also check for correct CRC values prior to declaring the In Frame condition 5 3 LOF Tolerance 2 0 R W 000 LOF Defect Declaration Tolerance 2 0 These bits along with the LOF...

Page 33: ...se bits permit the user to specify the destination circuitry that will receive and process the D E Time slot within the incoming T1 data stream RXDLBW 1 0 RECEIVE DATA LINK BANDWIDTH SELECTED 00 Recei...

Page 34: ...FUNCTION TYPE DEFAULT DESCRIPTION OPERATION RXDL 1 0 DESTINATION CIRCUITRY FOR RECEIVE DATA LINK 00 Receive LAPD Controller Block 1 and RxSER_n The Data Link bits are routed to the Receive LAPD Contro...

Page 35: ...s 8 through 15 within the incoming T1 data stream has changed since the last read of this register as depicted below 0 CAS data for Time slots 8 through 15 has NOT changed since the last read of this...

Page 36: ...Mask R W 0 Framer Alarm Mask This bit can be used to mask the alarms associated with the Framing Mode that is selected Regardless of the framing mode this bit will mask to following alarms LOF IF COFA...

Page 37: ...a MOS type of message to transmitting a BOS type of message If the user disables this feature then the Transmit HDLC Controller Block 1 will NOT transmit the ABORT sequence whenever it abruptly transi...

Page 38: ...S within this register is set to 0 1 Tx_FCS_EN R W 0 Transmit LAPD Message with Frame Check Sequence FCS This bit permits the user to configure the Transmit HDLC Controller block 1 to compute and appe...

Page 39: ...C1 Buffer 1 is the next available buffer In this case if the user wishes to write in the contents of a new outbound Data Link Message into the Transmit HDLC1 Mes sage Buffer he she should proceed to w...

Page 40: ...0 R W 0000000 Receive HDLC Message byte count The exact function of these bits depends on whether the Receive HDLC Controller Block 1 is configured to receive MOS or BOS messages In BOS Mode These se...

Page 41: ...bit permits the user to freeze any signaling update on the RxSIGn output pin as well as the Receive Signaling Array Register RSAR 0xN500 0xN51F until this bit is cleared 0 Signaling on RxSIG and RSAR...

Page 42: ...Rx Slip Buffer FIFO Latency 4 0 R W 00100 Receive Slip Buffer FIFO Latency 4 0 These bits permit the user to specify the Receive Data Latency in terms of RxSerClk_n clock periods whenever the Receive...

Page 43: ...er should drive the DMA Acknowledge ACK0 low to indicate that it is ready to start the transfer The external DMA controller should place new data on the Microprocessor data bus each time the Write Sig...

Page 44: ...rnal DMA controller should drive the DMA Acknowl edge ACK1 low to indicate that it is ready to receive the data The T1 Framer should place new data on the Microprocessor data bus each time the Read Si...

Page 45: ...le Auto Clear This bit configures all interrupt enable bits to clear or not clear after reading the interrupt status bit 0 Configures all Interrupt Enable bits to not cleared after reading the interru...

Page 46: ...the HDLC controller is Enabled this bit set to 1 If the HDLC con troller is disabled while transmitting a message BOS will disrupt the transmission and send all ones MOS will send the flag sequence 0...

Page 47: ...ith an embedded signature of 01111100 11111111 right to left which recurs at 386 bit intervals in the DS 1 signal RAI CI Remote Alarm Indication Customer Installation RAI CI is a repeti tive pattern w...

Page 48: ...ditions When this bit is set High the RLOS_n pin will pull High during a LOS condition and pull Low when data is present on RTIP RRING 0 Disables the RLOS output pin 1 Enables the RLOS output pin 5 FA...

Page 49: ...rating at 2 048Mbit s in DS 1 mode In this application 63 gaps missing data are inserted so that the overall bit rate is reduced to 1 544Mbit s If the transmit Gapped Clock Interface is enabled TxMSYN...

Page 50: ...TxFr1544 to 1 6 Reserved Reserved 5 TxPLClkEnb TxSync Is Low R W 0 Transmit payload clock enable TxSYNC is Active Low This exact function of this bit depends on whether the T1 framer is configured to...

Page 51: ...is bit has no effect in the high speed or multiplexed modes of operation In high speed or multiplexed modes TxCHN 0 functions as TxSIGn for signaling input 3 TxICLKINV R W 0 Transmit Clock Inversion B...

Page 52: ...data input 01 2 048Mbit s High Speed MVIP Mode Transmit backplane interface signals include TxSERCLK is an input clock at 1 544MHz TxMSYNC is the high speed input clock at 2 048MHz to input high speed...

Page 53: ...o 4 channels and output to the line on channels 0 through 3 The TxSYNC signal pulses High during the framing bit of each DS 1 frame 01 Bit Multiplexed Mode at 16 384MHz is Enabled Transmit backplane i...

Page 54: ...the line for BERT pattern and declare BERT LOCK if BERT has locked onto the input pattern 0 Disables the BERT Switch Feature 1 Enables the BERT Switch Feature 2 BER 1 R W 0 Bit Error Rate This bit is...

Page 55: ...isabled T1 Transmit Framer will gener ate an unframed BERT pattern to the line side if this bit is enabled If PRBS switch function is enabled T1 Receive Framer will generate an unframed BERT pattern t...

Page 56: ...is bit is used to select whether the receive frame boundary RxSYNC is active low or active high 0 Selects RxSync to be active High 1 Selects RxSync to be active Low 4 RxFr1544 R W 0 Receive Fractional...

Page 57: ...e data of four channels from the line side are multi plexed onto one serial stream inside the receive framer and output to the back plane interface on RxSER The backplane speed will become either 12 3...

Page 58: ...lane interface signals include RxSERCLK is an input or output clock at 1 544MHz RxSYNC is an input or output signal which indicates the receive singe frame boundary RxSER is the base rate data output...

Page 59: ...Serial Output RxSER The RxSYNC signal pulses High during the framing bit of each DS 1 frame 01 Bit Multiplexed Mode at 16 384MHz is Enabled Receive backplane interface is taking data from the four LI...

Page 60: ...utput depending on whether BERT switch function is enabled or not bit 3 in register 0xN121 If the BERT Switch function is disabled T1 transmit framer will insert a single BERT error and output to the...

Page 61: ...function and this bit are both enabled T1 Trans mit Framer will detect the incoming BERT pattern from the transmit backplane interface and declare BERT lock if incoming data locks onto the BERT patte...

Page 62: ...loopback code deactivation length There are four lengths supported by the XRT86VX38 as presented in the table below RXLBCALEN 1 0 RECEIVE LOOPBACK CODE ACTIVATION LENGTH 00 Selects 4 bit receive loopb...

Page 63: ...n loopback code is enabled Register address 0xN126 The XRT86VX38 will cancel the remote loopback upon detecting the loopback code deactivation code specified in the Receive Loopback Code Deactivation...

Page 64: ...CENB R W 0 Receive activation loopback code enable This bit enables the receive loopback activation code detection Receive loopback activation code is detected by writing the expected receive activati...

Page 65: ...oopcode 5 is enabled this bit will determine which input the loopcode will be detected on By default the loopcode is search ing for the line side RTIP RRING 0 Line Side RTIP RRING 1 System Side TxSER...

Page 66: ...ve LoopCode Switch 0 If receive loopcode 0 is enabled this bit will determine which input the loopcode will be detected on By default the loopcode is search ing for the line side RTIP RRING 0 Line Sid...

Page 67: ...Framed Loopback Code This bit selects either framed or unframed loopback code generation in the transmit path 0 Selects an Unframed loopback code for transmission 1 Selects a framed loopback code for...

Page 68: ...ontrol Register 0 Disables the receive loopback code activation detection 1 Enables the receive loopback code activation detection TABLE 46 RECEIVE LOOPBACK DEACTIVATION CODE REGISTER CODE 1 RLDCR1 HE...

Page 69: ...Framed Loopback Code This bit selects either framed or unframed loopback code generation in the transmit path 0 Selects an Unframed loopback code for transmission 1 Selects a framed loopback code for...

Page 70: ...ontrol Register 0 Disables the receive loopback code activation detection 1 Enables the receive loopback code activation detection TABLE 49 RECEIVE LOOPBACK DEACTIVATION CODE REGISTER CODE 2 RLDCR2 HE...

Page 71: ...ERATION 7 3 Reserved R W 0 Reserved 2 0 LCTimer R W 110 Loopcode Timer Select These bits are used to select the timer value for declaring a valid loopcode detection for both Activation and De Activati...

Page 72: ...This bit provides the contents of the U2 bit within the outgoing SPRM message 3 0 R_BIT R W 0000 R Bit This bit provides the contents of the R bit within the outgoing SPRM message TABLE 52 TRANSMIT S...

Page 73: ...ng a MOS type of message to transmitting a BOS type of message If the user disables this feature then the Transmit HDLC Controller Block 2 will NOT transmit the ABORT sequence whenever it abruptly tra...

Page 74: ...S within this register is set to 0 1 Tx_FCS_EN R W 0 Transmit LAPD Message with Frame Check Sequence FCS This bit permits the user to configure the Transmit HDLC Controller block 2 to compute and appe...

Page 75: ...C2 Buffer 1 is the next available buffer In this case if the user wishes to write in the contents of a new outbound Data Link Message into the Transmit HDLC2 Mes sage Buffer he she should proceed to w...

Page 76: ...0 R W 0000000 Receive HDLC Message byte count The exact function of these bits depends on whether the Receive HDLC Controller Block 2 is configured to receive MOS or BOS messages In BOS Mode These se...

Page 77: ...Framed Loopback Code This bit selects either framed or unframed loopback code generation in the transmit path 0 Selects an Unframed loopback code for transmission 1 Selects a framed loopback code for...

Page 78: ...ontrol Register 0 Disables the receive loopback code activation detection 1 Enables the receive loopback code activation detection TABLE 58 RECEIVE LOOPBACK DEACTIVATION CODE REGISTER CODE 3 RLDCR3 HE...

Page 79: ...Framed Loopback Code This bit selects either framed or unframed loopback code generation in the transmit path 0 Selects an Unframed loopback code for transmission 1 Selects a framed loopback code for...

Page 80: ...ontrol Register 0 Disables the receive loopback code activation detection 1 Enables the receive loopback code activation detection TABLE 61 RECEIVE LOOPBACK DEACTIVATION CODE REGISTER CODE 4 RLDCR4 HE...

Page 81: ...Framed Loopback Code This bit selects either framed or unframed loopback code generation in the transmit path 0 Selects an Unframed loopback code for transmission 1 Selects a framed loopback code for...

Page 82: ...ontrol Register 0 Disables the receive loopback code activation detection 1 Enables the receive loopback code activation detection TABLE 64 RECEIVE LOOPBACK DEACTIVATION CODE REGISTER CODE 5 RLDCR5 HE...

Page 83: ...Framed Loopback Code This bit selects either framed or unframed loopback code generation in the transmit path 0 Selects an Unframed loopback code for transmission 1 Selects a framed loopback code for...

Page 84: ...ontrol Register 0 Disables the receive loopback code activation detection 1 Enables the receive loopback code activation detection TABLE 67 RECEIVE LOOPBACK DEACTIVATION CODE REGISTER CODE 6 RLDCR6 HE...

Page 85: ...a MOS type of mes sage to transmitting a BOS type of message If the user disables this feature then the Transmit HDLC Controller Block 3 will NOT transmit the ABORT sequence whenever it abruptly tran...

Page 86: ...within this register is set to 0 1 Tx_FCS_EN R W 0 Transmit LAPD Message with Frame Check Sequence FCS This bit permits the user to configure the Transmit HDLC Controller block 3 to compute and appen...

Page 87: ...C3 Buffer 1 is the next available buffer In this case if the user wishes to write in the contents of a new outbound Data Link Message into the Transmit HDLC3 Mes sage Buffer he she should proceed to w...

Page 88: ...0 R W 0000000 Receive HDLC Message byte count The exact function of these bits depends on whether the Receive HDLC Controller Block 3 is configured to receive MOS or BOS messages In BOS Mode These se...

Page 89: ...Framed Loopback Code This bit selects either framed or unframed loopback code generation in the transmit path 0 Selects an Unframed loopback code for transmission 1 Selects a framed loopback code for...

Page 90: ...ontrol Register 0 Disables the receive loopback code activation detection 1 Enables the receive loopback code activation detection TABLE 73 RECEIVE LOOPBACK DEACTIVATION CODE REGISTER CODE 7 RLDCR7 HE...

Page 91: ...0 01 80 01 Daly Pattern Framed This pattern is shown in HEX format for simplification purposes 01 01 01 01 01 01 80 01 01 01 01 01 01 03 01 01 01 01 07 01 01 01 01 55 55 55 55 AA AA AA AA 01 01 01 01...

Page 92: ...g its own alarm filter settings for consecutive pattern qualification and many more NOTE If the receive BOC is enabled the part will still report BOS and MOS messages as described in the register desc...

Page 93: ...et This bit is used to reset the receive BOC controller The function of this bit is to reset all the BOC register values to their default values except the BOC Interrupt registers This register bit is...

Page 94: ...BITS 5 0 Receive BOC Message These bits contain the most recently received BOC message if the filter setting has been meet in bits 2 1 of register 0xn170h TABLE 77 SSM RECEIVE FDL REGISTER RFDLR 0XN17...

Page 95: ...dition this register has a filter for consecutive message validation BITS 7 6 Reserved BITS 5 0 Receive FDL Match 3 These bits can be used to set an expected value to be compared to the actual receive...

Page 96: ...ult is one repetition BITS 7 0 Transmit Byte Count Value These bits are used to store the amount of repetitions the Transmit BOC message will be sent before an Abort sequence The default value is 1 If...

Page 97: ...N166 TS6 0xN167 TS7 0xN168 TS8 0xN169 TS9 0xN16A TS10 0xN16B TS11 0xN16C TS12 0xN16D TS13 0xN16E TS14 0xN16F TS15 0xN1C0 TS16 0xN1C1 TS17 0xN1C2 TS18 0xN1C3 TS29 0xN1C4 TS20 0xN1C5 TS21 0xN1C6 TS22 0x...

Page 98: ...identify the XRT86VX38 Framer LIU The value of this register is 0x3Ch TABLE 86 REVISION ID REGISTER REVID HEX ADDRESS 0X01FF BIT FUNCTION TYPE DEFAULT DESCRIPTION OPERATION 7 0 REVID 7 0 RO 00000001 R...

Page 99: ...ot 0 and 0xN317 represents D E time slot 23 6 LAPDcntl 0 R W 0 5 4 TxZERO 1 0 R W 00 Selects Type of Zero Suppression These bits select the type of zero code suppression used by the XRT86VX38 device L...

Page 100: ...t octet are inverted OUTPUT TIME_SLOT_OCTET XOR 0x55 0x4 Contents of the selected timeslot octet will be substituted with the 8 bit value in the Transmit Programmable User Code Register 0xN320 0xN337...

Page 101: ...AULT DESCRIPTION OPERATION 7 0 TUCR 7 0 R W b00010111 Transmit Programmable User code These eight bits allow users to program any code in this register to replace the input PCM data when the Transmit...

Page 102: ...for Time Slot 23 5 C x R W See Note Transmit Signaling bit C This bit allows user to provide signaling Bit C Octets 0 23 if Robbed bit signaling is enabled Rob_Enb bit of this register set to 1 and i...

Page 103: ...RC 0 R W See Note TABLE 89 TRANSMIT SIGNALING CONTROL REGISTER 0 23 TSCR 0 23 HEX ADDRESS 0XN340 TO 0XN357 BIT FUNCTION TYPE DEFAULT DESCRIPTION OPERATION TXSIGSRC 1 0 SIGNALING SOURCE SELECTED 00 11...

Page 104: ...ime slot 23 6 LAPDcntl 0 R W 0 5 4 RxZERO 1 0 R W 00 Type of Zero Suppression These bits select the type of zero code suppression used by the XRT86VX38 device LAPDCNTL 1 0 RECEIVE LAPD CONTROLLER SELE...

Page 105: ...tet are inverted OUTPUT TIME_SLOT_OCTET XOR 0x55 0x4 Contents of the selected timeslot octet will be substituted with the 8 bit value in the Receive Programmable User Code Register 0xN380 0xN397 0x5 C...

Page 106: ...397 BIT FUNCTION TYPE DEFAULT DESCRIPTION OPERATION 7 0 RxUSER 7 0 R W 11111111 Receive Programmable User code These eight bits allow users to program any code in this register to replace the received...

Page 107: ...utput enable This bit enables or disables signaling information to output via the Receive Overhead pin RxOH_n The signaling information in the receive signaling array registers RSAR Address 0xN500 0xN...

Page 108: ...OPERATION RXSIGC 1 0 SIGNALING SUBSTITUTION SCHEMES 00 Substitutes all signaling bits with one 01 Enables 16 code A B C D signaling substi tution Users must write to bits 3 0 in the Receive Sig naling...

Page 109: ...ode or 2 code signaling substitu tion is enabled 2 SIG16 B 4 B 2 A R W 0 16 code 4 code Signaling Bit B This bit provides the value of signaling bit B to substitute the receive signaling bit B when 16...

Page 110: ...received signaling state must be the same for 2 superframes before this register is updated If the signaling bits for two consecutive superframes are not the same the current value of this register wi...

Page 111: ...automatically incremented such that the entire 96 Byte LAPD message can be written into or read from buffer 0 Register 0xN600 continuously TABLE 96 LAPD BUFFER 1 CONTROL REGISTER LAPDBCR1 HEX ADDRESS...

Page 112: ...der to clear the PMON count 6 RLCVC 14 RUR 0 5 RLCVC 13 RUR 0 4 RLCVC 12 RUR 0 3 RLCVC 11 RUR 0 2 RLCVC 10 RUR 0 1 RLCVC 9 RUR 0 0 RLCVC 8 RUR 0 TABLE 98 PMON RECEIVE LINE CODE VIOLATION COUNTER LSB R...

Page 113: ...er to clear the PMON count 6 RFAEC 14 RUR 0 5 RFAEC 13 RUR 0 4 RFAEC 12 RUR 0 3 RFAEC 11 RUR 0 2 RFAEC 10 RUR 0 1 RFAEC 9 RUR 0 0 RFAEC 8 RUR 0 TABLE 100 PMON RECEIVE FRAMING ALIGNMENT BIT ERROR COUNT...

Page 114: ...number of instances that Receive Severely Errored Frames have been detected by the T1 Framer since the last read of this register in T1 mode Severely Errored Frame is defined as having framing bit err...

Page 115: ...clear the PMON count 6 RSBBEC 14 RUR 0 5 RSBBEC 13 RUR 0 4 RSBBEC 12 RUR 0 3 RSBBEC 11 RUR 0 2 RSBBEC 10 RUR 0 1 RSBBEC 9 RUR 0 0 RSBBEC 8 RUR 0 TABLE 103 PMON RECEIVE CRC 6 BIT ERROR COUNTER LSB RSBB...

Page 116: ...lative number of instances that Receive Loss of Frame condition have been detected by the T1 Framer since the last read of this register NOTE This counter counts once every time the Loss of Frame cond...

Page 117: ...PRBS Bit Error counter NOTE For all 16 bit wide PMON registers user must read the MSB counter first before reading the LSB counter in order to read the accurate PMON counts To clear PMON count user m...

Page 118: ...the Receive T1 Excessive Zero Violation counter NOTE For all 16 bit wide PMON registers user must read the MSB counter first before reading the LSB counter in order to read the accurate PMON counts T...

Page 119: ...read of this register 6 FCSEC2 6 RUR 0 5 FCSEC2 5 RUR 0 4 FCSEC2 4 RUR 0 3 FCSEC2 3 RUR 0 2 FCSEC2 2 RUR 0 1 FCSEC2 1 RUR 0 0 FCSEC2 0 RUR 0 TABLE 114 PMON LAPD2 FRAME CHECK SEQUENCE ERROR COUNTER 3...

Page 120: ...Block is NOT currently declaring the Loss of Recovered Clock interrupt 1 Indicates that the T1 Receive Framer Block is currently declar ing the Loss of Recovered Clock interrupt NOTE This bit is only...

Page 121: ...ce 1 Indicates the Alarm Error Block has an interrupt request await ing service Interrupt service routine should branch to the interrupt source and read the corresponding alarm and error status regist...

Page 122: ...f Recovered Clock Interrupt Enable This bit permits the user to either enable or disable the Loss of Recovered Clock Interrupt for interrupt generation 0 Disables the Loss of Recovered Clock Interrupt...

Page 123: ...larm Error interrupts will be dis abled for interrupt generation If the user writes a 1 to this register bit the Alarm Error Block interrupt at the Block Level will be enabled However the individual A...

Page 124: ...Receive T1 Framer block is currently declaring the Yellow Alarm condition within the incoming T1 data stream as described below Yellow alarm or Remote Alarm Indication RAI is declared when RAI conditi...

Page 125: ...nce the last read of this register If this interrupt is enabled then the Receive T1 Framer block will generate an interrupt in response to either one of the following conditions 1 Whenever the Receive...

Page 126: ...t that the Receive T1 Framer block clears the Out of Frame defect condition 0 Disables the Change in Out of Frame Defect Condition Interrupt 1 Enables the Change in Out of Frame Defect Condition Inter...

Page 127: ...R WC 0 Change in Signaling Bits Interrupt Status This Reset Upon Read bit field indicates whether or not the Change in Signaling Bits interrupt has occurred since the last read of this register If thi...

Page 128: ...red to mimic the Framing Bit pattern within the incoming T1 data stream 0 Indicates that the Frame Mimic Detection interrupt has not occurred since the last read of this register 1 Indicates that the...

Page 129: ...mine which sig nalling channel has changed state 0 Disables the Change in Signaling Bits Interrupt 1 Enables the Change in Signaling Bits Interrupt NOTE This bit has no meaning when Robbed Bit Signali...

Page 130: ...ce If the user enables this interrupt then the Receive T1 Framer block will generate an inter rupt when it detects a CRC 6 error within the incoming T1 multiframe 0 Disables the CRC 6 Error Detection...

Page 131: ...r 1 Transmit HDLC1 Controller Start of Transmission interrupt TxSOT has occurred since the last read of this register 5 RxSOT RUR WC 0 Receive HDLC1 Controller Start of Reception RxSOT Interrupt Statu...

Page 132: ...terrupt has occurred since the last read of this regis ter 1 Rx ABORT RUR WC 0 Receipt of Abort Sequence Interrupt Status This Reset Upon Read bit indicates whether or not the Receipt of Abort Sequenc...

Page 133: ...e an interrupt when it has started to receive a data link message 0 Disables the Receive HDLC1 Controller Start of Reception RxSOT interrupt 1 Enables the Receive HDLC1 Controller Start of Reception R...

Page 134: ...t is enabled the Receive HDLC1 Controller will generate an interrupt when it has detected the Abort Sequence i e a string of seven 7 consecutive 1 s within the incoming data link channel 0 Disables th...

Page 135: ...then a full frame of data will be repeated and this interrupt bit will be set to 1 0 Indicates that the Transmit Slip Buffer Empty interrupt has not occurred since the last read of this register 1 In...

Page 136: ...tus 0 Indicates that the T1 Receive Framer is currently declaring T1 multiframe LOCK status 2 RxSB_FULL RUR WC 0 Receive Slip buffer Full Interrupt Status This Reset Upon Read bit indicates whether or...

Page 137: ...errupt has occurred since the last read of this register The Receive Slip Buffer Slips interrupt is declared when the receive slip buffer is either filled or emptied This interrupt bit will be set to...

Page 138: ...operation occurs then a full frame of data will be repeated and the interrupt status bit will be set to 1 0 Disables the Transmit Slip Buffer Empty interrupt when the Transmit Slip Buffer empties 1 E...

Page 139: ...isables the Receive Slip Buffer Empty interrupt when the Trans mit Slip Buffer empties 1 Enables the Receive Slip Buffer Empty interrupt when the Trans mit Slip Buffer empties 0 RxSLIP_ENB R W 0 Recei...

Page 140: ...vation Code interrupt Status This Reset Upon Read bit field indicates whether or not the Change in Receive Loopback Activation Code interrupt has occurred since the last read of this register If this...

Page 141: ...pback Activation Code 0 Disables the Change in Receive Loopback Activation Code interrupt within the T1 Receive Framer 1 Enables the Change in Receive Loopback Activation Code interrupt within the T1...

Page 142: ...Change in Excessive Zero Condition interrupt has NOT occurred since the last read of this register 1 Indicates the Change in Excessive Zero Condition interrupt has occurred since the last read of this...

Page 143: ...than 276 Bytes in length 0 Indicates that the SS7 interrupt has not occurred since the last read of this register 1 Indicates that the SS7 interrupt has occurred since the last read of this register T...

Page 144: ...s 1 Whenever the Receive T1 Framer block declares the Receive LOS condition 2 Whenever the Receive T1 Framer block clears the Receive LOS condition 0 Indicates that the Change in Receive LOS Condition...

Page 145: ...errupt Status This Reset Upon Read bit field indicates whether or not the Change in Receive Loopback Activation Code interrupt has occurred since the last read of this register If this interrupt is en...

Page 146: ...pback Activation Code 0 Disables the Change in Receive Loopback Activation Code interrupt within the T1 Receive Framer 1 Enables the Change in Receive Loopback Activation Code interrupt within the T1...

Page 147: ...r 1 Transmit HDLC2 Controller Start of Transmission interrupt TxSOT has occurred since the last read of this register 5 RxSOT RUR WC 0 Receive HDLC2 Controller Start of Reception RxSOT Interrupt Statu...

Page 148: ...terrupt has occurred since the last read of this regis ter 1 Rx ABORT RUR WC 0 Receipt of Abort Sequence Interrupt Status This Reset Upon Read bit indicates whether or not the Receipt of Abort Sequenc...

Page 149: ...e an interrupt when it has started to receive a data link message 0 Disables the Receive HDLC2 Controller Start of Reception RxSOT interrupt 1 Enables the Receive HDLC2 Controller Start of Reception R...

Page 150: ...t is enabled the Receive HDLC2 Controller will generate an interrupt when it has detected the Abort Sequence i e a string of seven 7 consecutive 1 s within the incoming data link channel 0 Disables th...

Page 151: ...than 276 Bytes in length 0 Indicates that the SS7 interrupt has not occurred since the last read of this register 1 Indicates that the SS7 interrupt has occurred since the last read of this register T...

Page 152: ...errupt Status This Reset Upon Read bit field indicates whether or not the Change in Receive Loopback Activation Code interrupt has occurred since the last read of this register If this interrupt is en...

Page 153: ...pback Activation Code 0 Disables the Change in Receive Loopback Activation Code interrupt within the T1 Receive Framer 1 Enables the Change in Receive Loopback Activation Code interrupt within the T1...

Page 154: ...errupt Status This Reset Upon Read bit field indicates whether or not the Change in Receive Loopback Activation Code interrupt has occurred since the last read of this register If this interrupt is en...

Page 155: ...pback Activation Code 0 Disables the Change in Receive Loopback Activation Code interrupt within the T1 Receive Framer 1 Enables the Change in Receive Loopback Activation Code interrupt within the T1...

Page 156: ...errupt Status This Reset Upon Read bit field indicates whether or not the Change in Receive Loopback Activation Code interrupt has occurred since the last read of this register If this interrupt is en...

Page 157: ...pback Activation Code 0 Disables the Change in Receive Loopback Activation Code interrupt within the T1 Receive Framer 1 Enables the Change in Receive Loopback Activation Code interrupt within the T1...

Page 158: ...errupt Status This Reset Upon Read bit field indicates whether or not the Change in Receive Loopback Activation Code interrupt has occurred since the last read of this register If this interrupt is en...

Page 159: ...pback Activation Code 0 Disables the Change in Receive Loopback Activation Code interrupt within the T1 Receive Framer 1 Enables the Change in Receive Loopback Activation Code interrupt within the T1...

Page 160: ...errupt Status This Reset Upon Read bit field indicates whether or not the Change in Receive Loopback Activation Code interrupt has occurred since the last read of this register If this interrupt is en...

Page 161: ...pback Activation Code 0 Disables the Change in Receive Loopback Activation Code interrupt within the T1 Receive Framer 1 Enables the Change in Receive Loopback Activation Code interrupt within the T1...

Page 162: ...errupt Status This Reset Upon Read bit field indicates whether or not the Change in Receive Loopback Activation Code interrupt has occurred since the last read of this register If this interrupt is en...

Page 163: ...pback Activation Code 0 Disables the Change in Receive Loopback Activation Code interrupt within the T1 Receive Framer 1 Enables the Change in Receive Loopback Activation Code interrupt within the T1...

Page 164: ...gister 1 Transmit HDLC3 Controller Start of Transmission interrupt TxSOT has occurred since the last read of this register 5 RxSOT RUR WC 0 Receive HDLC3 Controller Start of Reception RxSOT Interrupt...

Page 165: ...interrupt has occurred since the last read of this register 1 Rx ABORT RUR WC 0 Receipt of Abort Sequence Interrupt Status This Reset Upon Read bit indicates whether or not the Receipt of Abort Sequen...

Page 166: ...e an interrupt when it has started to receive a data link message 0 Disables the Receive HDLC3 Controller Start of Reception RxSOT interrupt 1 Enables the Receive HDLC3 Controller Start of Reception R...

Page 167: ...t is enabled the Receive HDLC3 Controller will generate an interrupt when it has detected the Abort Sequence i e a string of seven 7 consecutive 1 s within the incoming data link channel 0 Disables th...

Page 168: ...than 276 Bytes in length 0 Indicates that the SS7 interrupt has not occurred since the last read of this register 1 Indicates that the SS7 interrupt has occurred since the last read of this register T...

Page 169: ...he AIS CI condition 1 Indicates the Receive T1 Framer is currently detecting the AIS CI condi tion NOTE This bit only works if AIS CI detection is enabled Register 0xN11C 4 RxRAI CI_state RO 0 Rx RAI...

Page 170: ...the Change in RAI CI Condition interrupt has NOT occurred since the last read of this register 1 Indicates the Change in RAI CI Condition interrupt has occurred since the last read of this register TA...

Page 171: ...t when 3 or more consecutive Non BOC messages occur Non BOC means that the message meets the 0xxxxxx011111111 framing format but does not contain a valid BOC 0 No Change 1 BOC Cleared BIT 4 RFDL Abort...

Page 172: ...cator of a complete BOC transmission for system alert or to initiate a response for future processing 0 Not Emptied 1 Emptied BIT 1 Receive FDL Match 1 Event This bit is set when the receive FDL messa...

Page 173: ...errupt 0 Disabled 1 Interrupt Enabled BIT 3 RFDL Register Full Event This bit is used to enable the RFDL Full Interrupt 0 Disabled 1 Interrupt Enabled BIT 2 TFDL Register Empty Event This bit is used...

Page 174: ...ed from its previous value IF the SSM message was valid Therefore this interrupt is only active once the BOC has received a valid SSM message This register is Reset Upon Read 0 No Change in SSM 1 Chan...

Page 175: ...ned as anytime the receive SSM message has changed from its previous value IF the SSM message was valid Therefore this interrupt is only active once the BOC has received a valid SSM message 0 Disabled...

Page 176: ...neration is enabled 0 Normal Operation PRBS generator is output on TTIP and TRING if PRBS generation is enabled 1 PRBS Generator is output on RPOS and RCLK 5 RXON_n R W 0 Receiver ON This bit permits...

Page 177: ...o be controlled by using the Arbitrary mode where users can specify the amplitude of the pulse shape by using the 8 Arbitrary Pulse Segments provided in the LIU registers 0xNF08 0xNF0F where n is the...

Page 178: ...0 TP 0x0Ch T1 Short Haul 15dB 533 to 655 feet 3 0dB 100 TP 0x0Dh T1 Short Haul 15dB Arbitrary Pulse 100 TP 0x0Eh T1 Gain Mode 29dB 0 to 133 feet 0 6dB 100 TP 0x0Fh T1 Gain Mode 29dB 133 to 266 feet 1...

Page 179: ...termination impedance when the LIU block is configured in Internal Termination Mode In internal termination mode i e TXTSEL 1 and RXTSEL 1 internal transmit and receive termination can be selected ac...

Page 180: ...LIU Block 1 JABW_n R W 0 Jitter Attenuator Bandwidth Select In T1 mode the Jitter Attenuator Bandwidth is always 3Hz and this bit has no effect on the Jitter Attenuator Bandwidth The FIFOS bit D0 of...

Page 181: ...quence PRBS with no more than 14 consecutive zeros TAOS Transmit All Ones Whenever the user implements this configuration setting the Trans mit T1 LIU Block will ignore the data that it is accepting f...

Page 182: ...86VX38 device and tri states the TTIP and TRING output pins 1 Turns on the Transmit Driver associated with the XRT86VX38 device NOTE If the user wishes to exercise software control over the state of t...

Page 183: ...04 an interrupt will be generated Automatic Loop Up Code Detection and Remote Loop Back Activation Enable When this mode is enabled the state of the NLCD bit bit 3 of regis ter 0xNF05 is reset to 0 an...

Page 184: ...this bit location before writing a 1 1 INSBER_n R W 0 Insert Bit Error This bit is used to insert a single bit error on the transmitter of the T1 LIU Block When the T1 LIU Block is configured to tran...

Page 185: ...t Status Interrupt 1 Enables the FIFO Limit Status Interrupt 4 LCVIE_n R W 0 Line Code Violation Interrupt Enable Writing a 1 to this bit enables Line Code Violation Interrupt generation writing a 0 m...

Page 186: ...the Receive Section within XRT86VX38 clears the LOS Defect condition 0 Disables the Change in the LOS Defect Condition Interrupt 1 Enables the Change in the LOS Defect Condition Interrupt 0 QRPDIE_n R...

Page 187: ...6VX38 is NOT cur rently declaring the Transmit DMO Alarm condition 1 Indicates that the Transmit Section of XRT86VX38 is currently declaring the Transmit DMO Alarm condition NOTE If the DMO interrupt...

Page 188: ...ode detection mode i e If NLCDE1 1 and NLCDE0 1 the state of the NLCD sta tus bit is reset to 0 and the XRT86VX38 is programmed to monitor the receive input data for the Loop Up code This bit is set t...

Page 189: ...the Receive Section is currently declaring the LOS Defect condition NOTE If the RLOSIE bit bit D1 of Register 0xNF04 is enabled any transition on this bit will generate an Interrupt 0 QRPD_n RO 0 Quas...

Page 190: ...pt has NOT occurred since the last read of this register 1 Indicates that the FIFO Limit Status Interrupt has occurred since the last read of this register This bit is set to a 1 every time when FIFO...

Page 191: ...Receive LOS Defect Condition Interrupt has occurred since the last read of this register NOTE The user can determine the current state of the Receive LOS Defect condition by reading out the contents...

Page 192: ...y TABLE 170 LIU CHANNEL CONTROL ARBITRARY REGISTER 1 LIUCCAR1 HEX ADDRESS 0X0FN8 BIT FUNCTION TYPE DEFAULT DESCRIPTION OPERATION 7 Reserved R W 0 6 0 Arb_Seg1 R W 0 Arbitrary Transmit Pulse Shape Segm...

Page 193: ...b_seg4 R W 0 Arbitrary Transmit Pulse Shape Segment 4 These seven bits form the forth of the eight segments of the transmit shape pulse when the XRT86VX38 is configured in Arbitrary Mode These seven b...

Page 194: ...g7 R W 0 Arbitrary Transmit Pulse Shape Segment 7 These seven bits form the seventh of the eight segments of the transmit shape pulse when the XRT86VX38 is configured in Arbi trary Mode These seven bi...

Page 195: ...abled the Transmit T1 Framer Block will automat ically transmit an All Ones data to the line for the channel that detects an RLOS condition 0 Disables the Automatic Transmit All Ones feature upon dete...

Page 196: ...rrupt to the Microprocessor pin 0 Disables the global interrupt generation for all channels within the E1 LIU Block 1 Enables the global interrupt generation for all channels within the E1 LIU Block 0...

Page 197: ...be set to 1 to enable ExLOS This only applies to the receiver NOTE 2 If RLOS is required to meet G 775 in this mode and not ExLOS then the CLOS 5 0 bits in Register 0x0FN7 can be used See Register 0x...

Page 198: ...ng Enable This bit allows users to tristate the output pins of all channels for in circuit testing purposes When In Circuit Testing is enabled all output pins of the XRT86VX38 are Tri stated When In C...

Page 199: ...ut 3 0 These four bits allow users to select the programmable input clock rates for the MCLKIN input pin according to the table below NOTE User must provide any one of the above clock frequencies to t...

Page 200: ...WC 0 Global Channel 0 Interrupt Status Indicator This Reset Upon Read bit field indicates whether or not an interrupt has occurred on Channel 0 within the XRT86VX38 device since the last read of this...

Page 201: ...256 PIN FINE PITCH BALL GRID ARRAY 256 Fine Pitch Ball Grid Array 17 0 mm x 17 0 mm fpBGA Rev 1 00 SYMBOL MIN MAX MIN MAX A 0 058 0 070 1 48 1 78 A1 0 013 0 017 0 33 0 43 A2 0 045 0 053 1 15 1 35 D 0...

Page 202: ...MAX MIN MAX A 0 056 0 067 1 43 1 71 A1 0 010 0 014 0 26 0 36 A2 0 046 0 053 1 17 1 35 D 0 663 0 675 16 85 17 15 D1 0 567 BSC 14 40 BSC b 0 014 0 018 0 36 0 46 e 0 031 BSC 0 80 BSC INCHES MILLIMETERS...

Page 203: ...veness Products are not authorized for use in such applications unless EXAR Corporation receives in writing assurances to its satisfaction that a the risk of injury or damage has been minimized b the...

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