XRT86VL38
PRELIMINARY
xr
OCTAL T1/E1/J1 FRAMER/LIU COMBO
REV. P1.0.6
59
3.
Assert the ALE/AS* (Address-Strobe) input pin by toggling it low. This step enables the Address Bus input
drivers, within the Microprocessor Interface Block of the XRT86VL38 device.
4.
After allowing the data on the Address Bus pins to settle (by waiting the appropriate "Address Setup" time),
the microprocessor should toggle the ALE/AS* input pin "high". This step causes the XRT86VL38 device
to latch the contents of the "Address Bus" into its internal circuitry. At this point, the address of the register
or buffer location (within the XRT86VL38 device) has now been selected.
5.
Afterwards, the microprocessor should indicate that this cycle is a "Read" cycle by setting the WR*/R/W*
(R/W*) input pin "high".
6.
Next the microprocessor should initiate the current bus cycle by toggling the RD*/DS* (Data Strobe) input
pin "low". This step enables the bi-directional data bus output drivers, within the XRT86VL38 device. At
this point, the bi-directional data bus output drivers will proceed to driver the contents of the "Address" reg-
ister onto the bi-directional data bus, D[7:0].
7.
Immediately after the microprocessor toggles the "Data Strobe" (RD*/DS*) signal "low", the XRT86VL38
device will continue to drive the RDY*/DTACK* output pin "high". The XRT86VL38 device does this in
order to inform the microprocessor that the data (to be read from the data bus) is "NOT READY" to be
latched into the microprocessor. In this case, the microprocessor should continue to hold the "Data
Strobe" (RD*/DS*) signal "low" until it detects the "RDY*/DTACK*" output pin toggling "low".
8.
After some settling time, the data on the "bi-directional" data bus will stabilize and can be read by the
microprocessor. The XRT86VL38 device will indicate that this data can be read by asserting the RDY*/
DTACK* (DTACK) output signal (by toggling it "low").
9.
After the microprocessor detects the RDY*/DTACK* signal (from the XRT86VL38 device) toggling "low", it
can terminate the Read Cycle by toggling the "RD*/DS*" (Data Strobe) input pin "high".
Figure presents a timing diagram that illustrates the behavior of the Microprocessor Interface signals during a
"Motorola-Asynchronous" Read Operation.
3.2.2
The Motorola-Asynchronous Write-Cycle
F
IGURE
6. M
OTOROLA
A
SYNCHRONOUS
M
ODE
I
NTERFACE
S
IGNALS
D
URING
R
EAD
O
PERATIONS
ALE/AS
RD*/DS*
A[14:0]
CS*
D[7:0]
RDY/DTACK*
Not Valid
Valid Data
Address of Target Register
WR*/R/W*
Microprocessor places “target”
Address value on A[14:0]
Microprocessor Interface latches contents on
A[14:0] upon rising edge of AS*
Address Decoding
Circuitry asserts
CS*
Microprocessor keeps R/W* “high”
To denote READ Operation
Read Operation begins
Here
DTACK* toggles “low” to indicate
That valid data can be read from
D[7:0]
Read Operation is
Terminated Here
