Detailed
Specifications
Issue A
27
LPC Bus Components
The ICH7-M LPC bus is connected to components listed below:
Super I/O chipset
LPC Serial Port Chipset
iTE IT8718F Super I/O Chipset
The iTE IT8718F Super I/O chipset is connected to the ICH7-M through the LPC bus.
Figure 18: Super I/O
The iTE IT8718F is an LPC interface-based Super I/O device that comes with
Environment Controller integration. Some of the features of the iTE IT8718F chipset are
listed below:
ACPI and LANDesk Compliant
Enhanced Hardware Monitor
Fan Speed Controller
Two 16C550 UARTs for serial port control
One IEEE 1284 Parallel Port
Keyboard Controller
Watchdog Timer
Some of the Super I/O features are described in more detail below:
Super I/O LPC Interface
The LPC interface on the Super I/O complies with the Intel
®
Low Pin Count Specification
Rev. 1.0. The LPC interface supports both LDRQ# and SERIRQ protocols as well as PCI
PME# interfaces.
Summary of Contents for ALUDRA
Page 116: ...ALUDRA user manual Issue A 116 Appendix D Address Mapping I O Address Map ...
Page 117: ...Appendix D Address Mapping Issue A 117 Table IO Address Map ...
Page 118: ...ALUDRA user manual Issue A 118 IRQ Address Map Table IRQ Address Map ...
Page 119: ...Appendix D Address Mapping Issue A 119 Memory Address Map Table Memory Address Map ...
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