ETAS
Hardware Description
FETK-T3.0 - User’s Guide
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4.10.3.2 FETK Trigger Generation
To generate triggers, the ECU software sets bits by writing the associated trig-
ger index in the microcontroller trigger registers (DBG_TRGx). Each bit of the
trigger registers corresponds to an FETK hardware trigger.
The FETK periodically polls (reads) the trigger registers via JTAG. The polling
rate is configurable, with 50 µs default. The FETK then starts acquisition of
appropriate measurement data based on which bits of the registers are set.
Active bits in trigger registers are automatically cleared by microcontroller
when the registers are read by FETK.
4.10.4
Timer Triggering
The trigger mode "Timer Triggering" uses four internal timers of the FETK-T3.0
for triggering. A fixed configurable period is used for triggering.
The time intervals between trigger events are in accordance with the config-
ured timer values. This values and their resolution have to be defined in the A2L
file. Available settings are:
• Minimum time interval 100 µs
• Maximum period duration 1 s
• Timer resolution 1 µs
The timers work in an asynchronous manner to the ECU software.
NOTE
The selective setting of trigger bits is accomplished in hardware by the micro-
controller and does not require a Read-Modify-Write sequence by the ECU
software.
