ETK-V1.1 - User’s Guide
27
ETAS
Hardware Description
4.12
Braindead Flashing
Braindead Flashing (BDF) means downloading program code to the non-volatile
memory of the ECU (i.e. internal or external flash), regardless of the current
memory contents. It is not required that a programming routine is present in the
ECU - the memory may be empty or corrupted.
The ETK-V1.1 features Braindead Flashing with two methods:
• BDF via JTAG debug interface is supported for all MPC5500 family micro-
controllers. It is recommended as standard method for all new projects.
• BDF via chip select remapping is available for MPC5554 microcontrollers
only. It is supported for existing projects for compatibility reasons.
4.12.1
Braindead Flashing via JTAG Debug Interface
This method uses the JTAG interface of the MCU's microcontroller to enable the
debug mode of microcontroller and to download a flash programming driver
into the microcontroller's internal SRAM.
After download, the microcontroller is given a resume/go command. It executes
the programming driver which receives data via the ETK mailbox and programs it
into the microcontroller's flash. When flash programming is done, a reset is
issued and the microcontroller executes the recently programmed code.
The following steps are sequenced by a ProF control flow:
• Put ECU's microcontroller into reset
• Disable external watchdog timer (optional, see chapter 4.12.3
• Initiate microcontroller's debug mode and halt state
• Initialize the MMU registers to a known state
• Initialize the Internal SRAM
• Download flash programming driver into the internal RAM region of the
controller that contains communication and flash routines
• Set Program Counter to point to the beginning of the boot code
• Resume microcontroller code execution by issuing a go/resume command
• Program the new ECU software to the non-volatile memory (internal or
external flash)
• Reset the CPU (release JTAG debug interface control)
Note
During BDF via JTAG, debugger access to the ECU's microcontroller is not pos-
sible. The ETK-V1.1 logic takes exclusive control over the microcontroller's
JTAG interface. A debugger attached to the JTAG/Nexus connector (Mictor 38
pin) will not work until the final reset command is issued from the ProF com-
mand flow.
