ETAS
Hardware Description
BR_XETK-S4.0
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User
Guide
24
4.8
Trigger Modes
4.8.1
Overview
The BR_XETK-S4.0 supports the following trigger modes:
• Pinless triggering
• Timer triggering
4.8.2
Pinless Triggering
4.8.2.1
Startup Handshake
The JTAG Data Communication (JDC) register is used to generate process the
XETK startup handshake. The ECU must ensure that all memory ECC initializa
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tion has been completed prior to the start-up handshake.
For further information on ECC initialization, please refer to the microcontrol
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ler's reference manual.
4.8.2.2
XETK Trigger Generation
To generate triggers, the ECU software sets bits by writing the associated trig
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ger index in the "DTS_SEMAPHORE" register.
Each bit of the "DTS_SEMAPHORE" corresponds to an XETK hardware trigger.
Within the XETK’s configuration and/or A2L file, bit 0 corresponds to hardware
trigger 1 and bit 31 corresponds to hardware trigger 32.
The XETK periodically polls (reads) "DTS_SEMAPHORE" via JTAG. The polling
rate is configurable, with 50 µs default. The XETK then starts acquisition of
appropriate measurement data based on which bits of the register are set.
Active bits in "DTS_SEMAPHORE" are automatically cleared by the microcon
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troller when the register is read by XETK.
4.8.3
Timer Triggering
The trigger mode "Timer Triggering" uses four internal timers of the BR_XETK-
S4.0 for triggering. A fixed configurable period is used for triggering.
The time intervals between trigger events are in accordance with the config
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ured timer values. These values and their resolution must be defined in the A2L
file. Available settings are:
NOTE
The selective setting of trigger bits is accomplished in hardware by the micro
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controller and does not require a Read-Modify-Write sequence by the ECU
software.
NOTE
Only the index 0 to 31 corresponding to the first 32 triggers are supported by
the BR_XETK-S4.0
