ERM Neoverse N1 Technical Reference Manual Download

Page: 98 / 241

Table 4-10 Shared peripheral interrupts (continued)

Source

Description

263

MMUTCU2_PMU_IRPT

PMU interrupt

264

MMUTCU2_EVENT_Q_IRPT_S

Event Queue Secure interrupt, indicating Event Queue Non-Empty or Overflow

265

MMUTCU2_CMD_SYNC_IRPT_S

SYNC Complete Secure interrupt

266

MMUTCU2_GLOBAL_IRPT_S

Global Secure interrupt

267

MMUTCU2_EVENT_Q_IRPT_NS

Event Queue non-Secure interrupt, indicating Event Queue Non-Empty or
Overflow

268

MMUTCU2_CMD_SYNC_IRPT_NS

SYNC Complete Non-secure interrupt

269

MMUTCU2_GLOBAL_IRPT_NS

Global Non-secure interrupt

319-270 -

Reserved

323-320 MMUTBU_PMU_IRPT[3:0]

TBU PMU Interrupt. Allocated to 4 TBUs in the system.

511-324 -

Reserved

512

CLUSTER0SCP ->AP MHU Non-secure

513

CLUSTER0SCP ->AP MHU secure

514

CLUSTER1SCP ->AP MHU Non-secure

515

CLUSTER1SCP ->AP MHU secure

575-516 -

Reserved

576

P0_REFCLK_GENTIM

Pn_REFCLK Generic Secure Timer interrupts

577

P0_REFCLK_GENTIM

Pn_REFCLK Generic Secure Timer interrupts

640-578 -

Reserved

4.3.2

System Control Processor interrupt map

The

System Control Processor

(SCP) receives interrupts from several sources.

The sources of the interrupts to the SCP are:
• Application Processor system wakeup interrupts
• CoreSight power and reset request interrupts
• Internal SCP subsystem interrupts
• Expansion SCP interrupts

The interrupts are routed to the Nested Vector Interrupt Controllers in Cortex

‑

M7 processors where they

can be managed by software.

The following table shows the SCP interrupts.

Table 4-11 SCP interrupts

Source

Description

NMI

SCP Generic Watchdog

SCP Watchdog(WS0)

Reserved

4 Programmers model

4.3 N1 SoC interrupt maps

101489_0000_02_en

reserved.

4-98

Non-Confidential - Beta

Summary of Contents for Neoverse N1

Page 2: ...N ANY DIRECT INDIRECT SPECIAL INCIDENTAL PUNITIVE OR CONSEQUENTIAL DAMAGES HOWEVER CAUSED AND REGARDLESS OF THE THEORY OF LIABILITY ARISING OUT OF ANY USE OF THIS DOCUMENT EVEN IF ARM HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES This document consists solely of commercial items You shall be responsible for ensuring that any use duplication or disclosure of this document complies fully with ...

Page 3: ... requested Recycle it using local WEEE recycling facilities These facilities are now very common and might provide free collection If purchased directly from Arm Arm provides free collection Please e mail weee arm com for instructions The CE Declaration of Conformity for this product is available on request The system should be powered down when not in use It is recommended that ESD precautions be...

Page 4: ...etting started 1 19 1 5 Accessing the ATX power cables 1 20 Chapter 2 Hardware description 2 1 N1 SDP hardware 2 22 2 2 N1 SoC 2 25 2 3 External power 2 27 2 4 Clocks 2 28 2 5 Resets 2 35 2 6 IOFPGA 2 37 2 7 HDLCD video 2 43 2 8 PCI Express and CCIX systems 2 45 2 9 Chip to Chip communications 2 48 2 10 UARTs 2 51 101489_0000_02_en Copyright 2019 2020 Arm Limited or its affiliates All rights reser...

Page 5: ...registers 4 105 4 5 Serial Configuration Control registers 4 119 4 6 APB system registers 4 197 4 7 APB energy meter registers 4 206 4 8 UART memory addresses and control registers 4 225 Appendix A Signal descriptions A 1 UART headers Appx A 229 A 2 UART DB9 connectors Appx A 231 A 3 N1 SoC JTAG connector Appx A 232 A 4 Trace connector Appx A 233 A 5 Front panel I O header Appx A 235 A 6 PCI Expre...

Page 6: ...erse N1 System Development Platform Technical Reference Manual It contains the following About this book on page 7 Feedback on page 10 101489_0000_02_en Copyright 2019 2020 Arm Limited or its affiliates All rights reserved 6 Non Confidential Beta ...

Page 7: ... issues of this book Glossary The Arm Glossary is a list of terms used in Arm documentation together with definitions for those terms The Arm Glossary does not contain terms that are industry standard unless the Arm meaning differs from the generally accepted meaning See the Arm Glossary for more information Typographic conventions italic Introduces special terminology denotes cross references and...

Page 8: ...alue within the shaded area at that time The actual level is unimportant and does not affect normal operation Clock HIGH to LOW Transient HIGH LOW to HIGH Bus stable Bus to high impedance Bus change High impedance to stable bus Figure 1 Key to timing diagram conventions Signals The signal conventions are Signal level The level of an asserted signal depends on whether the signal is active HIGH or a...

Page 9: ...rtex M7 Processor Technical Reference Manual DDI 0489 Arm PrimeCell UART PL011 Technical Reference Manual DDI 0183 Arm PrimeCell General Purpose Input Output PL061 Technical Reference Manual DDI 0190 Arm PrimeCell Real Time Clock PL031 Technical Reference Manual DDI 0224 Arm Dual Timer SP804 Technical Reference Manual DDI 0271 Arm Watchdog Module SP805 Technical Reference Manual DDI 0270 Arm Prime...

Page 10: ...com Give The title Arm Neoverse N1 System Development Platform Technical Reference Manual The number 101489_0000_02_en If applicable the page number s to which your comments refer A concise explanation of your comments Arm also welcomes general suggestions for additions and improvements Note Arm tests the PDF only in Adobe Acrobat and Acrobat Reader and cannot guarantee the quality of the represen...

Page 11: ... following sections 1 1 Precautions on page 1 12 1 2 About the N1 SDP on page 1 13 1 3 The N1 SDP at a glance on page 1 14 1 4 Getting started on page 1 19 1 5 Accessing the ATX power cables on page 1 20 101489_0000_02_en Copyright 2019 2020 Arm Limited or its affiliates All rights reserved 1 11 Non Confidential Beta ...

Page 12: ...and that the fans have stopped turning before opening the chassis 1 1 2 Operating temperature The N1 SDP has been tested in the temperature range 15 C 30 C 1 1 3 Preventing damage The N1 SDP is intended for use within a laboratory or engineering development environment Caution If you remove the N1 SDP from the PC tower observe the following precautions Never subject the board to high electrostatic...

Page 13: ...tandard PC tower unit The N1 SoC contains two dual core Arm Neoverse N1 processor clusters The system demonstrates Arm technology in the context of Cache Coherent Interconnect for Accelerators CCIX protocol by Running coherent traffic between the N1 SoC and an accelerator card Coherent communication between two N1 SoCs Enabling development of CCIX enabled FPGA accelerators 1 Introduction 1 2 About...

Page 14: ...ower back panel and front panel and the N1 board Figure 1 1 Back panel Figure 1 2 Front panel reset buttons 1 Introduction 1 3 The N1 SDP at a glance 101489_0000_02_en Copyright 2019 2020 Arm Limited or its affiliates All rights reserved 1 14 Non Confidential Beta ...

Page 15: ...following table describes the components connectors and push buttons 1 Introduction 1 3 The N1 SDP at a glance 101489_0000_02_en Copyright 2019 2020 Arm Limited or its affiliates All rights reserved 1 15 Non Confidential Beta ...

Page 16: ...back panel The DB9 connectors are logically UARTs but the pins follow the RS232 specification 11 Chip to Chip C2C Connector Ribbon cable to Chip to Chip C2C connector 19 on board 12 Slot 4 PCIe CCIX 16 connector Board Remove side panel for access 16 lanes used Gen 4 link 13 Slot 3 PCIe 16 connector 8 lanes used 8 lanes unused Gen 3 link 14 Slot 2 PCIe 16 connector 16 lanes used Gen 3 link 15 Slot ...

Page 17: ... Connector Back panel Ribbon cable to Chip to Chip C2C connector 11 on back panel 20 RDIMM1 memory Board Remove side panel for access 21 RDIMM0 memory 22 ATX power connector and power indicator LEDs 23 User switch SW8 24 User switch SW1 25 Reserved for use by Arm 26 IOFPGA microSD card 27 IOFPGA 28 User LED0 29 User LED7 30 Reserved for use by Arm 31 IOFPGA JTAG 32 Platform Controller Chip PCC 33 ...

Page 18: ...o the front panel Connects to the power LED 41 On Off Soft reset push button PBON 42 Hardware reset button PBRESET Front panel 43 On Off Soft reset push button PBON and power LED 44 HDD activity LED Combined signal from SATA0 and SATA1 from front panel I O connector on board 1 Introduction 1 3 The N1 SDP at a glance 101489_0000_02_en Copyright 2019 2020 Arm Limited or its affiliates All rights res...

Page 19: ... SDP at a glance on page 1 14 for the location of the configuration switches 3 To complete the powerup sequence from the standby state briefly press the PBON button The system is now fully powered and in the operating state Editing configuration files The configuration microSD card contains the system configuration files To modify the system default settings edit or replace configuration files whi...

Page 20: ...ply Access the ATX power cables To access the ATX power cables you must gain access to the chassis 1 Remove the large metal side panel Undo the thumbscrews at the rear of the tower Slide the side panel away from the tower 2 The ATX power cables are now accessible folded up inside the tower Unfold the power cables to connect them to external hard drives 1 Introduction 1 5 Accessing the ATX power ca...

Page 21: ... 2 4 Clocks on page 2 28 2 5 Resets on page 2 35 2 6 IOFPGA on page 2 37 2 7 HDLCD video on page 2 43 2 8 PCI Express and CCIX systems on page 2 45 2 9 Chip to Chip communications on page 2 48 2 10 UARTs on page 2 51 2 11 LEDs switches and buttons on page 2 55 2 12 Debug on page 2 59 101489_0000_02_en Copyright 2019 2020 Arm Limited or its affiliates All rights reserved 2 21 Non Confidential Beta ...

Page 22: ...I IOFPGA Chip2Chip Thin Links TSIF Thin Links TMIF Thin Links TSIF SCC SCC MCP I2C SCP I2C SCP UART CTI UART UART UART AP UART MCP UART SCC UART UART UART SMC SCP I2C MCP I2C SCP I2C I2C I2C PMIC OSCCLK UART SMC DDR3 UART eMMC HDMI Dual 7 segment display microSD User LEDs 1 2 3 4 5 6 7 8 User switches Clock generators PLLs TLX 400 TLX 400 DBG USB Serial USB PORT4 PORT3 PORT1 PORT2 PCC Ethernet MCC...

Page 23: ...ory Cache Coherent Interconnect for Accelerators CCIX PCI Express 16 Gen 4 slot Connects to Gen 4 root complex and PHY on the N1 SoC PCI Express 48 lane 18 port Gen 3 switch Gigabit Ethernet controller 1 Gen 1 link to PCIe switch SATA 3 0 controller 1 Gen 2 link to PCIe switch USB 3 0 controller 1 Gen 2 link to PCIe switch 16 PCIe Gen 3 slot 8 PCIe Gen 3 slot 1 PCIe Gen 3 slot Four USB 3 0 ports f...

Page 24: ...on PBON Hardware reset button PBRESET Programmable oscillators JTAG debug port 32 bit Trace port Related information 1 3 The N1 SDP at a glance on page 1 14 2 Hardware description 2 1 N1 SDP hardware 101489_0000_02_en Copyright 2019 2020 Arm Limited or its affiliates All rights reserved 2 24 Non Confidential Beta ...

Page 25: ...256 bit switch 64 bit switch S S M S S M M AXI to APB PCIe RC PCIe PHY CCIX RC CCIX PHY GPIO CMN 600 Thin Links TLX 400 TSIF Thin Links TLX 400 TMIF IOFPGA IOFPGA GPIO Clock and resets Clock sources Resets UART JTAG IRQ DDR4 DDR4 IOFPGA CXLA N1 cluster 0 Core 0 Core 1 PVT sensors L3 FCM cache AP GTimer AP UART Secure Watchdog Generic Watchdog AP Secure GTimer NIC 400 Access control BP140 BP140 BP1...

Page 26: ...ace One Cache Coherent Interconnect for Accelerators CCIX Gen 4 root complex and PHY Connects to one 16 PCI Express slot Backwards compatible to PCI Express Gen 4 One PCIe Gen 4 root complex and PHY running as Gen 3 Connects to the following downstream slots and peripherals through a PCI Express Gen 3 switch One 16 PCI Express slot One 8 PCI Express slot One 1 PCI Express slot One 1 Gigabit Ethern...

Page 27: ...lands ATX Always On region Operates in standby state Powers the Motherboard Configuration Controller MCC and Platform Controller Chip PCC subsystems only Switched region Main board VIO and all other non MCC and non PCC supplies including the IOFPGA This arrangement enables the PCC to receive a request to place the board into standby state over its local Ethernet connection The following figure sho...

Page 28: ...rograms the clock generators according to default values defined in the io_v0 txt configuration file You can change the operational clock frequencies by modifying the configuration file See 3 3 3 Contents of the MB directory on page 3 65 for an example io_v txt configuration file Note Arm recommends that you operate the N1 board at the default clock frequencies 2 4 2 SoC clocks Programmable clock ...

Page 29: ...CLK SCPNICCLK SCPQSPICLK SCPI2CCLK MCPNICCLK MCPQSPICLK MCPI2CCLK PCIEAXICLK PCIEAPBCLK CCIXAPBCLK SYSAPBCLK TMIF2xCLK TSIF2xCLK PMCLK CCIXAXICLK REFCLK DDR4 PHY0 SCP expansion DDR4 PHY1 MCP expansion IOFPGA TSIF PCIe subsystem CCIX subsystem SYS expansion CCIX_CMN REFCLK PCIE_CMN REFCLK IOFPGA SCC TSIF CLK0 TSIF CLKI CFG F2S CLK TMIF CLKI TMIF CLKO P JTAG CPU0PLL SWCLKTCK CG Trace TRACE CLKA TRAC...

Page 30: ...ck for CLUSPLL Generates CLUSPLLCLK a common cluster clock for cluster 0 and cluster 1 DMCREFCLK OSC6 50MHz Reference clock for DMCPLL Generates DMCPLLCLK for the DDR subsystem INTREFCLK OSC4 50MHz Reference clock for INTPLL Generates INTPLLCLK for the CMN 600 Coherent Mesh Network SYSREFCLK OSC0 50MHz Reference clock for SYSPLL Generates the main system clock SYSPLLCLK and other clocks through pr...

Page 31: ...OFPGA with incoming data from IOFPGA TMIF_CLKO N1 SoC TLX 400 master interface 75MHz Thin Links based AXI master interface clock exported from N1 SoC with data transmitted from N1 SoC to IOFPGA TSIF_CLKI IOFPGA TLX 400 slave interface 80MHz Thin Links based AXI slave interface clock received from IOFPGA with incoming data from IOFPGA TSIF_CLKO N1 SoC TLX 400 slave interface 75MHz Thin Links based ...

Page 32: ... 128 TSIF2XCLK_DIV Sets value of divider value to generate TSIF2XCLK from SYSPLLCLK See 4 5 8 IOFPGA_TSIF2XCLK_DIV Register on page 4 129 SCPNICCLK_CTRL Selects input clock to generate SCPNICLK See 4 5 9 SCPNICCLK_CTRL Register on page 4 130 SCPNICCLK_DIV Sets value of divider value to generate SCPNICCLK from SYSPLLCLK See 4 5 10 SCPNICCLK_DIV Register on page 4 131 SCPI2CCLK_CTRL Selects input cl...

Page 33: ...4 144 CCIXAPBCLK_CTRL Selects input clock to generate CCIXAPBCLK See 4 5 29 CCIXAPBCLK_CTRL Register on page 4 145 CCIXAPBCLK_DIV Sets value of divider value to generate CCIXAPBCLK from SYSPLLCLK See 4 5 30 CCIXAPBCLK_DIV Register on page 4 146 SYS_CLK_EN Enables or disables internally generated clocks See 4 5 31 SYS_CLK_EN Register on page 4 146 CPU0_PLL_CTRL0 Control CPU0PLL to generate CPU0PLLC...

Page 34: ...lone clock for Real Time Clock RTC IOFPGA_DDR3_SYSCLK GTX clock 100MHz Drives DDR3 controller reference clock at 400MHz Thin Links based AXI master and slave interface clocks between IOFPGA and N1 SoC 75MHz from N1 SoC to IOFPGA 80MHz from IOFPGA to N1 SoC See 2 4 2 SoC clocks on page 2 28 for descriptions of Thin Links clocks SMBM_CLK MCC 40MHz SMB clock SMBP_CLK PCC 40MHz SMB clock CFG_M2F_CLK M...

Page 35: ...er up By default this button powers up the system in standby mode nPBON generates an interrupt to either the MCC or PCC to control the powerup sequence N1 SoC resets The N1 SoC has the following resets from the board Table 2 5 N1 SoC resets Reset Source Comment SOC_nPOR MCC IOFPGA Main powerup reset for the whole system except some SCC logic De assertion of this input initiates the powerup sequenc...

Page 36: ...d IOFPGA config PCC config AP boot IOFPGA_nPOR MCC IOFPGA IOFPGA_nRST MCC IOFPGA SOC_nPOR MCC IOFPGA SOC_nRST MCC IOFPGA Figure 2 5 Reset sequence Related information 1 3 The N1 SDP at a glance on page 1 14 2 Hardware description 2 5 Resets 101489_0000_02_en Copyright 2019 2020 Arm Limited or its affiliates All rights reserved 2 36 Non Confidential Beta ...

Page 37: ...GA The IOFPGA on the N1 board contains the following blocks and interfaces eMMC device microSD card controller QSPI controller DDR3 controller PL031 Real Time Clock RTC SP804 Timers SP805 Watchdog SP810 System controller PL011 UARTs GIC 400 interrupt controller 1MB SRAM I2C configuration of PCIe switch and HDMI PHY HDLCD APB mapping to user LEDs and switches APB mapped energy meter registers 2 Har...

Page 38: ...controller DDR3 AHB HDLCD HDMI video eMMC SDIO eMMC AXI AXI AXI AXI PLO61 1 I2S interface I2 S audio TLX 400 TMIF TLX 400 TSIF TLX 400 TMIF TLX 400 TSIF AXI AXI PCC SRAM AXI SMB to AHB SCP I2 C MCP I2 C QSPI QSPI controller AHB PLO61 0 UART IP1 PLO11 UART IP2 PL011 SCC SCC GIC 400 AXI AHB I3C interface I3C I3 C UART configurable mux demux system SCP UART MCP UART AP UART UART configurable mux demu...

Page 39: ...tem Control Processor SCP and the Manageability Control Processor MCP in the N1 SoC Implements a set of interrupt memory mapped registers accessible by the Application Processors AP over the Thin Links TXL 400 interface to determine the interrupt source The base address of the interrupt memory mapped registers is 0x1CA0_0000 The IOFPGA interrupts are separately combined and driven to the Platform ...

Page 40: ... F2MCC_INT F2PCC_INT AP SCP MCP nIRQCPU0 AP_EXTINT nIRQCPU1 SCP_EXTINT IRQ 19 MSCP_SS_RSTREQ nIRQCPU2 MCP_EXTINT IRQ 34 IRQ 20 IRQ 21 IRQ 22 nIRQCPU3 IRQ 23 IRQ 24 IRQ 25 nIRQCPU4 AP_EXTAUXINT Figure 2 7 IOFPGA interrupt routing The following table shows the input interrupts to the GIC 400 Table 2 6 IOFPGA GIC 400 interrupt sources Interrupt ID IRQ level Source Comment IRQ 0 1 Timer 0 IRQ 1 1 Time...

Page 41: ..._EXTINT MCC to AP IRQ 21 1 M2F_SCP_EXTINT MCC to SCP IRQ 22 1 M2F_MCP_EXTINT MCC to MCP IRQ 23 1 P2F_AP_EXTINT PCC to AP IRQ 24 1 P2F_SCP_EXTINT PCC to SCP IRQ 25 1 P2F_MCP_EXTINT PCC to MCP IRQ 26 1 QSPI IRQ 27 1 I2S IRQ 28 1 I3C IRQ 29 1 DDR4 EEPROM I2C IRQ 30 0 DDR4_nEVENT0 IRQ 31 0 DDR4_nEVENT1 IRQ 32 0 PCIe_nWAKE IRQ 33 0 CCIX nWAKE IRQ 34 0 FATAL_ERRn from PCIe switch The following table sho...

Page 42: ...l Processor SCP N1 SoC nIRQCPU2 Manageability Control Processor MCP N1 SoC nIRQCPU3 Motherboard Configuration Controller MCC N1 board nIRQCPU4 Platform Controller Chip PCC N1 board 2 Hardware description 2 6 IOFPGA 101489_0000_02_en Copyright 2019 2020 Arm Limited or its affiliates All rights reserved 2 42 Non Confidential Beta ...

Page 43: ...k is derived from a clock generator on the N1 board and a PLL in the IOFPGA The RGB video connects to GPIO drivers in the IOFPGA that drive the HDMI transmitter PHY at up to 120MHz The PHY is a TDA19988 HDMI transmitter which drives the HDMI connector The Application Processor AP code configures the HDLCD controller and the Motherboard Configuration Controller MCC or AP configures the PHY over I2C...

Page 44: ...PXLPLLCLK N1 SoC Thin Links TMIF S TLX 400 DDR3 M M N1 clusters Thin Links TMIF M Figure 2 8 HDLCD interface Related information 1 3 The N1 SDP at a glance on page 1 14 2 Hardware description 2 7 HDLCD video 101489_0000_02_en Copyright 2019 2020 Arm Limited or its affiliates All rights reserved 2 44 Non Confidential Beta ...

Page 45: ...nology The N1 SoC and N1 board provide the Chip to Chip C2C sideband signals necessary for CCIX expansion The CCIX interface also functions as a standard PCIe Gen 4 interface One Gen 4 root complex on the N1 SoC connects directly to a Gen 3 switch Downstream of the switch provides access to three PCIe slots a four port USB 3 0 Host Controller a two port SATA controller and one Gigabit Ethernet por...

Page 46: ...TA ports are accessible by removing the side panel See1 3 The N1 SDP at a glance on page 1 14 2 8 2 PCI Express and CCIX expansion slots The following table shows the PCIe expansion slots on the N1 board Table 2 8 PCI Express expansion slots Slot number PCIe lane connector size Number of lanes connected Unused lanes Comment Slot 1 4 1 3 PCIe Slot 2 16 16 0 PCIe Slot 3 16 8 8 PCIe Slot 4 16 16 0 PC...

Page 47: ...connects to the Gigabit Ethernet GbE controller over a 1 Gen 1 1 link The GbE controller drives an RJ45 GbE port on the back panel The GbE controller is a RealTek RTL8111GS device The controller provides a 10 100 1000Base T connection to the GbE port Related information 1 3 The N1 SDP at a glance on page 1 14 2 8 5 USB 3 0 ports The PCI switch connects to a USB 3 0 Host controller over a single la...

Page 48: ...connectors are Cross Trigger Interface CTI System counter synchronization REFCLK handshaking synchronization SCP I2C MCP I2C CoreSight debug JTAG The following figure shows the CTI and synchronization signals N1 board N1 board N1 SoC CNTSYNC_OUT CNTSYNC_IN CTSSYNC_OUT CTSSYNC_IN CTITRIG_OUT CTITRIG_IN CTITRIG_OUTACK CTITRIG_INACK N1 SoC CNTSYNC_OUT CNTSYNC_IN CTSSYNC_OUT CTSSYNC_IN CTITRIG_OUT CTI...

Page 49: ... register pullups 4 MCC updates the SCC registers in the IOFPGA with CHIP_ID and multi chip support 5 MCC releases the N1 SoC from reset 6 The SCP or MCP reads the SCC registers and configures the CCIX root port appropriately CCIX root complex master CCIX endpoint slave This sequence includes several layers of PCIe and CCIX bring up across the links to verify the root complex register configuratio...

Page 50: ...aster and slave N1 boards The following are necessary to enable CCIX traffic between the two N1 boards The master exports REFCLK The slave is configured to accept REFCLK from the master and distribute it locally The slave detects the PCIe reset nPERST from the master for the System Control Processor SCP to release the local PCIe internal reset This is done by driving nPERST from the slave into one...

Page 51: ...SDP UART system enables access to the N1 SoC and IOFPGA on the N1 board 2 Hardware description 2 10 UARTs 101489_0000_02_en Copyright 2019 2020 Arm Limited or its affiliates All rights reserved 2 51 Non Confidential Beta ...

Page 52: ...RT1 5 2 way header PORT2 UART2 5 2 way header PORT3 PORT4 UART3 5 2 way header Ribbon cable UART1 back panel USB1 USB2 USB3 USB4 USB USB No connection USB UART USB MCC USB PCC Permanent connection Configurable connection default Configurable connection non default Key UART RS232 Ribbon cable UART RS232 UART RS232 RS232 UART Ribbon cable connection AP UART1 MCP UART1 Figure 2 12 UART system 2 Hardw...

Page 53: ...nnected to the DBG USB port FPGAUART1 Not used FPGAUART2 Not used Operation and getting started When a serial terminal is connected to the DBG USB port but before mains power is applied The USB powers the USB hub and the Serial USB bridge The MCC and PCC UARTS are visible as COM ports The command prompt is not shown When mains power is applied the MCC and PCC are powered and the MCC command prompt...

Page 54: ...tor to the 5 2 way header UART1 on the board The header and DB9 connector pins follow the RS232 specification No pin 10 on the 5 2 way header UART2 UART2 5 2 way header on board The header pins follow the RS232 specification No pin 10 UART3 UART3 5 2 way header on board The header pins follow the RS232 specification No pin 10 PCC_UART4 UART4 port on PCC PCC_UART5 UART5 port on PCC PCC_UART6 UART6 ...

Page 55: ...orm Controller Chip PCC Table 2 13 PCC system LEDs LED Description Position Access Function RAS RDIMM LEDs 2 orange On N1 board One next to each RDIMM slot Remove side panel Indicates DDR4 configuration issues or that RAS events have occurred PCIe status LED 1 green On N1 board Near PCC Indicates that PCIe is properly configured and link training completed CCIX status LED 1 green Indicates that CC...

Page 56: ...Gen 1 Off Off Off Off On Off 0x2 1 Gen 2 Off Off Off Off On On 0x3 1 Gen 3 Off Off Off On Off Off 0x4 1 Gen 4 Off Off Off On Off On 0x5 2 Gen 1 Off Off Off On On Off 0x6 2 Gen 2 Off Off Off On On On 0x7 2 Gen 3 Off Off On Off Off Off 0x8 2 Gen 4 Off Off On Off Off On 0x9 4 Gen 1 Off Off On Off On Off 0xA 4 Gen 2 Off Off On Off On On 0xB 4 Gen 3 Off Off On On Off Off 0xC 4 Gen 4 Off Off On On Off O...

Page 57: ...buttons The hardware reset push buttons are PBON the ON OFF Soft Reset button PBRESET the Hardware reset button See 2 5 Resets on page 2 35 for a description of the functions of the hardware reset push buttons See 1 3 The N1 SDP at a glance on page 1 14 for the locations of the hardware reset buttons Configuration DIP switches There are two configuration DIP switches SW0 and SW1 on the back panel ...

Page 58: ...mation 1 3 The N1 SDP at a glance on page 1 14 2 Hardware description 2 11 LEDs switches and buttons 101489_0000_02_en Copyright 2019 2020 Arm Limited or its affiliates All rights reserved 2 58 Non Confidential Beta ...

Page 59: ...ctor on the back panel provides access to JTAG debug and to 32 bit trace See 1 3 The N1 SDP at a glance on page 1 14 for the location of the JTAG and trace connectors on the back panel Related information 1 3 The N1 SDP at a glance on page 1 14 2 Hardware description 2 12 Debug 101489_0000_02_en Copyright 2019 2020 Arm Limited or its affiliates All rights reserved 2 59 Non Confidential Beta ...

Page 60: ...onfiguration process on page 3 61 3 2 Powerup and powerdown sequences on page 3 62 3 3 Configuration files on page 3 64 3 4 Configuration switches on page 3 68 3 5 Use of reset push buttons on page 3 70 3 6 Command line interface on page 3 71 101489_0000_02_en Copyright 2019 2020 Arm Limited or its affiliates All rights reserved 3 60 Non Confidential Beta ...

Page 61: ...ing the power button on the PC case or the PBON button preliminary configuration takes place and the board enters the standby state The MCC command line interface is enabled in the standby state You can connect a workstation to the DBG USB port and edit configuration files or Drag and Drop new configuration files Configuration resumes after another press of the power button on the PC tower or the ...

Page 62: ... clocks 15 The MCC reads the FPGA image from the configuration microSD card and loads it into the IOFPGA 16 The MCC sets the board oscillator frequencies using values from the board txt file 17 The MCC releases the Serial Configuration Controller SCC reset nCFG_RESET 18 If necessary the MCC programs the IOFPGA and N1 SoC SCC registers as a backup procedure 19 The MCC programs the SCP and MCP QSPI ...

Page 63: ...ATXPSU 11 The system is now in the standby state and waits for a short press of the PBON button Related information 1 3 The N1 SDP at a glance on page 1 14 3 Configuration 3 2 Powerup and powerdown sequences 101489_0000_02_en Copyright 2019 2020 Arm Limited or its affiliates All rights reserved 3 63 Non Confidential Beta ...

Page 64: ...USBMSD and you can add edit or delete files You can use a standard text editor that produces DOS line endings to read and edit the board configuration files The following figure shows a typical example of the directory structure in the microSD card memory Caution Files names and directory names are in 8 3 format File names that you generate must be in lowercase Directory names must be in uppercase...

Page 65: ...HBI0316A TITLE N1SDP Configuration file CONFIGURATION TESTMENU FALSE AUTORUN TRUE Auto Run from power on AUTORUNDELAY 3 Delay in seconds to wait for key press to stop RTC TRUE TRUE Enable RTC FALSE Disable RTC APUART0 6 0 Not Used 1 USBPORT1 2 UART0 3 USBPORT2 4 UART1 5 PCC_UART5 6 USBPORT4 7 UART3 MCCUART 1 0 Not Used 1 USBPORT1 2 UART0 3 USBPORT2 4 UART1 PCCUART 1 0 Not Used 1 USBPORT2 2 UART1 3...

Page 66: ...P_AUTO Image Update NONE AUTO FORCE SCP_AUTO MCP_AUTO IMAGE1FILE SOFTWARE scp_fw bin Image for test IMAGE2ADDRESS 0x60000000 Please select the required executable program IMAGE2UPDATE FORCE Image Update NONE AUTO FORCE SCP_AUTO MCP_AUTO IMAGE2FILE SOFTWARE scp_rom bin Image for test IMAGE3ADDRESS 0x62000000 Please select the required executable program IMAGE3UPDATE FORCE Image Update NONE AUTO FOR...

Page 67: ...BOOT_CTL enable TLX SOCCON 0x1164 0x01000000 SoC SCC BOOT_CTL_STA 0xX1000000 MCC OK SOCCON 0x1168 0x00000000 SoC SCC SCP_BOOT_ADR SOCCON 0x116C 0x00000000 SoC SCC MCP_BOOT_ADR SOCCON 0x1170 0x00000000 SoC SCC PLATFORM_CTRL SOCCON 0x1174 0x00000000 SoC SCC TARGETIDAPP 0x07B00477 SOCCON 0x1178 0x00000000 SoC SCC TARGETIDSCP 0x07B10477 SOCCON 0x117C 0x00000000 SoC SCC TARGETIDMCP 0x07B20477 SOCCON 0x...

Page 68: ... and the flow control signals on UART0 to control the standby state This setting is typically used on test farms See the following for information about the configuration switches 1 3 The N1 SDP at a glance on page 1 14 1 4 Getting started on page 1 19 3 4 2 Remote UART configuration To enable remote UART control Switch SW1 on the side panel must be ON and the correct options must be set in the co...

Page 69: ... the host computer Alternatively you can use a custom terminal program such as VETerminal exe that Arm provides on the N1 SDP DVD This program integrates the terminal output and control buttons into a single application Related information 1 3 The N1 SDP at a glance on page 1 14 3 Configuration 3 4 Configuration switches 101489_0000_02_en Copyright 2019 2020 Arm Limited or its affiliates All right...

Page 70: ...equence In the operating state press the PBON button for longer than two seconds to initiate the powerdown sequence In the operating state press the PBRESET button to initiate a hardware reset See 3 2 Powerup and powerdown sequences on page 3 62 Related information 1 3 The N1 SDP at a glance on page 1 14 3 Configuration 3 5 Use of reset push buttons 101489_0000_02_en Copyright 2019 2020 Arm Limite...

Page 71: ... 14 3 6 2 MCC main command menu The following table shows the MCC main menu system commands Table 3 1 N1 SDP MCC main command menu Command Description CAP filename A Capture serial data to the file filename Use the A option to append data to an existing file COPY input_filename_1 input_filename_2 output_filename Copy a file input_filename_1 to output_filename Option input_filename_2 merges input_f...

Page 72: ...m memory address EXAM address nnnn Examine system memory address at address nnnn is number in Hex of words to read EXIT or QUIT Return to main menu HELP or Display this help TIME Display current time 3 6 4 EEPROM menu To switch to the EEPROM submenu enter EEPROM at the main menu The contents of the N1 SDP EEPROMs identify the specific board variant and might contain data to load to the other devic...

Page 73: ...rase image named image_id stored in Motherboard EEPROM ERASEIMAGES Erase images stored in Motherboard EEPROM HELP or Display this help READIMAGES Read images stored in Motherboard EEPROM READCF 0 Read configuration EEPROM READRANGE 0 start end Read EEPROM between start and end 3 Configuration 3 6 Command line interface 101489_0000_02_en Copyright 2019 2020 Arm Limited or its affiliates All rights ...

Page 74: ... 3 N1 SoC interrupt maps on page 4 95 4 4 System Security Control registers on page 4 105 4 5 Serial Configuration Control registers on page 4 119 4 6 APB system registers on page 4 197 4 7 APB energy meter registers on page 4 206 4 8 UART memory addresses and control registers on page 4 225 101489_0000_02_en Copyright 2019 2020 Arm Limited or its affiliates All rights reserved 4 74 Non Confidenti...

Page 75: ...d in the accompanying text Do not modify undefined register bits Ignore undefined register bits on reads All register bits are reset to a logic 0 by a system or powerup reset All register summary tables in this chapter describe register access types as follows RW Read write RO Read only WO Write only 4 Programmers model 4 1 About this programmers model 101489_0000_02_en Copyright 2019 2020 Arm Lim...

Page 76: ...ory map on page 4 76 4 2 2 Application Processor subsystem peripherals memory map on page 4 79 4 2 3 Manageability Control Processor memory map on page 4 83 4 2 4 Manageability Control Processor peripherals memory map on page 4 84 4 2 5 System Control Processor memory map on page 4 87 4 2 6 System Control Processor peripherals memory map on page 4 89 4 2 7 CoreSight system memory map on page 4 90 ...

Page 77: ...0_0000 0x49_0000_0000 PCIe ECAM configuration space PCIe slave AXI 0x00_7000_0000 CCIX MM032 memory space CCIX slave AXI 0x00_6920_0000 CCIX ECAM configuration space CCIX slave AXI 0x00_6800_0000 Reserved NIC 400 SoC GPV Reserved 0x00_6280_0000 0x00_6285_0000 0x00_6286_0000 0x00_6400_0000 0x00_6410_0000 0x00_6411_0000 GPIO Reserved 0x00_6900_0000 Reserved 0x00_6D20_0000 Reserved 0x00_7520_0000 PCI...

Page 78: ...5_FFFF 64KB PCIe msg APB 0x0_6200_0000 0x0_6200_0FFF 4KB CCIX root complex configuration space APB 0x0_6280_0000 0x0_6284_FFFF 320KB CCIX PHY APB 0x0_6285_0000 0x0_6285_FFFF 64KB CCIX msg APB 0x0_6400_0000 0x0_640F_FFFF 1MB NIC 400 N1 SoC GPV 0x0_6410_0000 0x0_6410_FFFF 64KB GPIO 0x0_6800_0000 0x0_68FF_FFFF 16MB CCIX ECAM configuration space CCIX slave AXI 0x0_6920_0000 0x0_6D1F_FFFF 64MB CCIX MMO...

Page 79: ... 3TB DRAM2 4 2 2 Application Processor subsystem peripherals memory map The Application Processor AP memory map of the N1 SDP contains a region associated with the subsystem peripherals The following figure shows the subsystem peripherals region of the AP memory map 4 Programmers model 4 2 N1 SDP memory maps 101489_0000_02_en Copyright 2019 2020 Arm Limited or its affiliates All rights reserved 4 ...

Page 80: ...000 0x00_4445_0000 0x00_4520_0000 0x00_4522_0000 0x00_4540_0000 0x00_4542_0000 0x00_4700_0000 0x00_4701_0000 0x00_4702_0000 0x00_4C40_0000 0x00_4C41_0000 0x00_4C42_0000 0x00_4C43_0000 0x00_4D00_0000 0x00_4E00_0000 0x00_4F00_0000 Application Processor subsystem peripherals memory map SCP MHU1 0x00_4500_0000 Reserved 0x00_4502_0000 Reserved 0x00_2E00_0000 Always secure Secure and Non Secure Key SCP ...

Page 81: ...FFF 64KB AP_REFCLK_S CNTBase1 0x00_2A83_0000 0x00_2A83_FFFF 64KB AP_REFCLK_NS CNTBase0 0x00_2B00_0000 0x00_2B0F_FFFF 1MB Reserved for SCP MCP to access whole of application space 0x00_2C00_0000 0x00_2C00_1FFF 8KB GICC registers 0x00_2C01_0000 0x00_2C01_0FFF 4KB GICH registers 0x00_2C02_0000 0x00_2C02_1FFF 8KB GICV registers 0x00_2E08_0000 0x00_2FFF_FFFF 32256KB Reserved for GIC 0x00_3000_0000 0x00...

Page 82: ... MHU 0x00_4C41_0000 0x00_4C41_FFFF 64KB AP2MCP MHU Non Secure RAM 0x00_4C42_0000 0x00_4C42_FFFF 64KB AP2MCP MHU Secure RAM 0x00_4D00_0000 0x00_4DFF_FFFF 16MB Base STM 0x00_4E00_0000 0x00_4EFF_FFFF 16MB Memory Element 0x00_4F00_0000 0x00_4F03_FFFF 256KB Translation Control Unit0 TCU0 for CCIX root port 0x00_4F04_0000 0x00_4F05_FFFF 128KB Translation Buffer Unit0 TBU0 for CCIX root port 0x00_4F06_00...

Page 83: ...0000 0x0_3400_0000 0x0_3400_1000 0x0_3FFF_E000 0x0_3FFF_F000 0x0_0100_0000 MCP SoC expansion MCP SoC expansion 0x0_4400_0000 0x0_4800_0000 MCP SoC expansion 0x0_4C00_0000 0x0_4E00_0000 0x0_5000_0000 0x0_5080_0000 Reserved 0x0_6000_0000 0x0_6000_0000 0x0_A000_0000 System Access Port 0x0_E000_0000 Private peripheral bus Internal Private peripheral bus External 0x0_E004_0000 0x0_E010_0000 Reserved 0x...

Page 84: ..._0000 0x0_4BFF_FFFF 64MB MCP SoC expansion 0x0_4C00_0000 0x0_4DFF_FFFF 32MB MCP peripherals 0x0_4E00_0000 0x0_4FFF_FFFF 32MB Reserved 0x0_5000_0000 0x0_507F_FFFF 8MB Element management peripherals 0x0_5080_0000 0x0_5FFF_FFFF 248MB Reserved 0x0_6000_0000 0x0_9FFF_FFFF 1GB System Access Port Translated to 0x0_4000_0000 to 0x0_7FFF_FFFF of AP memory map 0x0_A000_0000 0x0_DFFF_FFFF 1GB System Access P...

Page 85: ...0x0_4C00_1000 0x0_4C00_2000 0x0_4C00_3000 0x0_4C00_4000 0x0_4C00_6000 Reserved 0x0_4C00_7000 AP2MCP MHU 0x0_4C40_0000 AP2MCP MHU Non secure RAM 0x0_4C41_0000 AP2MCP MHU Secure RAM 0x0_4C42_0000 Reserved 0x0_4C43_0000 MCP peripherals memory map SCP2 MCP MHU SCP2MCP MHU Secure RAM SCP2MCP MHU Non secure RAM 0x0_4560_0000 0x0_4561_0000 0x0_4562_2000 MCP peripherals memory map MCP peripherals memory m...

Page 86: ...00_2000 0x00_4C00_2FFF 4KB MCPUART0 0x00_4C00_3000 0x00_4C00_3FFF 4KB MCPUART1 0x00_4C00_6000 0x00_4C00_6FFF 4KB Watchdog SP805 0x00_4C40_0000 0x00_4C40_FFFF 64KB AP2 MCP MHU 0x00_4C41_0000 0x00_4C41_FFFF 64KB AP2 MCP MHU Non secure RAM 0x00_4C42_0000 0x00_4C42_FFFF 64KB AP2 MCP MHU Secure RAM 4 Programmers model 4 2 N1 SDP memory maps 101489_0000_02_en Copyright 2019 2020 Arm Limited or its affil...

Page 87: ...Port 0x0_E000_0000 Private peripheral bus Internal Private peripheral bus External 0x0_E004_0000 0x0_E010_0000 Reserved 0x01_0000_0000 0x0_0100_0000 SCP PVT CTRL Reserved 0x0_3FFF_A000 SCP I2C1 PMIC 0x0_3FFF_B000 SCP I2C 2 SPD PCC 0x0_3FFF_C000 Reserved 0x0_3FFF_D000 0x0_3FFF_F000 Memory element 0 configuration Memory element 0 manager Reserved Memory element 1 configuration Memory element 1 manag...

Page 88: ..._43FF_FFFF 64MB SCP SoC expansion 0x0_4400_0000 0x0_45FF_FFFF 32MB SCP peripherals 0x0_4600_0000 0x0_47FF_FFFF 32MB Reserved 0x0_4800_0000 0x0_4BFF_FFFF 64MB MCP SoC expansion 0x0_4C00_0000 0x0_4DFF_FFFF 32MB Reserved 0x0_4E00_0000 0x0_4E00_FFFF 64KB Memory element 0 configuration 0x0_4E01_0000 0x0_4E01_FFFF 64KB Memory element 0 manager 0x0_4E10_0000 0x0_4E10_FFFF 64KB Memory element 1 configurat...

Page 89: ..._7000 0x0_0100_0000 SCP SoC expansion SCP SoC expansion 0x0_4400_0000 0x0_4800_0000 MCP SoC expansion 0x0_4C00_0000 0x0_4E00_0000 0x0_5000_0000 0x0_5080_0000 Reserved 0x0_6000_0000 0x0_A000_0000 System Access Port 0x0_E000_0000 Private peripheral bus Internal Private peripheral bus External 0x0_E004_0000 0x0_E010_0000 Reserved 0x01_0000_0000 Watchdog Reserved 0x0_4400_A000 Reserved 0x0_4400_B000 R...

Page 90: ..._0000 0x00_4C12_FFFF 64KB Cluster 1 time frame 0x00_4500_0000 0x00_4501_FFFF 128KB AP2SCP Message Handling Unit MHU 0x00_452C_0000 0x00_452D_FFFF 128KB AP2SCP MHU Non secure RAM 0x00_4540_0000 0x00_4541_FFFF 128KB AP2SCP MHU Secure RAM 0x00_4560_0000 0x00_4560_FFFF 64KB SCP2MCH MHU 0x00_4561_0000 0x00_4561_FFFF 64KB SCP2MCP MHU Non secure RAM 0x00_4562_0000 0x00_4562_FFFF 64KB SCP2MCP MHU Secure R...

Page 91: ...00 0x04_020E_0000 Reserved 0x04_0000_0000 Reserved Reserved 0x04_0001_1000 0x04_0041_0000 EXP ROM 0x04_0100_0000 0x04_020C_0000 CLUS0 ELA CLUS0 CLUS ELA 0x04_020D_0000 Reserved 0x04_020F_0000 CoreSight system memory map Reserved 0x04_0203_0000 Figure 4 7 CoreSight system memory map The following table shows the peripherals region of the N1 SDP CoreSight debug and trace memory map Undefined locatio...

Page 92: ...04_0100_5000 0x04_0100_5FFF 4KB CCIX PHY PIPE ELA 0x04_0100_6000 0x04_0100_6FFF 4KB CCIX PCIE PIPE ELA 0x04_0100_7000 0x04_0100_7FFF 4KB EXP CTI2 0x04_0202_0000 0x04_0202_FFFF 64KB CLUS0 CTI 0x04_020C_0000 0x04_020C_FFFF 64KB CLUS0 ELA 0x04_020D_0000 0x04_020D_FFFF 64KB CLUS0 CLUS ELA 0x04_020E_0000 0x04_020E_FFFF 64KB CLUS0 CLUS CTI 4 Programmers model 4 2 N1 SDP memory maps 101489_0000_02_en Cop...

Page 93: ...3_0000 0x00_1C05_0000 0x00_1C06_0000 0x00_1C07_0000 0x00_1C08_0000 0x00_1C09_0000 0x00_1C0A_0000 0x00_1C0B_0000 0x00_1C0C_0000 0x00_1C0D_0000 FPGAUART1 0x00_1C0E_0000 0x00_1C0F_0000 0x00_1C10_0000 0x00_1800_0000 0x00_1C01_0000 0x00_1C04_0000 GPIO 1 SCC 0x00_1C11_0000 0x00_1C12_0000 0x00_1C13_0000 0x00_1C14_0000 0x00_1C15_0000 0x00_1CA0_0000 0x00_1CA1_0000 0x00_1D00_0000 0x00_1D10_0000 0x00_1D20_00...

Page 94: ...0x1C0B_0000 0x1C0B_FFFF 64KB Watchdog 0x1C0C_0000 0x1C0C_FFFF 64KB QSPI SPI configuration 0x1C0D_0000 0x1C0D_FFFF 64KB Dual Timer 0 1 0x1C0E_0000 0x1C0E_FFFF 64KB Dual Timer 2 3 0x1C0F_0000 0x1C0F_FFFF 64KB DVI I2C 0x1C10_0000 0x1C10_FFFF 64KB Real Time Clock 0x1C11_0000 0x1C11_FFFF 64KB GPIO 0 0x1C12_0000 0x1C12_FFFF 64KB GPIO 1 0x1C13_0000 0x1C13_FFFF 64KB SCC 0x1C14_0000 0x1C14_FFFF 64KB SMC co...

Page 95: ...est 22 COMMIRQn Debug Communications Channel receive or transmit request 23 PMUIRQn PMU interrupt 24 CTIIRQ CTI Interrupt 25 VCPUMNTIRQn Virtual Maintenance Interrupt PPI6 26 CNTHPIRQn Non secure PL2 Timer event PPI5 27 CNTVIRQn Virtual Timer event PPI4 28 CNTHVIRQn 29 CNTPSIRQn Secure PL1 Physical Timer event PPI1 30 CNTPNSIRQn Non secure PL1 Physical Timer event PPI2 31 Reserved The following ta...

Page 96: ...ecure 92 AP_REFCLK Generic Timer Non secure AP_REFCLK Generic Timer Interrupt Non secure 93 Generic Watchdog Watchdog WS0 Interrupt 94 Generic Watchdog Watchdog WS1 Interrupt 95 AP_UART0 AP UART0 interrupt 96 AP_UART1 AP UART1 interrupt 127 97 Reserved 128 N1 board AP external IRQ AP_EXT_INT 129 N1 board AP external Ethernet IRQ AP_EXT_ETHERNET_INT 167 130 Reserved 168 N1 SoC GPIO combined IRQ 176...

Page 97: ...peed_change 243 N1 SoC ccix_link_training_done 244 N1 SoC ccix_pll_status_rise 245 N1 SoC ccix_message_fifo_interrupt 246 N1 SoC ccix_local_interrupt_ras 247 N1 SoC ccix_hot_reset_irq 248 N1 SoC ccix_flr_reset_irq 249 N1 SoC ccix_power_state_change_irq 255 250 Reserved 256 MMUTCU1_PMU_IRPT PMU interrupt 257 MMUTCU1_EVENT_Q_IRPT_S Event Queue Secure interrupt indicating Event Queue Non Empty or Ove...

Page 98: ...secure 515 CLUSTER1SCP AP MHU secure 575 516 Reserved 576 P0_REFCLK_GENTIM Pn_REFCLK Generic Secure Timer interrupts 577 P0_REFCLK_GENTIM Pn_REFCLK Generic Secure Timer interrupts 640 578 Reserved 4 3 2 System Control Processor interrupt map The System Control Processor SCP receives interrupts from several sources The sources of the interrupts to the SCP are Application Processor system wakeup int...

Page 99: ... Time stamp synchronization interrupt 36 Reserved 37 CTI CTI Trigger 0 38 CTI CTI Trigger 1 39 GICECCFATAL GIC Fatal ECC failure 40 GICAXIMERR GIC Fatal AXI Master error 41 Reserved 42 AON_UART_INT Always on UART interrupt 43 Reserved 44 Generic Watchdog Generic Watchdog timer interrupt WS0 45 Generic Watchdog Generic Watchdog timer interrupt WS1 46 Trusted Watchdog Trusted Watchdog timer interrup...

Page 100: ...MU_TCU_RASIRPT Consolidated MMU RAS for the interrupt coming from multiple TCUs 95 CONS_MMU_TBU_RASIRPT NUM_TBUS 1 0 Consolidated TBU for the interrupts coming from various TBUs 96 INTREQPPU PPU interrupt from CMN 600 97 INTREQERRNS Non Secure error handling interrupt from CMN 600 98 INTREQERRS Secure error handling interrupt from CMN 600 99 INTREQFAULTS Secure Fault handling interrupt from CMN 60...

Page 101: ...209 SCP PMIC I2C SCP PMIC I2C interrupt I2C1 210 SCP SPD PCC I2C SCP SPD PCC I2C interrupt I2C2 211 SCP QSPI SCP QSPI interrupt 212 PVT controller PVT controller interrupt 218 213 Reserved 219 ccix_bus_device_change_irq ccix_bus_device_change_irq 220 ccix_inta_out ccix_inta_out 221 ccix_intb_out ccix_intb_out 222 ccix_intc_out ccix_intc_out 223 ccix_intd_out ccix_intd_out 224 ccix_phy_interrupt_ou...

Page 102: ...sor system wakeup interrupts CoreSight power and reset request interrupts Internal MCP subsystem interrupts Expansion MCP interrupts The interrupts are routed to the Nested Vector Interrupt Controllers in Cortex M7 processors where they can be managed by software The following table shows the MCP interrupts Table 4 12 MCP interrupts ID Source Description NMI MCP Generic Watchdog MCP Watchdog WS0 0...

Page 103: ...le TCUs 95 MMU_TBU_RASIRPT NUM_TBUS 1 0 Consolidated TBU for the interrupts coming from multiple TBUs 96 INTREQPPU PPU interrupt from CMN 600 97 INTREQERRNS Non secure error handling interrupt from CMN 600 98 INTREQERRS Secure error handling interrupt from CMN 600 99 INTREQFAULTS Secure Fault handling interrupt from CMN 600 100 INTREQFAULTNS Non secure Fault handling interrupt from CMN 600 101 INT...

Page 104: ...P QSPI interrupt 219 211 Reserved 220 pcie_aer_interrupt pcie_aer_interrupt 221 pcie_local_interrupt_reset pcie_local_interrupt_reset 222 pcie_local_interrupt_ras pcie_local_interrupt_ras 223 ccix_aer_interrupt ccix_aer_interrupt 224 ccix_local_interrupt_reset ccix_phy_interrupt_out 225 ccix_local_interrupt_ras ccix_aer_interrupt 239 226 ccix_link_down_reset_out ccix_link_down_reset_out 4 Programm...

Page 105: ... page 4 115 4 4 14 SSC_PID1 Register on page 4 115 4 4 15 SSC_PID2 Register on page 4 116 4 4 16 SSC_COMPID0 Register on page 4 116 4 4 17 SSC_COMPID1 Register on page 4 117 4 4 18 SSC_COMPID2 Register on page 4 117 4 4 19 SSC_COMPID3 Register on page 4 118 4 4 1 System Security Control registers summary The base memory address of the SSC registers is 0x0_2A42_0000 in the subystem peripherals regi...

Page 106: ...trol registers See 4 4 10 SSC_SW_CAPCTRL Register on page 4 113 0x0500 SSC_CHIPID_ST RO 0x0000_0000 32 CHIPID status register See 4 4 11 SSC_CHIPID_ST Register on page 4 113 0x0FD0 SSC_PID4 RO 0x0000_0004 32 Peripheral ID4 register See 4 4 12 SSC_PID4 Register on page 4 114 0x0FE0 SSC_PID0 RO 0x0000_0044 32 Peripheral ID0 register See 4 4 13 SSC_PID0 Register on page 4 115 0x0FE4 SSC_PID1 RO 0x000...

Page 107: ...be internally driven Usage constraints This register is read only Configurations Available in all N1 board configurations Memory offset and full register reset value See 4 4 1 System Security Control registers summary on page 4 105 The following table shows the SSC_DBGCFG_STAT Register bit assignments Table 4 14 SSC_DBGCFG_STAT Register bit assignments Bits Name Type Function 31 8 Reserved 7 SPIDE...

Page 108: ... 4 4 3 SSC_DBGCFG _SET Register The SSC_DBGCFG _SET Register characteristics are Purpose The SSC_DBGCFG _SET register is a Secure access only write only memory mapped register This register is associated with the SSC_DBGCFG _STAT register Writing 0b1 to a particular field in the SSC_DBGCFG _SET register sets the corresponding bit in the SSC_DBGCFG _STAT register to 0b1 Usage constraints This regis...

Page 109: ..._STAT to 0b1 1 0 Reserved 4 4 4 SSC_DBGCFG _CLR Register The SSC_DBGCFG _CLR Register characteristics are Purpose The SSC_DBGCFG _CLR register is a Secure access only write only memory mapped register This register is associated with the SSC_DBGCFG _STAT register Writing0b1 to a particular field in the SSC_DBGCFG _CLR register clears the corresponding bit in the SSC_DBGCFG _STAT register to 0b0 Us...

Page 110: ...EN_SEL_STAT to 0b0 2 DEVICEEN_INT_CLR RO Clears DEVICEEN_INT_STAT to 0b0 0b0 No effect 0b1 Clear DEVICEEN_INT_STAT to 0b0 1 0 Reserved 4 4 5 SSC_AUXDBGCFG Register The SSC_AUXDBGCFG Register characteristics are Purpose The SSC_AUXDBGCFG register is a Secure access only read write register The register provides override control of the debug authentication signals DBGEN and NIDEN Usage constraints T...

Page 111: ...at their reset value 4 4 6 SSC_GPRETN Register The SSC_GPRETN Register characteristics are Purpose The SSC_GPRETN register is a secure access read write memory mapped register that provides 16 bit general storage for security purposes The register resets only on system powerup reset Usage constraints There are no usage constraints Configurations Available in all N1 board configurations Memory offs...

Page 112: ...D RO Equals Arm identifier 0x41 on N1 SoC 11 0 PART_NUMBER RO Equals Arm identifier 0x7B0 on N1 SoC 4 4 8 SSC_SW_SCRATCH Registers The SSC_SW_SCRATCH Register characteristics are Purpose The SSC_SW_SCRATCH registers are scratch registers for use by software Usage constraints There are no usage constraints Configurations Available in all N1 board configurations Memory offset and full register reset...

Page 113: ...it to enable writing to the SSC_SW_CAP registers Usage constraints Once set the active bit bit 0 cannot be cleared until SoC_nPOR is asserted Configurations Available in all N1 board configurations Memory offset and full register reset value See 4 4 1 System Security Control registers summary on page 4 105 The following table shows the SSC_SW_CAPCTRL Register bit assignments Table 4 22 SSC_SW_CAPC...

Page 114: ...0 Single chip 0b1 Multi chip Reset value 0b0 7 6 Reserved 5 0 CHIP_ID RO Tie off value in multi chip mode This is 0b0 for single chip mode Reset value 0b000000 4 4 12 SSC_PID4 Register The SSC_PID4 Register characteristics are Purpose Stores peripheral identification information Usage constraints This register is read only Configurations Available in all N1 board configurations Memory offset and f...

Page 115: ...e 4 105 The following table shows the SSC_PID0 Register bit assignments Table 4 25 SSC_PID0 Register bit assignments Bits Name Type Function 31 8 Reserved 7 0 PART_0 RO Bits 7 0 of part number Reset value 0x44 4 4 14 SSC_PID1 Register The SSC_PID1 Register characteristics are Purpose Stores peripheral identification information Usage constraints This register is read only Configurations Available ...

Page 116: ...n page 4 105 The following table shows the SSC_PID2 Register bit assignments Table 4 27 SSC_PID2 Register bit assignments Bits Name Type Function 31 8 Reserved 7 4 REVISION RO Revision number Reset value 0x0 3 JEDEC RO JEDEC ID Reset value 0b1 2 0 DES_1 RO Designer ID Reset value 0b011 4 4 16 SSC_COMPID0 Register The SSC_COMPID0 Register characteristics are Purpose The SSC_COMPID0 register stores ...

Page 117: ...rol registers summary on page 4 105 The following table shows the SSC_COMPID1 Register bit assignments Table 4 29 SSC_COMPID1 Register bit assignments Bits Name Type Function 31 8 Reserved 7 0 SSC_COMPID1 RO Component ID 1 information Reset value 0xF0 4 4 18 SSC_COMPID2 Register The SSC_COMPID2 Register characteristics are Purpose The SSC_COMPID2 register stores component identification informatio...

Page 118: ...gurations Available in all N1 board configurations Memory offset and full register reset value See 4 4 1 System Security Control registers summary on page 4 105 The following table shows the SSC_COMPID3 Register bit assignments Table 4 31 SSC_COMPID3 Register bit assignments Bits Name Type Function 31 8 Reserved 7 0 SSC_COMPID3 RO Component ID 3 information Reset value 0xB1 4 Programmers model 4 4...

Page 119: ...LK_CTRL Register on page 4 139 4 5 22 MCPQSPICLK_DIV Register on page 4 140 4 5 23 PCIEAXICLK_CTRL Register on page 4 140 4 5 24 PCIEAXICLK_DIV Register on page 4 141 4 5 25 CCIXAXICLK_CTRL Register on page 4 142 4 5 26 CCIXAXICLK_DIV Register on page 4 143 4 5 27 PCIEAPBCLK_CTRL Register on page 4 143 4 5 28 PCIEAPBCLK_DIV Register on page 4 144 4 5 29 CCIXAPBCLK_CTRL Register on page 4 145 4 5 3...

Page 120: ... 180 4 5 76 STM_CTRL Register on page 4 181 4 5 77 AXI_OVRD_PCIE Register on page 4 182 4 5 78 AXI_OVRD_CCIX Register on page 4 183 4 5 79 AXI_OVRD_TSIF Register on page 4 184 4 5 80 TRACE_PAD_CTRL0 Register on page 4 184 4 5 81 TRACE_PAD_CTRL1 Register on page 4 187 4 5 82 IOFPGA_TMIF_PAD_CTRL Register on page 4 188 4 5 83 IOFPGA_TSIF_PAD_CTRL Register on page 4 189 4 5 84 APB_CTRL_CLR Register o...

Page 121: ...0x000F_000F 32 See 4 5 12 SCPI2CCLK_DIV Register on page 4 132 0x0048 SCPQSPICLK_CTRL RW RO 0x0000_0101 32 See 4 5 13 SCPQSPICLK_CTRL Register on page 4 133 0x004C SCPQSPICLK_DIV RW RO 0x0000_0000 32 See 4 5 14 SCPQSPICLK_DIV Register on page 4 134 0x0054 SENSORCLK_CTRL RW RO 0x0000_0101 32 See 4 5 15 SENSORCLK_CTRL Register on page 4 134 0x0058 SENSORCLK_DIV RW RO 0x0017_0017 32 See 4 5 16 SENSOR...

Page 122: ... Register on page 4 150 0x010C CPU1_PLL_CTRL1 RW RO 0x9100_0000 32 See 4 5 35 CPU1_PLL_CTRL1 Register on page 4 151 0x0110 CLUS_PLL_CTRL0 RW 0x8010_2000 32 See 4 5 36 CLUS_PLL_CTRL0 Register on page 4 152 0x0114 CLUS_PLL_CTRL1 RW RO 0x9100_0000 32 See 4 5 37 CLUS_PLL_CTRL1 Register on page 4 153 0x0118 SYS_PLL_CTRL0 RW 0x8010_3000 32 See 4 5 38 SYS_PLL_CTRL0 Register on page 4 154 0x011C SYS_PLL_C...

Page 123: ... 0x0198 BOOT_GPR6 RW RO 0x0000_0000 32 See 4 5 59 BOOT_GPR6 Register on page 4 169 0x019C BOOT_GPR7 RW RO 0x0000_0000 32 See 4 5 60 BOOT_GPR7 Register on page 4 169 0x01A0 INSTANCE_ID RW RO 0x0000_0000 32 See 4 5 61 INSTANCE_ID Register on page 4 170 0x01A4 PCIE_BOOT_CTRL RW 0x0000_0003 32 See 4 5 62 PCIE_BOOT_CTRL Register on page 4 170 0x01B4 DBG_AUTHN_CTRL RW 0x0000_0007 32 See 4 5 63 DBG_AUTHN...

Page 124: ...0x0011_1111 32 See 4 5 82 IOFPGA_TMIF_PAD_CTRL Register on page 4 188 0x020C IOFPGA_TSIF_PAD_CTRL RW 0x0011_1111 32 See 4 5 83 IOFPGA_TSIF_PAD_CTRL Register on page 4 189 0x0E00 APB_CTRL_CLR RW 0xXXXX_XXXX 32 See 4 5 84 APB_CTRL_CLR Register on page 4 191 0x0FD0 PID4 RO 0x0000_0004 32 See 4 5 85 PID4 Register on page 4 191 0xFE0 PID0 RO 0x0000_00AF 32 See 4 5 86 PID0 Register on page 4 192 0xFE4 P...

Page 125: ...ion value 2 Note The example values in this register and the clock frequency they generate are part of a clock configuration which enables correct operation of the N1 SoC Further SoC testing and measurement by Arm or by other developers might result in new register values 4 5 3 SYSAPBCLK_CTRL Register The SYSAPBCLK_CTRL Register characteristics are Purpose Selects source for clock SYSAPBCLK Usage ...

Page 126: ... might result in new register values 4 5 4 SYSAPBCLK _DIV Register The SYSAPBCLK _DIV Register characteristics are Purpose Controls the SYSAPBCLK division value from SYSPLLCLK Usage constraints Bits 20 16 are read only Bits 4 0 are read write Configurations Available in all N1 board configurations Memory offset and full register reset value See 4 5 1 Serial Configuration Control registers summary ...

Page 127: ...ts Bits 11 8 are read only Bits 3 0 are read write Configurations Available in all N1 board configurations Memory offset and full register reset value See 4 5 1 Serial Configuration Control registers summary on page 4 120 The following table shows the IOFPGA_TMIF2XCLK_CTRL Register bit assignments Table 4 36 IOFPGA_TMIF2XCLK_CTRL Register bit assignments Bits Name Type Function 31 12 Reserved 11 8...

Page 128: ...V Register bit assignments Bits Name Type Function 31 21 Reserved 20 16 CLKDIV_CUR RO Current clock divider value Division value CLKDIV_CUR 1 15 5 Reserved 4 0 CLKDIV RW Sets clock division value Division value CLKDIV_CUR 1 Reset value 0b10011 division value 20 Note The example values in this register and the clock frequency they generate are part of a clock configuration which enables correct ope...

Page 129: ...testing and measurement by Arm or by other developers might result in new register values 4 5 8 IOFPGA_TSIF2XCLK_DIV Register The IOFPGA_TSIF2XCLK_DIV Register characteristics are Purpose Controls the TSIF2XCLK division value from SYSPLLCLK Usage constraints Bits 20 16 are read only Bits 4 0 are read write Configurations Available in all N1 board configurations Memory offset and full register rese...

Page 130: ...aints Bits 11 8 are read only Bits 3 0 are read write Configurations Available in all N1 board configurations Memory offset and full register reset value See 4 5 1 Serial Configuration Control registers summary on page 4 120 The following table shows the SCPNICCLK_CTRL Register bit assignments Table 4 40 SCPNICCLK_CTRL Register bit assignments Bits Name Type Function 31 12 Reserved 11 8 CLKSEL_CUR...

Page 131: ...ter bit assignments Bits Name Type Function 31 21 Reserved 20 16 CLKDIV_CUR RO Current clock divider value Division value CLKDIV_CUR 1 15 5 Reserved 4 0 CLKDIV RW Sets clock division value Division value CLKDIV_CUR 1 Reset value 0b00111 division value 8 Note The example values in this register and the clock frequency they generate are part of a clock configuration which enables correct operation o...

Page 132: ...r SoC testing and measurement by Arm or by other developers might result in new register values 4 5 12 SCPI2CCLK_DIV Register The SCPI2CCLK_DIV Register characteristics are Purpose Controls the SCPI2CCLK division value from SYSPLLCLK Usage constraints Bits 20 16 are read only Bits 4 0 are read write Configurations Available in all N1 board configurations Memory offset and full register reset value...

Page 133: ...s Bits 11 8 are read only Bits 3 0 are read write Configurations Available in all N1 board configurations Memory offset and full register reset value See 4 5 1 Serial Configuration Control registers summary on page 4 120 The following table shows the SCPQSPICLK_CTRL Register bit assignments Table 4 44 SCPQSPICLK_CTRL Register bit assignments Bits Name Type Function 31 12 Reserved 11 8 CLKSEL_CUR R...

Page 134: ...gister bit assignments Bits Name Type Function 31 21 Reserved 20 16 CLKDIV_CUR RO Current clock divider value Division value CLKDIV_CUR 1 15 5 Reserved 4 0 CLKDIV RW Sets clock division value Division value CLKDIV_CUR 1 Reset value 0b00000 division value 1 Note The example values in this register and the clock frequency they generate are part of a clock configuration which enables correct operatio...

Page 135: ...r SoC testing and measurement by Arm or by other developers might result in new register values 4 5 16 SENSORCLK_DIV Register The SENSORCLK_DIV Register characteristics are Purpose Controls the SENSORCLK division value from SYSPLLCLK Usage constraints Bits 20 16 are read only Bits 4 0 are read write Configurations Available in all N1 board configurations Memory offset and full register reset value...

Page 136: ...ts Bits 11 8 are read only Bits 3 0 are read write Configurations Available in all N1 board configurations Memory offset and full register reset value See 4 5 1 Serial Configuration Control registers summary on page 4 120 The following table shows the MCPNICCLK_CTRL Register bit assignments Table 4 48 MCPNICCLK_CTRL Register bit assignments Bits Name Type Function 31 12 Reserved 11 8 CLKSEL_CUR RO...

Page 137: ...ter bit assignments Bits Name Type Function 31 21 Reserved 20 16 CLKDIV_CUR RO Current clock divider value Division value CLKDIV_CUR 1 15 5 Reserved 4 0 CLKDIV RW Sets clock division value Division value CLKDIV_CUR 1 Reset value 0b00111 division value 8 Note The example values in this register and the clock frequency they generate are part of a clock configuration which enables correct operation o...

Page 138: ...r SoC testing and measurement by Arm or by other developers might result in new register values 4 5 20 MCPI2CCLK_DIV Register The MCPI2CCLK_DIV Register characteristics are Purpose Controls the MCPI2CCLK division value from SYSPLLCLK Usage constraints Bits 20 16 are read only Bits 4 0 are read write Configurations Available in all N1 board configurations Memory offset and full register reset value...

Page 139: ...s Bits 11 8 are read only Bits 3 0 are read write Configurations Available in all N1 board configurations Memory offset and full register reset value See 4 5 1 Serial Configuration Control registers summary on page 4 120 The following table shows the MCPQSPICLK_CTRL Register bit assignments Table 4 52 MCPQSPICLK_CTRL Register bit assignments Bits Name Type Function 31 12 Reserved 11 8 CLKSEL_CUR R...

Page 140: ...ster bit assignments Bits Name Type Function 31 21 Reserved 20 16 CLKDIV_CUR RO Current clock divider value Division value CLKDIV_CUR 1 15 5 Reserved 4 0 CLKDIV RW Sets clock division value Division value CLKDIV_CUR 1 Reset value 0b00000 division value 1 Note The example values in this register and the clock frequency they generate are part of a clock configuration which enables correct operation ...

Page 141: ...r SoC testing and measurement by Arm or by other developers might result in new register values 4 5 24 PCIEAXICLK_DIV Register The PCIEAXICLK_DIV Register characteristics are Purpose Controls the PCIEAXICLK division value from SYSPLLCLK Usage constraints Bits 20 16 are read only Bits 4 0 are read write Configurations Available in all N1 board configurations Memory offset and full register reset va...

Page 142: ...ts Bits 11 8 are read only Bits 3 0 are read write Configurations Available in all N1 board configurations Memory offset and full register reset value See 4 5 1 Serial Configuration Control registers summary on page 4 120 The following table shows the CCIXAXICLK_CTRL Register bit assignments Table 4 56 CCIXAXICLK_CTRL Register bit assignments Bits Name Type Function 31 12 Reserved 11 8 CLKSEL_CUR ...

Page 143: ...ster bit assignments Bits Name Type Function 31 21 Reserved 20 16 CLKDIV_CUR RO Current clock divider value Division value CLKDIV_CUR 1 15 5 Reserved 4 0 CLKDIV RW Sets clock division value Division value CLKDIV_CUR 1 Reset value 0b00001 division value 2 Note The example values in this register and the clock frequency they generate are part of a clock configuration which enables correct operation ...

Page 144: ...r SoC testing and measurement by Arm or by other developers might result in new register values 4 5 28 PCIEAPBCLK_DIV Register The PCIEAPBCLK_DIV Register characteristics are Purpose Controls the PCIEAPBCLK division value from SYSPLLCLK Usage constraints Bits 20 16 are read only Bits 4 0 are read write Configurations Available in all N1 board configurations Memory offset and full register reset va...

Page 145: ...ts Bits 11 8 are read only Bits 3 0 are read write Configurations Available in all N1 board configurations Memory offset and full register reset value See 4 5 1 Serial Configuration Control registers summary on page 4 120 The following table shows the CCIXAPBCLK_CTRL Register bit assignments Table 4 60 CCIXAPBCLK_CTRL Register bit assignments Bits Name Type Function 31 12 Reserved 11 8 CLKSEL_CUR ...

Page 146: ...IV Register bit assignments Bits Name Type Function 31 21 Reserved 20 16 CLKDIV_CUR RO Current clock divider value Division value CLKDIV_CUR 1 15 5 Reserved 4 0 CLKDIV RW Sets clock division value Division value CLKDIV_CUR 1 Reset value 0b01011 division value 12 Note The example values in this register and the clock frequency they generate are part of a clock configuration which enables correct op...

Page 147: ... 0b1 11 PCIEAPBCLKEN RW Enable clock PCIEAPBCLK 0b0 Clock disabled 0b1 Clock enabled Reset value 0b1 10 PCIEAXICLKEN RW Enable clock PCIEAXICLK 0b0 Clock disabled 0b1 Clock enabled Reset value 0b1 9 MCPQSPICLKEN RW Enable clock MCPQSPICLK 0b0 Clock disabled 0b1 Clock enabled Reset value 0b1 8 MCPI2CCLKEN RW Enable clock MCPI2CCLK 0b0 Clock disabled 0b1 Clock enabled Reset value 0b1 7 MCPNICCLKEN R...

Page 148: ...value 0b1 1 IOFPGA_TMIF2XCLKEN RW Enable clock TMIF2XCLK 0b0 Clock disabled 0b1 Clock enabled Reset value 0b1 0 SYSAPBCLKEN RW Enable clock SYSAPBCLK 0b0 Clock disabled 0b1 Clock enabled Reset value 0b1 4 5 32 CPU0_PLL_CTRL0 Register The CPU0_PLL_CTRL0 Register characteristics are Purpose This register and register CPU0_PLL_CTRL1 control the settings of clock control PLL CPU0PLL Usage constraints ...

Page 149: ...ed 0x1 PLL bypassed Reset value 0b0 Note The example values in this register and the clock frequency they generate are part of a clock configuration which enables correct operation of the N1 SoC Further SoC testing and measurement by Arm or by other developers might result in new register values 4 5 33 CPU0_PLL_CTRL1 Register The CPU0_PLL_CTRL1 Register characteristics are Purpose This register an...

Page 150: ...guration which enables correct operation of the N1 SoC Further SoC testing and measurement by Arm or by other developers might result in new register values 4 5 34 CPU1_PLL_CTRL0 Register The CPU1_PLL_CTRL0 Register characteristics are Purpose This register and register CPU1_PLL_CTRL1 control the settings of clock control PLL CPU1PLL Usage constraints There are no usage constraints Configurations ...

Page 151: ...s in this register and the clock frequency they generate are part of a clock configuration which enables correct operation of the N1 SoC Further SoC testing and measurement by Arm or by other developers might result in new register values 4 5 35 CPU1_PLL_CTRL1 Register The CPU1_PLL_CTRL1 Register characteristics are Purpose This register and register CPU1_PLL_CTRL0 control the settings of clock co...

Page 152: ...guration which enables correct operation of the N1 SoC Further SoC testing and measurement by Arm or by other developers might result in new register values 4 5 36 CLUS_PLL_CTRL0 Register The CLUS_PLL_CTRL0 Register characteristics are Purpose This register and register CLUS_PLL_CTRL1 control the settings of clock control PLL CLUSPLL Usage constraints There are no usage constraints Configurations ...

Page 153: ...in this register and the clock frequency they generate are part of a clock configuration which enables correct operation of the N1 SoC Further SoC testing and measurement by Arm or by other developers might result in new register values 4 5 37 CLUS_PLL_CTRL1 Register The CLUS_PLL_CTRL1 Register characteristics are Purpose This register and register CLUS_PLL_CTRL0 control the settings of clock cont...

Page 154: ...figuration which enables correct operation of the N1 SoC Further SoC testing and measurement by Arm or by other developers might result in new register values 4 5 38 SYS_PLL_CTRL0 Register The SYS_PLL_CTRL0 Register characteristics are Purpose This register and register SYS_PLL_CTRL1 control the settings of clock control PLL SYSPLL Usage constraints There are no usage constraints Configurations Av...

Page 155: ... in this register and the clock frequency they generate are part of a clock configuration which enables correct operation of the N1 SoC Further SoC testing and measurement by Arm or by other developers might result in new register values 4 5 39 SYS_PLL_CTRL1 Register The SYS_PLL_CTRL1 Register characteristics are Purpose This register and register SYS_PLL_CTRL0 control the settings of clock contro...

Page 156: ...iguration which enables correct operation of the N1 SoC Further SoC testing and measurement by Arm or by other developers might result in new register values 4 5 40 DMC_PLL_CTRL0 Register The DMC_PLL_CTRL0 Register characteristics are Purpose This register and register DMC_PLL_CTRL1 control the settings of clock control PLL DMCPLL Usage constraints There are no usage constraints Configurations Ava...

Page 157: ...es in this register and the clock frequency they generate are part of a clock configuration which enables correct operation of the N1 SoC Further SoC testing and measurement by Arm or by other developers might result in new register values 4 5 41 DMC_PLL_CTRL1 Register The DMC_PLL_CTRL1 Register characteristics are Purpose This register and register DMC_PLL_CTRL0 control the settings of clock cont...

Page 158: ...iguration which enables correct operation of the N1 SoC Further SoC testing and measurement by Arm or by other developers might result in new register values 4 5 42 INT_PLL_CTRL0 Register The INT_PLL_CTRL0 Register characteristics are Purpose This register and register INT_PLL_CTRL1 control the settings of clock control PLL INTPLL Usage constraints There are no usage constraints Configurations Ava...

Page 159: ...s in this register and the clock frequency they generate are part of a clock configuration which enables correct operation of the N1 SoC Further SoC testing and measurement by Arm or by other developers might result in new register values 4 5 43 INT_PLL_CTRL1 Register The INT_PLL_CTRL1 Register characteristics are Purpose This register and register INT_PLL_CTRL0 control the settings of clock contr...

Page 160: ... might result in new register values 4 5 44 SYS_MAN_RESET Register The SYS_MAN_RESET Register characteristics are Purpose Controls the manual resets of the internal resets at SoC level Usage constraints There are no usage constraints Configurations Available in all N1 board configurations Memory offset and full register reset value See 4 5 1 Serial Configuration Control registers summary on page 4...

Page 161: ... Reset Reset value 0b0 5 FORCE_SCP_SENSOR_RST SENSORCLK manual reset 0b0 Not reset 0b1 Reset Reset value 0b0 4 FORCE_SCP_QSPI_RST SCPQSPICLK manual reset 0b0 Not reset 0b1 Reset Reset value 0b0 3 FORCE_SCP_I2C_RST SCP I2CCLK manual reset 0b0 Not reset 0b1 Reset Reset value 0b0 2 FORCE_IOFPGA_TSIF_RST TSIF2XCLK manual reset 0b0 Not reset 0b1 Reset Reset value 0b0 4 Programmers model 4 5 Serial Conf...

Page 162: ...er reset value See 4 5 1 Serial Configuration Control registers summary on page 4 120 The following table shows the BOOT_CTL Register bit assignments Table 4 76 BOOT_CTL Register bit assignments Bits Name Type Function 31 PORESET_HOLD RO from APB interface RW from serial interface Powerup reset hold 0b0 Do not hold powerup reset 0b1 Hold powerup reset Reset value 0b0 Note This bit is valid only wh...

Page 163: ...t value 0x00 23 7 Reserved 6 MCP_ACG_QDENY RO MCP ACG QDENYn Reset value 0b0 5 MCP_ACG_QACCEPT RO MCP ACG QACCEPTn Reset value 0b0 4 MCP_QACTIVE RO MCP ACG QACTIVE Reset value 0b0 3 RO Reserved 2 SCP_ACG_QDENY RO SCP ACG QDENYn 1 SCP_QACCEPT RO SCP ACG QACCEPTn Reset value 0b0 0 SCP_ACG_QACTIVE RO SCP ACG QACTIVE Reset value 0b0 4 5 47 SCP_BOOT_ADR Register The SCP_BOOT_ADR Register characteristic...

Page 164: ...4 5 1 Serial Configuration Control registers summary on page 4 120 The following table shows the MCP_BOOT_ADR Register bit assignments Table 4 79 MCP_BOOT_ADR Register bit assignments Bits Name Type Function 31 0 ADDRESS RO from APB interface RW from serial interface Bootup address of MCP Reset value 0x00000000 4 5 49 PLATFORM_CTRL Register The PLATFORM_CTRL Register characteristics are Purpose N1...

Page 165: ... Configuration Control registers summary on page 4 120 The following table shows the TARGETIDAPP Register bit assignments Table 4 81 TARGETIDAPP Register bit assignments Bits Name Type Function 31 0 ID RO from APB interface RW from serial interface CoreSight target ID of AP Reset value 0x07B00477 4 5 51 TARGETIDSCP Register The TARGETIDSCP Register characteristics are Purpose Stores the SCP bootup...

Page 166: ...7 4 5 53 BOOT_GPR0 Register The BOOT_GPR0 Register characteristics are Purpose Bootup general purpose register This register enables an external controller to pass bootup configuration information into the N1 SoC before the release of the powerup reset The register does not export any control from the SCC Usage constraints This register is read only from the APB interface and read write from the s...

Page 167: ...er The BOOT_GPR2 Register characteristics are Purpose Bootup general purpose register This register enables an external controller to pass bootup configuration information into the N1 SoC before the release of the powerup reset The register does not export any control from the SCC Usage constraints This register is read only from the APB interface and read write from the serial interface Configura...

Page 168: ...of the powerup reset The register does not export any control from the SCC Usage constraints This register is read only from the APB interface and read write from the serial interface Configurations Available in all N1 board configurations Memory offset and full register reset value See 4 5 1 Serial Configuration Control registers summary on page 4 120 The following table shows the BOOT_GPR4 Regis...

Page 169: ...5 1 Serial Configuration Control registers summary on page 4 120 The following table shows the BOOT_GPR6 Register bit assignments Table 4 90 BOOT_GPR6 Register bit assignments Bits Name Type Function 31 0 REG RO from APB interface RW from serial interface Bootup general purpose register 6 Reset value 0x00000000 4 5 60 BOOT_GPR7 Register The BOOT_GPR7 Register characteristics are Purpose Bootup gen...

Page 170: ... 4 92 INSTANCE_ID Register bit assignments Bits Name Type Function 31 4 Reserved 3 0 ID RO from APB interface RW from serial interface SWJ DP instance ID register Reset value 0b0000 4 5 62 PCIE_BOOT_CTRL Register The PCIE_BOOT_CTRL Register characteristics are Purpose Enables reset of sticky bits in the PCIe and CCIX controllers during reset of the PCIe and CCIX controllers Usage constraints There...

Page 171: ...r characteristics are Purpose Drives the CoreSight authentication external interface Usage constraints There are no usage constraints Configurations Available in all N1 board configurations Memory offset and full register reset value See 4 5 1 Serial Configuration Control registers summary on page 4 120 The following table shows the DBG_AUTHN_CTRL Register bit assignments Table 4 94 DBG_AUTHN_CTRL...

Page 172: ...5 1 Serial Configuration Control registers summary on page 4 120 The following table shows the CTI0_CTRL Register bit assignments Table 4 95 CTI0_CTRL Register bit assignments Bits Name Type Function 31 16 Reserved 15 8 TODBGENSEL RW CTI TODBGENSEL input Reset value 0x00 7 0 TINIDENSEL RW CTI TINIDENSEL input Reset value 0x00 4 5 65 CTI1_CTRL Register The CTI1_CTRL Register characteristics are Pur...

Page 173: ...ons Memory offset and full register reset value See 4 5 1 Serial Configuration Control registers summary on page 4 120 The following table shows the CTI0TO3_CTRL Register bit assignments Table 4 97 CTI0TO3_CTRL Register bit assignments Bits Name Type Function 31 16 Reserved 15 8 TODBGENSEL RW CTI TODBGENSEL input Reset value 0x00 7 0 TINIDENSEL RW CTI TINIDENSEL input Reset value 0x00 4 5 67 MCP_W...

Page 174: ...rol registers summary on page 4 120 The following table shows the SCP_WDOGCTI_CTRL Register bit assignments Table 4 99 SCP_WDOGCTI_CTRL Register bit assignments Bits Name Type Function 31 16 Reserved 15 8 TODBGENSEL RW CTI TODBGENSEL input Reset value 0x00 7 0 Reserved 4 5 69 DBGEXPCTI_CTRL Register The DBGEXPCTI_CTRL Register characteristics are Purpose CTI trigger mask register Usage constraints...

Page 175: ... Memory offset and full register reset value See 4 5 1 Serial Configuration Control registers summary on page 4 120 The following table shows the PCIE_PM_CTRL Register bit assignments Table 4 101 PCIE_PM_CTRL Register bit assignments Bits Name Type Function 31 2 Reserved 1 PM_ACK RO PCIe powerup acknowledgement 0b0 Not acknowledge 0b1 Acknowledge Reset value 0b0 0 PM_REQ RW PCIe powerup request 0b...

Page 176: ...stics are Purpose SCC scan based debug control register Usage constraints Bits 9 8 and bits 5 4 are read only Bits 15 0 are reserved All other bits are read write Configurations Available in all N1 board configurations Memory offset and full register reset value See 4 5 1 Serial Configuration Control registers summary on page 4 120 The following table shows the SCDBG_CTRL Register bit assignments ...

Page 177: ...o effect 0b1 Include manual trigger Reset value 0b0 5 TRIG_ELA_SOC RO Or ed Logic Analyzer ELA STOPCLOCK trigger from all N1 SoC ELAs Reset value 0b0 4 TRIG_ELA_AP RO Or ed Logic Analyzer ELA STOPCLOCK trigger from both N1clusters Reset value 0b0 3 TRIG_CTHALT_C1 RW Include N1 cluster 1 cross trigger halt event OR function of all PE cross trigger halt events Reset value 0b0 2 TRIG_CTHALT_C0 RW Inc...

Page 178: ...Memory offset and full register reset value See 4 5 1 Serial Configuration Control registers summary on page 4 120 The following table shows the EXP_IF_CTRL Register bit assignments Table 4 104 EXP_IF_CTRL Register bit assignments Bits Name Type Function 31 24 Reserved 23 16 TSIF_WIN_ADDR RW Controls the location of the TSIF 1TB address window inside the Application Processor memory map 0 4TB for ...

Page 179: ...Used LRU replacement policy This policy typically provides the best average performance However when multiple translations are prefetched using a StashTranslation transaction they might evict each other 0b1 The Micro TLB uses a round robin replacement policy This policy enables prefetch multiple translations using a StashTranslation transaction without evictions if the Micro TLB size is not exceed...

Page 180: ...Serial Configuration Control registers summary on page 4 120 The following table shows the CMN_CCIX_CTRL Register bit assignments Table 4 106 CMN_CCIX_CTRL Register bit assignments Bits Name Type Function 31 28 Reserved 27 CXLA_CXSCLK _QDENY RO QDENY of CXLA CXSCLK control Q channel at CXS interface side Reset value 0b0 26 CXLA_CXSCLK _QACCEPT RO QACCEPTn of CXLA CXSCLK control Q channel at CXS in...

Page 181: ...de This bit maintains its reset value while the CCIX subsystem is operating It is only used to complete Q channel power down handshakes when the CCIX subsystem CCIX PCIe controller needs reset while the main part of CMN 600 is running This is useful for CCIX subsystem error clearance Reset value 0b1 15 0 PCIE_BUS_NUM RW The PCIe ID BUS_NUM 15 8 DEVICE_NUM 7 3 FUNCTION_NUM 2 0 used for CMN 600 to f...

Page 182: ... enabled that is the AXI can stall and the trace output is guaranteed Reset value 0b0 4 5 77 AXI_OVRD_PCIE Register The AXI_OVRD_PCIE Register characteristics are Purpose Controls PCIe AXI slave expansion interface override Usage constraints There are no usage constraints Configurations Available in all N1 board configurations Memory offset and full register reset value See 4 5 1 Serial Configurat...

Page 183: ... Controls CCIX AXI slave expansion interface override Usage constraints There are no usage constraints Configurations Available in all N1 board configurations Memory offset and full register reset value See 4 5 1 Serial Configuration Control registers summary on page 4 120 The following table shows the AXI_OVRD_CCIX Register bit assignments Table 4 109 AXI_OVRD_CCIX Register bit assignments Bits N...

Page 184: ...nts There are no usage constraints Configurations Available in all N1 board configurations Memory offset and full register reset value See 4 5 1 Serial Configuration Control registers summary on page 4 120 The following table shows the AXI_OVRD_TSIF Register bit assignments Table 4 110 AXI_OVRD_CCIX Register bit assignments Bits Name Type Function 31 14 Reserved 13 12 ARDOMAIN RW Override value of...

Page 185: ...e Function 31 29 Reserved 28 IO_SR_TRACE_DATA 3 RW Slew rate control of trace port output pads TRACE_DATA 31 24 0b0 Fast 0b1 Slow Reset value 0b1 27 26 Reserved 25 24 IO_DS_TRACE_DATA 3 RW Drive strength control of trace port output pads TRACE_DATA 31 24 0b00 2mA 0b01 8mA 0b10 4mA 0b11 12mA Reset value 0b01 23 21 Reserved 20 IO_SR_TRACE_DATA 2 RW Slew rate control of trace port output pads TRACE_D...

Page 186: ...ACE_DATA 1 RW Drive strength control of trace port output pads TRACE_DATA 15 8 0b00 2mA 0b01 8mA 0b10 4mA 0b11 12mA Reset value 0b01 7 5 Reserved 4 IO_SR_TRACE_DATA 0 RW Slew rate control of trace port output pads TRACE_DATA 7 0 0b0 Fast 0b1 Slow Reset value 0b1 3 2 Reserved 1 0 IO_DS_TRACE_DATA 0 RW Drive strength control of trace port output pads TRACE_DATA 7 0 0b00 2mA 0b01 8mA 0b10 4mA 0b11 12...

Page 187: ...le 4 112 TRACE_PAD_CTRL1 Register bit assignments Bits Name Type Function 31 13 Reserved 12 IO_SR_TRACE_CLK_B RW Slew rate control of trace port output pad TRACE_CLK_B 0b0 Fast 0b1 Slow Reset value 0b1 11 10 Reserved 9 8 IO_DS_TRACE_CLK_B RW Drive strength control of trace port output pad TRACE_CLK_B 0b00 2mA 0b01 8mA 0b10 4mA 0b11 12mA Reset value 0b01 7 5 Reserved 4 IO_SR_TRACE_CLK_A RW Slew rat...

Page 188: ...ster reset value See 4 5 1 Serial Configuration Control registers summary on page 4 120 The following table shows the IOFPGA_TMIF_PAD_CTRL Register bit assignments Table 4 113 IOFPGA_TMIF_PAD_CTRL Register bit assignments Bits Name Type Function 31 21 Reserved 20 IO_SR_IOFPGA_AXI_TMIF_CLK RW Slew rate control of IOFPGA AXI TMIF output pad IOFPGA_TMIF_CLK_O 0b0 Fast 0b1 Slow Reset value 0b1 19 18 R...

Page 189: ...MIF_DATA RW Slew rate control of IOFPGA AXI TMIF output pads IOFPGA_TMIF_DATA_O 7 0 0b0 Fast 0b1 Slow Reset value 0b1 3 2 Reserved 1 0 IO_DS_IOFPGA_AXI_TMIF_DATA RW Drive strength control of IOFPGA AXI TMIF output pads IOFPGA_TMIF_DATA_O 7 0 0b00 2mA 0b01 8mA 0b10 4mA 0b11 12mA Reset value 0b01 4 5 83 IOFPGA_TSIF_PAD_CTRL Register The IOFPGA_TSIF_PAD_CTRL Register characteristics are Purpose Contr...

Page 190: ..._AXI_TSIF_CLK RW Drive strength control of IOFPGA AXI TSIF output pad IOFPGA_TSIF_CLK_O 0b00 2mA 0b01 8mA 0b10 4mA 0b11 12mA Reset value 0b01 15 13 Reserved 12 IO_SR_IOFPGA_AXI_TSIF_CTL RW Slew rate control of IOFPGA AXI TSIF output pads IOFPGA_TSIF_VALID_O and IOFPGA_TSIF_CTL_O 1 0 0b0 Fast 0b1 Slow Reset value 0b1 11 10 Reserved 9 8 IO_DS_IOFPGA_AXI_TSIF_CTL RW Drive strength control of IOFPGA A...

Page 191: ...rations Available in all N1 board configurations Memory offset and full register reset value See 4 5 1 Serial Configuration Control registers summary on page 4 120 The following table shows the APB_CTRL_CLR Register bit assignments Table 4 115 APB_CTRL_CLR Register bit assignments Bits Name Type Function 31 12 NUMBER RW Writing 0xA50F5 to this field sets the register whose base address bits 11 0 s...

Page 192: ...ions Memory offset and full register reset value See 4 5 1 Serial Configuration Control registers summary on page 4 120 The following table shows the PID0 Register bit assignments Table 4 117 PID0 Register bit assignments Bits Name Type Function 31 8 Reserved 7 0 PID0 RO Peripheral ID 0 identification Reset value 0xAF 4 5 87 PID1 Register The PID1 Register characteristics are Purpose Stores periph...

Page 193: ...e shows the PID2 Register bit assignments Table 4 119 PID2 Register bit assignments Bits Name Type Function 31 8 Reserved 7 0 PID2 RO Peripheral ID 2 identification Reset value 0x0B 4 5 89 PID3 Register The PID3 Register characteristics are Purpose Stores peripheral identification information Usage constraints This register is read only Configurations Available in all N1 board configurations Memor...

Page 194: ...assignments Table 4 121 CID0 Register bit assignments Bits Name Type Function 31 8 Reserved 7 0 CID3 RO Component ID 3 identification Reset value 0x0D 4 5 91 CID1 Register The CID1 Register characteristics are Purpose Stores component identification information Usage constraints This register is read only Configurations Available in all N1 board configurations Memory offset and full register reset...

Page 195: ...assignments Table 4 123 CID2 Register bit assignments Bits Name Type Function 31 8 Reserved 7 0 CID2 RO Component ID 2 identification Reset value 0x05 4 5 93 CID3 Register The CID3 Register characteristics are Purpose Stores component identification information Usage constraints This register is read only Configurations Available in all N1 board configurations Memory offset and full register reset...

Page 196: ...unction 31 8 Reserved 7 0 CID3 RO Component ID 3 identification Reset value 0xB1 4 Programmers model 4 5 Serial Configuration Control registers 101489_0000_02_en Copyright 2019 2020 Arm Limited or its affiliates All rights reserved 4 196 Non Confidential Beta ...

Page 197: ... RO RW 0xX00000XX 32 See 4 6 3 SYS_SW Register on page 4 198 0x0008 SYS_LED RO RW 0x000000XX 32 See 4 6 4 SYS_LED Register on page 4 199 0x0024 SYS_100HZ RO RW 0xXXXXXXXX 32 See 4 6 5 SYS_100HZ Register on page 4 199 0x0030 SYS_FLAG RO 0x00000000 32 See 4 6 6 SYS_FLAG Registers on page 4 200 0x0030 SYS_FLAGSSET WO 32 See 4 6 6 SYS_FLAG Registers on page 4 200 0x0034 SYS_FLAGSCLR WO 32 See 4 6 6 SY...

Page 198: ...owing table shows the bit assignments Table 4 126 SYS_ID Register bit assignments Bits Name Type Function 31 28 Rev RO Board revision 0x0 Rev A board This is the prototype board and contains the N1 SoC 26 16 HBI RO HBI board number in BCD 0x316 HBI0316 15 12 Build RO Build variant of board 0xF All builds 11 8 Arch RO IOFPGA bus architecture 0x4 AHB 0x5 AXI 7 0 FPGA RO FPGA build in BCD The actual ...

Page 199: ...stics are Purpose Controls the eight user LEDs on the N1 SDP All LEDs are turned OFF at reset The Boot Monitor updates the LED value Usage constraints There are no usage constraints Configurations Available in all N1 board configurations Memory offset and full register reset value See 4 6 1 APB system register summary on page 4 197 The following table shows the bit assignments Table 4 128 SYS_LED ...

Page 200: ...YS_NVFLAGSCLR registers to set and clear the bits in the Flag Registers Usage constraints The SYS_FLAGS and SYS_NVFLAGS Registers are read only The SYS_FLAGSSET SYS_FLAGSCLR SYS_NVFLAGSSET and SYS_NVFLAGSCLR Registers are write only Configurations Available in all N1 SDP configurations SYS_FLAGS Register The SYS_FLAGS Register is one of the two flag registers It contains the current states of the ...

Page 201: ...traints Configurations Available in all N1 board configurations Memory offset and full register reset value See 4 6 1 APB system register summary on page 4 197 The following table shows the bit assignments Table 4 130 SYS_CFGSW Register bit assignments Bits Name Type Function 31 8 Reserved 7 0 SOFT_CONFIG_SWITCH RW Software applications can read these switch settings The application software defin...

Page 202: ...board configurations Memory offset and full register reset value See 4 6 1 APB system register summary on page 4 197 The following table shows the bit assignments Table 4 132 SYS_PCIE_CNTL Register bit assignments Bits Name Type Function 31 2 Reserved 1 PCIE_RSTHALT RW Error signal from PCIe switch 0 PCIE_nPERST RW Reset signal to PCIe expansion slots 4 6 10 SYS_PCIE_GBE Register The SYS_PCIE_GBE ...

Page 203: ...mary on page 4 197 The following table shows the bit assignments Table 4 134 SYS_PROC_ID0 Register bit assignments Bits Name Type Function 31 24 PROC_ID0 RW Denotes active clusters 23 0 Reserved 4 6 12 SYS_FAN_SPEED Register The SYS_FAN_SPEED Register characteristics are Purpose Contains a value that represents the fan operating speed The MCC uses this value to moderate the speed of the cooling fa...

Page 204: ...re Purpose This register in the SP810 system controller selects the source clocks for the four SP804 timers in the IOFPGA Usage constraints There are no usage constraints Configurations Available in all N1 board configurations Memory offset and full register reset value See 4 6 1 APB system register summary on page 4 197 The following table shows the bit assignments Table 4 136 SP810_CTRL Register...

Page 205: ...En1Sel Selects the source clock for SP804 1 timer clock TIM_CLK 1 0b0 TIM_CLK 1 32kHz 0b1 TIM_CLK 1 1MHz Note The default is 0b0 16 Reserved 15 TimerEn0Sel Selects the source clock for SP804 0 timer clock TIM_CLK 0 0b0 TIM_CLK 0 32kHz 0b1 TIM_CLK 0 1MHz Note The default is 0b0 14 0 Reserved 4 Programmers model 4 6 APB system registers 101489_0000_02_en Copyright 2019 2020 Arm Limited or its affili...

Page 206: ... 4 221 4 7 22 SYS_POW_DDR0 Register on page 4 221 4 7 23 SYS_POW_DDR1 Register on page 4 222 4 7 24 SYS_ENM_DDR0 Register on page 4 223 4 7 25 SYS_ENM_DDR1 Register on page 4 224 4 7 1 APB energy meter registers summary The base memory address of the APB energy meter registers in the IOFPGA is 0x1C01_0000 The APB energy meter registers contain values that represent supply currents supply voltages ...

Page 207: ...0x0000_0000 32 See 4 7 12 SYS_POW_PCIE Register on page 4 214 0x00FC SYS_POW_ CL1 RO 0x0000_0000 32 See 4 7 13 SYS_POW_CL1 Register on page 4 214 0x0100 SYS_ENM_L_SYS RW 0x0000_0000 32 See 4 7 14 SYS_ENM_SYS Register on page 4 215 0x0104 SYS_ENM_H_SYS RW 0x0000_0000 32 See 4 7 14 SYS_ENM_SYS Register on page 4 215 0x0108 SYS_ENM_L_CL0 RW 0x0000_0000 32 See 4 7 15 SYS_ENM_CL0 Register on page 4 216...

Page 208: ...pply Usage constraints This register is read only Configurations Available in all N1 board configurations Memory offset and full register reset value See 4 7 1 APB energy meter registers summary on page 4 206 Note The value measured by this register is provisional and subject to characterization on the RevB boards The following table shows the bit assignments Table 4 138 SYS_I_SYS Register bit ass...

Page 209: ...ll scale measurement 4096 represents 10A Full scale is 0xFFF Measured current SYS_I_CL0 1 381 amperes The CB_nRST reset signal resets the register to zero The register then updates every 100µs after the reset 4 7 4 SYS_I_PCIE Register The SYS_I_PCIE Register characteristics are Purpose Contains a 12 bit representation of the instantaneous current consumption of the PCIe cluster Usage constraints T...

Page 210: ...egisters summary on page 4 206 Note The value measured by this register is provisional and subject to characterization on the RevB boards The following table shows the bit assignments Table 4 141 SYS_I_CL1 Register bit assignments Bits Name Type Function 31 12 Reserved 11 0 SYS_I_CL1 RO 12 bit representation of current consumption of N1 cluster 1 Full scale measurement 4096 represents 5A Full scal...

Page 211: ...2 bit representation of the instantaneous supply voltage of N1 SoC cluster 0 Usage constraints This register is read only Configurations Available in all N1 board configurations Memory offset and full register reset value See 4 7 1 APB energy meter registers summary on page 4 206 The following table shows the bit assignments Table 4 143 SYS_V_CL0 Register bit assignments Bits Name Type Function 31...

Page 212: ... Register The SYS_V_CL1 Register characteristics are Purpose Contains a 12 bit representation of the instantaneous supply voltage of N1 SoC cluster 1 Usage constraints This register is read only Configurations Available in all N1 board configurations Memory offset and full register reset value See 4 7 1 APB energy meter registers summary on page 4 206 The following table shows the bit assignments ...

Page 213: ... operate from the VSYS power supply The value of these bits represents SYS_I_SYS I SYS_V_SYS V 1234803 watts Measured power consumption SYS_POW_SYS 1234803 The CB_nRST reset signal resets the register to zero The register then updates every 100µs after the reset 4 7 11 SYS_POW_CL0 Register The SYS_POW_CL0 Register characteristics are Purpose Contains a 24 bit representation of the instantaneous po...

Page 214: ...nergy meter registers summary on page 4 206 Note The value measured by this register is provisional and subject to characterization on the RevB boards The following table shows the bit assignments Table 4 148 SYS_POW_PCIE Register bit assignments Bits Name Type Function 31 24 Reserved 23 0 SYS_POW_PCIE RO 24 bit representation of the instantaneous power consumption of PCIe cluster The value of the...

Page 215: ...er consumption SYS_POW_CL1 1234803 watts The CB_nRST reset signal resets the register to zero The register then updates every 100µs after the reset 4 7 14 SYS_ENM_SYS Register The SYS_ENM_SYS Register characteristics are Purpose Contains a 64 bit representation of the accumulated energy consumption of the fabric of the N1 SoC outside the clusters Usage constraints Writing to this register clears t...

Page 216: ...00 Accumulated energy SYS_ENM_CH0_H_SYS SYS_ENM_L_SYS 12348030000 joules The CB_nRST reset signal resets the register to zero The register then updates every 100µs after the reset 4 7 15 SYS_ENM_CL0 Register The SYS_ENM_CL0 Register characteristics are Purpose Contains a 64 bit representation of the accumulated energy consumption of the N1 SoC cluster 0 Usage constraints This register is read only...

Page 217: ...M_H_CL0 SYS_ENM_L_CL0 6174020000 joules The CB_nRST reset signal resets the register to zero The register then updates every 100µs after the reset 4 7 16 SYS_ENM_PCIE Register The SYS_ENM_PCIE Register characteristics are Purpose Contains a 64 bit representation of the accumulated energy consumption of the PCIE cluster 0 Usage constraints This register is read only Configurations Available in all ...

Page 218: ..._ENM_H_PCIE SYS_ENM_L_PCIE 6174020000 joules The CB_nRST reset signal resets the register to zero The register then updates every 100µs after the reset 4 7 17 SYS_ENM_CL1 Register The SYS_ENM_CL1 Register characteristics are Purpose Contains a 64 bit representation of the accumulated energy consumption of N1 SoC cluster 1 Usage constraints This register is read only Configurations Available in all...

Page 219: ...ster characteristics are Purpose Contains a 12 bit representation of the instantaneous current consumption of DDR 0 Usage constraints This register is read only Configurations Available in all N1 board configurations Memory offset and full register reset value See 4 7 1 APB energy meter registers summary on page 4 206 Note The value measured by this register is provisional and subject to character...

Page 220: ...ion of the instantaneous current consumption of DDR 1 Full scale measurement 4096 represents 10A Full scale is 0xFFF Measured current SYS_I_DDR 1 1 381 amperes The CB_nRST reset signal resets the register to zero The register then updates every 100µs after the reset 4 7 20 SYS_V_DDR0 Register The SYS_V_DDR0 Register characteristics are Purpose Contains a 12 bit representation of the instantaneous ...

Page 221: ...ergy meter registers summary on page 4 206 The following table shows the bit assignments Table 4 157 SYS_V_DDR1 Register bit assignments Bits Name Type Function 31 12 Reserved 11 0 SYS_V_DDR1 RO 12 bit representation of the instantaneous supply voltage of DDR 1 Full scale measurement 4096 represents 2V5 Full scale is 0xFFF Measured voltage SYS_V_DDR1 1 1622 volts The CB_nRST reset signal resets th...

Page 222: ...et signal resets the register to zero The register then updates every 100µs after the reset 4 7 23 SYS_POW_DDR1 Register The SYS_POW_DDR1 Register characteristics are Purpose Contains a 24 bit representation of the instantaneous power consumption of DDR 1 Usage constraints This register is read only Configurations Available in all N1 board configurations Memory offset and full register reset value...

Page 223: ...nal and subject to characterization on the RevB boards The following table shows the bit assignments Table 4 160 SYS_ENM_DDR0 Register bit assignments Bits Name Type Function 63 32 SYS_ENM_H_DDR0 RO Most significant 32 bits of a 64 bit representation of the accumulated energy consumption of DDR 0 The memory address offset of these bits is 0x013C Accumulated energy SYS_ENM_H_DDR0 SYS_ENM_L_DDR0 617...

Page 224: ...nificant 32 bits of a 64 bit representation of the accumulated energy consumption of DDR 1 The memory address offset of these bits is 0x0144 Accumulated energy SYS_ENM_H_DDR1 SYS_ENM_L_DDR1 6174020000 joules The CB_nRST reset signal resets the register to zero The register then updates every 100µs after the reset 31 0 SYS_ENM_L_DDR1 RO Least significant 32 bits of a 64 bit representation of the ac...

Page 225: ...s memory map See 4 2 4 Manageability Control Processor peripherals memory map on page 4 84 FPGAUART1 0x00_1C09_0000 IOFPGA memory map 4 2 8 IOFPGA memory map on page 4 93 FPGAUART2 0x00_1C0A_0000 IOFPGA memory map 4 2 8 IOFPGA memory map on page 4 93 Note APUART1 is used to communicate with the MCP through MCPUART1 and is accessible to the Application Processor AP cores MCPUART1 is not accessible ...

Page 226: ...ntrol Register 0x0FE0 UART0PeriphID0 RO 0x0000_0011 32 UART0 peripheral ID Register 0 0x0FE4 UART0PeriphID1 RO 0x0000_0010 32 UART0 peripheral ID Register 1 0x0FE8 UART0PeriphID2 RO 0x0000_0004 32 UART0 peripheral ID Register 2 0x0FEC UART0PeriphID3 RO 0x0000_0000 32 UART0 peripheral ID Register 3 0x0FF0 UART0PCellID0 RO 0x0000_000D 32 UART0 component ID Register 0 0x0FF4 UART0PCellID1 RO 0x0000_0...

Page 227: ... RO 0x0000_0011 32 UART1 peripheral ID Register 0 0x1FE4 UART1PeriphID1 RO 0x0000_0010 32 UART1 peripheral ID Register 1 0x1FE8 UART1PeriphID2 RO 0x0000_0004 32 UART1 peripheral ID Register 2 0x1FEC UART1PeriphID3 RO 0x0000_0000 32 UART1 peripheral ID Register 3 0x1FF0 UART1PCellID0 RO 0x0000_000D 32 UART1 component ID Register 0 0x1FF4 UART1PCellID1 RO 0x0000_00F0 32 UART1 component ID Register 1...

Page 228: ...s on page Appx A 231 A 3 N1 SoC JTAG connector on page Appx A 232 A 4 Trace connector on page Appx A 233 A 5 Front panel I O header on page Appx A 235 A 6 PCI Express and CCIX slots on page Appx A 236 A 7 C2C connector on page Appx A 237 A 8 Power connectors on page Appx A 238 101489_0000_02_en Copyright 2019 2020 Arm Limited or its affiliates All rights reserved Appx A 228 Non Confidential Beta ...

Page 229: ... CTS 7 DTR 8 No connection 9 GND Arm supplies the N1 SDP with a ribbon cable connecting the UART0 header to the UART0 DB9 connector on the back panel Table A 2 UART1 header signal list Pin Signal Pin Signal 1 No connection 2 No connection 3 RX 4 No connection 5 TX 6 No connection 7 No connection 8 No connection 9 GND Arm supplies the N1 SDP with a ribbon cable connecting the UART1 header to the UA...

Page 230: ... 4 No connection 5 TX 6 No connection 7 No connection 8 No connection 9 GND Related information 1 3 The N1 SDP at a glance on page 1 14 A Signal descriptions A 1 UART headers 101489_0000_02_en Copyright 2019 2020 Arm Limited or its affiliates All rights reserved Appx A 230 Non Confidential Beta ...

Page 231: ...el Table A 5 UART0 DB9 connector signal list Pin Signal Pin Signal 1 No connection 2 RX 3 TX 4 DTR 5 GND 6 DSR 7 RTS 8 CTS 9 No connection Table A 6 UART1 DB9 connector signal list Pin Signal Pin Signal 1 No connection 2 RX 3 TX 4 No connection 5 GND 6 No connection 7 No connection 8 No connection 9 No connection Arm supplies the N1 SDP with ribbon cables making the following connections DB9 conne...

Page 232: ... 8 GND 9 TCK 10 GND 11 RTCK 12 GND 13 TDO 14 GND 15 nSRSTI 16 GND 17 DBGRQ 18 GND 19 DBGACK 20 GND Note Pin 1 is the lower left pin of the connector Pin 2 is the upper left pin of the connector Pins 1 5 7 13 15 and 19 have pullup resistors to 1V8 Pins 3 9 11 and 17 have pulldown resistors to GND Related information 1 3 The N1 SDP at a glance on page 1 14 A Signal descriptions A 3 N1 SoC JTAG conne...

Page 233: ..._DATA20 21 TRACE_DATA1 22 TRACE_DATA21 23 TRACE_DATA2 24 TRACE_DATA22 25 TRACE_DATA3 26 TRACE_DATA23 27 TRACE_DATA4 28 TRACE_DATA24 29 TRACE_DATA5 30 TRACE_DATA25 31 TRACE_DATA6 32 TRACE_DATA26 33 TRACE_DATA7 34 TRACE_DATA27 35 TRACE_DATA8 36 TRACE_DATA28 37 TRACE_DATA9 38 TRACE_DATA29 39 TRACE_DATA10 40 TRACE_DATA30 41 TRACE_DATA11 42 TRACE_DATA31 43 TRACE_DATA12 44 No connection 45 TRACE_DATA13 ...

Page 234: ...No connection Note Pin 17 TRACE_CTL is not used and has a pulldown resistor to GND Related information 1 3 The N1 SDP at a glance on page 1 14 A Signal descriptions A 4 Trace connector 101489_0000_02_en Copyright 2019 2020 Arm Limited or its affiliates All rights reserved Appx A 234 Non Confidential Beta ...

Page 235: ...MCC USB activity These pins are not brought out to the front panel 9 10 Connects to green LED in 4 level light pipe third from bottom on back panel Denotes MCC USB activity These pins are not brought out to the front panel 11 12 Power LED embedded in PBON button on front panel 13 14 HDD activity LED on front panel This signal is a combined signal from SATA0 and SATA1 15 16 Connects to the GbE acti...

Page 236: ...nes implemented Table A 10 PCI Express expansion slots Slot number PCIe lane connector size Used lanes Unused lanes Comment Slot 1 4 1 3 PCIe Slot 2 16 16 0 PCIe Slot 3 16 8 8 PCIe Slot 4 16 16 0 PCIe CCIX dual use Related information 1 3 The N1 SDP at a glance on page 1 14 A Signal descriptions A 6 PCI Express and CCIX slots 101489_0000_02_en Copyright 2019 2020 Arm Limited or its affiliates All ...

Page 237: ...ity Arm supplies adapter boards and connector cables for the master and slave CCIX slots See 2 9 Chip to Chip communications on page 2 48 Related information 1 3 The N1 SDP at a glance on page 1 14 A Signal descriptions A 7 C2C connector 101489_0000_02_en Copyright 2019 2020 Arm Limited or its affiliates All rights reserved Appx A 237 Non Confidential Beta ...

Page 238: ...ctions The following table shows the ATX EPS connector pin mapping Table A 11 ATX EPS pin mapping Pin Connection 1 GND 2 GND 3 GND 4 GND 5 12V 6 12V 7 12V 8 12V Related information 1 3 The N1 SDP at a glance on page 1 14 A Signal descriptions A 8 Power connectors 101489_0000_02_en Copyright 2019 2020 Arm Limited or its affiliates All rights reserved Appx A 238 Non Confidential Beta ...

Page 239: ...the technical changes between released issues of this book It contains the following section B 1 Revisions on page Appx B 240 101489_0000_02_en Copyright 2019 2020 Arm Limited or its affiliates All rights reserved Appx B 239 Non Confidential Beta ...

Page 240: ...ormation 4 7 APB energy meter registers on page 4 206 RevA boards Changed variable names in config txt file variables table Changed variable names in example config tx file 2 10 UARTs on page 2 51 3 3 2 config txt board configuration file on page 3 65 All board versions Added peripheral memory maps 4 2 2 Application Processor subsystem peripherals memory map on page 4 79 4 2 4 Manageability Contro...

Page 241: ...p 4 2 1 Application Processor memory map on page 4 76 All board versions Clarified PCIe and CCIX information in Application Processor memory map 4 2 1 Application Processor memory map on page 4 76 All board versions Added GICR to Application Processor subsystem peripherals memory map 4 2 2 Application Processor subsystem peripherals memory map on page 4 79 All board versions Added details of memor...

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