The following table shows the CPU1_PLL_CTRL0 Register bit assignments.
Table 4-65 CPU1_PLL_CTRL0 Register bit assignments
Bits
Name
Type
Function
[31]
PLLEN
RW
PLL global enable. After SoC bootup, the
PLL is disabled until this bit is set to
0b1
:
0x0
: PLL disabled.
0x1
: PLL enabled.
Reset value
0x1
.
[30:26] -
-
Reserved.
[25:20] REFDIV
RW
PLL reference, input clock, divider value.
Reset value
0b1
.
[19:8]
FBDIV
RW
PLL feedback divider value.
Reset value
0x30
, division value=48.
[7:1]
-
-
Reserved.
[0]
HARD_BYPASS
RW
Bypasses PLL to drive input clock directly
into the SoC:
0x0
: PLL not bypassed.
0x1
: PLL bypassed.
Reset value
0b0
.
Note
The example values in this register, and the clock frequency they generate, are part of a clock
configuration which enables correct operation of the N1 SoC. Further SoC testing and measurement, by
Arm or by other developers, might result in new register values.
4.5.35
CPU1_PLL_CTRL1 Register
The CPU1_PLL_CTRL1 Register characteristics are:
Purpose
This register, and register CPU1_PLL_CTRL0, control the settings of clock control PLL
CPU1PLL.
Usage constraints
There are no usage constraints.
Configurations
Available in all N1 board configurations.
Memory offset and full register reset value
See
4.5.1 Serial Configuration Control registers summary
4 Programmers model
4.5 Serial Configuration Control registers
101489_0000_02_en
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