Technical Description
18
Seiko Epson Corporation
S5U13706B00C Rev. 1.0 Evaluation Board
Rev. 5.1
6 Technical Description
6.1 PCI Bus Support
The S1D13706
does not
have on-chip PCI bus interface support. The S1D13706B00C uses
the PCI Bridge FPGA to support the PCI bus.
6.2 Direct Host Bus Interface Support
The S5U13706B00C is specifically designed to work using the PCI Bridge FPGA in a
standard PCI bus environment. However, the S1D13706 directly supports many other host
bus interfaces. Connectors H3 and H4 provide the necessary IO pins to interface to these
host buses. For further information on the host bus interfaces supported, see “CPU
Interface” on page 13.
Note
The PCI Bridge FPGA must be disabled using SW1-10 in order for direct host bus inter-
face to operate properly.
6.3 S1D13706 Embedded Memory
The S1D13706 has 80K bytes of embedded SRAM. The 80K byte display buffer address
space is directly and contiguously available through the 17-bit address bus.
6.4 Manual/Software Adjustable LCD Panel Positive Power Supply (VDDH)
Most passive LCD color and passive single monochrome LCD panels require a positive
bias voltage b24V and +40V. The S5U13706B00C uses a Maxim MAX754 LCD
Contrast Controller to provide this voltage range. The signal VDDH can be adjusted
manually (using a potentiometer) or controlled through software.
When JP5 is set to position 1-2, VDDH can be controlled through software to provide an
output voltage from +20V to +40V. CVOUT and GPO of the S1D13706 are connected to
LADJ and LON of MAX754. The output voltage (VDDH) can be adjusted from +20V to
+40V in 64 steps by sending pulses to CVOUT. Each CVOUT pulse decrements VDDH
one step t20V. When decremented 20V, VDDH resets to +40V again. In
other words, 63 pulses equal incrementing 1 step. After the MAX754 is reset (see
“Controlling the MAX754” on page 19), VDDH is set at +30V.
