4. History Data Details
4.3
Connection Verification Methods
This section describes methods for verifying connections between the main CPU and the LSI and
between USB devices and the LSI.
4.3.1
Main CPU and LSI Connection Verification Method
This section describes the method for verifying connections between the main CPU and the
LSI. Individual IDE signals can be checked via control from the main CPU, as shown
below.
•
RESET signal confirmation method
1. Confirm that the “IDE: Hardware reset” history entry appears when the main CPU
issue a Hardware Reset.
•
CS1 signal confirmation method
1. Confirm that the “IDE: SRST” history entry appears when the main CPU issues an
SRST.
The following signals should be checked, depending on the transfer mode used. The
signals used for Multi Word DMA and PIO transfer can be checked simultaneously using
Ultra DMA transfer. The signals used for PIO transfer can be checked simultaneously
using Multi Word DMA transfer. Set the Device Control register nIEN bit to 0 when
issuing commands.
•
Method for confirming CS0-, CS1-, DA0 to DA2, DIOW-, DIOR-, INTRQ, and DD0 to
DD15 signals
[When using PIO transfer only]
Confirm by issuing a command from the main CPU and by using PIO transfer.
1. Issue the SET FEATURE command and set PIO transfer.
2. Issue the WRITE SECTOR(S) command. Confirm that the command ends
normally and that the history entry appears as “IDE: command [30h]” – “IDE: PIO
(H->D)” – “IDE: INTRQ” – “IDE: idle”.
3. Issue the READ SECTOR(S) command and read the data written in 2. Confirm
that the command ends normally and that the history entry appears as “IDE:
command [20h]” – “IDE: PIO (D->H)” – “IDE: idle”.
This enables evaluation of the CS0-, CS1-, DA0 to DA2, DIOW-, DIOR-, and INTRQ
signals.
4. Compare the data written by the WRITE SECTOR(S) command against the data
read by the READ SECTOR(S) command. Confirm that they match.
This enables evaluation of the DD0 to DD15 signals.
12
EPSON
S1R72U16 Development Support
Manual (Rev.2.00)
