7
DETAILS OF INSTRUCTIONS
S1C33 FAMILY C33 PE CORE MANUAL
EPSON
107
ld.h [
%rb
],
%rs
Function
Signed halfword data transfer
Standard)
H[
rb
]
←
rs
(
15
:
0
)
Extension
1
) H[
rb
+
imm13
]
←
rs
(
15
:
0
)
Extension
2
) H[
rb
+
imm26
]
←
rs
(
15
:
0
)
Code
15
12
11
8
7
4
3
0
0
0
1
1
1
0
0
0
r b
r s
0x38__
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Flag
IE C V Z N
– – – – –
|
|
|
|
Mode
Src: Register direct
%rs
=
%r0
to
%r15
Dst: Register indirect
%rb
=
%r0
to
%r15
CLK
One cycle (two cycles when
ext
is used)
Description
(
1
) Standard
ld.h [
%rb
],
%rs
; memory address =
rb
The
16
low-order bits of the
rs
register are transferred to the specified memory location. The
rb
register contains the memory address to be accessed.
(
2
) Extension
1
ext
imm13
ld.h [
%rb
],
%rs
; memory address =
rb
+
imm13
The
e x t
instruction changes the addressing mode to register indirect addressing with
displacement. As a result, the
16
low-order bits of the
rs
register are transferred to the address
indicated by the content of the
rb
register with the
13
-bit immediate
imm13
added. The content
of the
rb
register is not altered.
(
3
) Extension
2
ext
imm13
; =
imm26
(25:13)
ext
imm13
; =
imm26
(12:0)
ld.h [
%rb
],
%rs
; memory address =
rb
+
imm26
The addressing mode changes to register indirect addressing with displacement, so the
16
low-
order bits of the
rs
register are transferred to the address indicated by the content of the
rb
register with the
26
-bit immediate
imm26
added. The content of the
rb
register is not altered.
Caution
The
rb
register and the displacement must specify a halfword boundary address (least significant bit
=
0
). Specifying an odd address causes an address misaligned exception.