Epson S1C31D50, Technical Instructions

Page: 112 / 472

7-25
Seiko Epson Corporation S1C31D50 TECHNICAL MANUAL
(Rev. 1.00)
7.7.12. PD Port Group
The PD port group consists of four ports PD0 – PD5 and two ports PD0 – PD1 are configured as
debugging function ports at initialization. These four ports support the GPIO function.
Table 7.7.12.1 Control Registers for Pd Port Group
Register name Bit Bit name Initial Reset R/W Remarks
PPORTPDDAT
(PD Port Data
Register)
15 – 14 – 0x0 – R –
13 – 8 PDOUT[5:0] 0x0 H0 R/W
7 – 6 – 0x0 – R
5 – 0 PDIN[5:0] x H0 R
PPORTPDIOEN
(PD Port Enable
Register)
15 – 14 – 0x0 – R –
13 – 8 PDIEN[5:0] 0x0 H0 R/W
7 – 4 – 0x0 – R
3 – 0 PDOEN[5:0] 0x0 H0 R/W
PPORTPDRCTL
(PD Port Pull-
up/down Control
Register)
15 – 14 – 0x0 – R –
13 – 8 PDPDPU[5:0] 0x0 H0 R/W
7 – 6 – 0x0 – R
5 – 0 PDREN[5:0] 0x0 H0 R/W
PPORTPDINTF
PPORTPDINTCTL
PPORTPDCHATEN
15 – 0 – 0x0000 – R –
PPORTPDMODSEL
(PD Port Mode
Select Register)
15 – 8 – 0x00 – R –
7 – 6 – 0x0 – R
5 – 0 PDSEL[5:0] 0x3 H0 R/W
PPORTPDFNCSEL
(PD Port Function
Select Register)
15 – 12 – 0x00 – R –
11 – 10 PD5MUX[1:0] 0x0 H0 R/W
9 – 8 PD4MUX[1:0] 0x0 H0 R/W
7 – 6 PD3MUX[1:0] 0x0 H0 R/W
5 – 4 PD2MUX[1:0] 0x0 H0 R/W
3 – 2 PD1MUX[1:0] 0x0 H0 R/W
1 – 0 PD0MUX[1:0] 0x0 H0 R/W
Table 7.7.12.2 Pd Port Group Function Assignment
Port
name
PdSEL y = 0 PDSEL y = 1
GPIO
PD y MUX = 0x0
(Function 0)
PD y MUX = 0x1
(Function 1)
PD y MUX = 0x2
(Function 2)
PD y MUX = 0x0
(Function 0)
Peripheral Pin Peripheral Peripheral Peripheral Pin Peripheral Pin
PD0 PD0 CPU core SWCLK – – – – – –
PD1 PD1 CPU core SWD – – – – – –
PD2 PD2 – – – – CLG OSC3 – –
PD3 PD3 – – – – CLG OSC4 – –
PD4 PD4 – – – – – – – –
PD5 PD5 – – – – – – – –