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RX8804CE

Page - 32

ETM59E-05

8.9. Reading / Writing Data via the I

2

C-Bus Interface

8.9.1. Overview of I

2

C-Bus

The I

2

C-Bus supports bi-directional communications via two signal lines: the SDA (data) line and SCL (clock) line. A

combination  of  these  two  signals  is  used  to  transmit  and  receive  communication  start/stop  signals,  data  transfer
signals, acknowledge signals, and so on.

Both the SCL and SDA signals are held at high level whenever communications are not being performed.
The starting and stopping of communications is controlled at the rising edge or falling edge of SDA while SCL is at
high level.

During data transfers, data changes that occur on the SDA line are performed while the SCL line is at low level, and
on the receiving side the data is output while the SCL line is at high level.
The I

2

C-Bus device does not include a chip select pin such as is found in ordinary logic devices. Instead of using a

chip select pin, slave addresses are allocated to each device and the receiving device responds to communications
only when its slave address matches the slave address in the received data. In either case, the data is transferred
via the SCL line at a rate of one bit per clock pulse.

8.9.2. System Configuration

All ports connected to the I

2

C-Bus must be either open drain or open collector ports in order to enable

“AND-

connections

” to multiple devices.

SCL and SDA are both connected to the V

DD

line via a pull-up resistance. Consequently, SCL and SDA are both

held at high level when the bus is released (when communication is not being performed).

Master

Transmitter

Receiver

Slave

Transmitter

Receiver

Other I

2

C-Bus device

CPU, etc.

RX8804CE

SDA

SCL

V

DD

Master

Transmitter

Receiver

Slave

Transmitter

Receiver

Figure 20 I

2

C-Bus Connection

Any device that controls the data transmission and data reception is defined as a

“Master”.

And any device that is controlled by a master device is defined as a

“Slave”.

The device transmitting data is defined as a

“Transmitter” and the device receiving data is defined as a “receiver”

In the case of this RTC module, controllers such as a CPU are defined as master devices and the RTC module is
defined as a slave device. When a device is used for both transmitting and receiving data, it is defined as either a
transmitter or receiver depending on these conditions.

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Summary of Contents for RX8804CE

Page 1: ...ETM59E 05 Preliminary Application Manual Real Time Clock Module RX8804CE ...

Page 2: ...general electronic applications and specifically designated applications Anticipated Purpose Epson products are NOT intended for any use beyond the Anticipated Purpose that requires particular quality or extremely high reliability in order to refrain from causing any malfunction or failure leading to critical harm to life and health serious property damage or severe impact on society including but...

Page 3: ...rking layout Frequency stability Mark and Lot Mark was updated 04 14 Jun 2018 16 40 5 RESET bit it explained detailed function of RESET 8 15 Figure of 32 kHz TCXO was updated SCL and SDA connects to GND 05 18 Sep 2020 1 Feature and Overview was updated 6 Table 6 Average Current consumption was added 10 Figure 6 Intertnal clock distribution diagram was added 17 8 3 SOUT Function Optimization of exp...

Page 4: ...Timing Chart of EVIN Time Stamping 20 8 4 3 INT pin Operation when an Interrupt Occurs 20 8 5 Alarm Interrupt Function 21 8 5 1 Alarm Interrupt Function 21 8 5 2 Alarm Interrupt Function Register 21 8 5 3 Examples of Alarm Settings 22 8 5 4 Alarm Interrupt Timing Chart 23 8 5 5 INT pin Operation when an Interrupt Occurs 24 8 6 Wakeup Timer Interrupt Function 24 8 6 1 Wakeup Timer Interrupt Functio...

Page 5: ...59E 05 8 14 When Used as a Clock Source 32 kHz TCXO 42 9 External Dimensions Marking Layout 43 9 1 RX8804CE 43 9 1 1 External Dimensions 43 9 1 2 Marking Layout 43 10 Application Notes 44 11 Figures 45 12 Tables 45 ...

Page 6: ...nA 3 0 V Typ Wide time keeping voltage range 1 5 V to 5 5 V Wide interface voltage range 1 6 V to 5 5 V SOUT can output self monitoring status voltage down etc SOUT can output programmed H L level also Time stamp function of Seconds from Year One time recorded by trigger of EVIN EVIN is equipped for time stamp trigger It has connectable pull up resistor Alarm interrupt function Combination of Day ...

Page 7: ...l this pin outputs a 32 768 kHz signal depend on FSEL bit When output is stopped the FOUT pin Hi Z high impedance FOE Input This is an input pin used to control the output mode of the FOUT pin When this pin s level is high the FOUT pin is in output mode When it is low output via the FOUT pin is stopped INT Output This pin is used to output alarm signals timer signals time update signals and other ...

Page 8: ...tem Symbol Condition Rating Unit Frequency stability f f XA Ta 0 to 50 C VDD 3 0 V Ta 40 to 85 C VDD 3 0 V Ta 85 to 105 C VDD 3 0 V 1 9 1 3 4 2 8 0 3 10 6 XB Ta 0 to 50 C VDD 3 0 V Ta 40 to 85 C VDD 3 0 V Ta 85 to 105 C VDD 3 0 V 3 8 4 5 0 5 8 0 3 Frequency voltage characteristics f V Ta 25 C VDD 1 5 V to 5 5 V 1 0 Max 10 6 V FOUT Symmetry SYM 50 VDD level 25 C VDD 1 5 V to 5 5 V 50 10 Oscillation...

Page 9: ...CL 0 Hz INT Hi Z FOUT is stopped Temp compensation is stopped VDD 5 V 0 38 1 55 Average Current consumption 8 IDD8 VDD 3 V 0 33 1 45 Peak Current consumption 1 IDD9 fSCL 0 Hz INT VDD FOUT is stopped Temp compensation ON peak VDD 5 V 55 100 Peak Current consumption 2 IDD10 VDD 3 V 50 95 High level input voltage VIH1 SCL SDA FOE 0 8 VDD 5 5 V VIH2 EVIN 0 8 VDD VDD Low level input voltage VIL SCL SDA...

Page 10: ...s Rise time for SCL and SDA tr 1 0 0 3 µs Fall time for SCL and SDA tf 0 3 0 3 µs Allowable spike time on bus tSP 50 50 ns Timing chart tHD DAT tSU DAT tHD STA tLOW tHIGH 1 fSCL tr tf tSU STA SDA SCL START CONDITION S BIT 7 MSB A7 BIT 6 A6 ACK A Protocol tBUF tSU STO STOP CONDITION P START CONDITION S P A tHD STA tSU STA S BIT 0 LSB R W S tSP Figure 3 I2 C Bus Timing Chart Note 1 As for the commun...

Page 11: ...compensation in 2 seconds cycle Figure 4 Temperature compensation current 7 3 2 IDD vs TC Characteristics for Reference Table 7 Average Current consumption IDD1 IDD2 Temp compensation interval TC Unit s IDD1 Typ VDD 5 0 V Unit µA IDD2 Typ VDD 3 0 V Unit µA 0 5 0 46 0 40 2 0 38 0 35 10 0 38 0 33 30 0 38 0 33 7 3 3 Reference characteristic of I2 C Bus active current Figure 5 I2 C Bus Current consump...

Page 12: ...1 0B Timer Counter 0 128 64 32 16 8 4 2 1 0C Timer Counter 1 32768 16384 8132 4096 2048 1024 512 256 0D Control1 TEST WADA USEL TE FSEL1 FSEL0 TSEL1 TSEL0 02h 0E Flag Register UF TF AF VLF VDET 00h 0F Control2 CSEL1 CSEL0 UIE TIE AIE RESET 40h Writing is avoided Read value is 0 always It can read and write is available avoid Init shows value of after power on Reset Unit is Hex Note Refer to Flag R...

Page 13: ...0h Writing is avoided Read value is 0 always It can read and write is available avoid Init shows value of after power on Reset Unit is Hex 8 1 4 Quick Reference Table 11 Quick Reference Update interrupt timing Default USEL 0 Once per seconds USEL 1 Once per minutes Output Frequency selection FSEL1 FSEL0 00 32 768 kHz FSEL1 FSEL0 01 1024 Hz FSEL1 FSEL0 10 1 Hz FSEL1 FSEL0 11 32 768 kHz Timer source...

Page 14: ...to 59 minutes after 59 it starts again from 00 minute 3 HOUR register This 24 hours register counts from 00 hour to 01 02 23 00 01 o indicates write protected bits Zero is always read from these bits 4 WEEK register This WEEK register consists of 7bit shift registers The data values are counted as follows Day 01h Day 02h Day 04h Day 08h Day 10h Day 20h Day 40h Day 01h Day 02h The correspondence be...

Page 15: ... 6 5 4 3 2 1 0 DAY Alarm 20 10 8 4 2 1 0D Control1 TEST WADA USEL TE FSEL1 FSEL0 TSEL1 TSEL0 0E Flag Register UF TF AF VLF VDET 0F Control2 CSEL1 CSEL0 UIE TIE AIE RESET The alarm interrupt function is used along with the AEI AF and WADA bits to set alarms for specified date day hour and minute values When the settings in the above alarm registers and the WADA bit match the current time the INT pi...

Page 16: ...EL1 CSEL0 UIE TIE AIE RESET Default 0 1 0 0 0 0 0 0 The default value is loaded after powering up from 0 V automatically TEST must be always cleared by a zero This register is used to specify the target for the alarm function or time update interrupt function and to select or set operations such as wakeup timer operations 1 TEST bit This is the manufacturer s test bit Its value should always be 0 ...

Page 17: ...xecutes reset of count down chain from 32 768kHz The detailed function of RESET For example S is start condition P is stop condition Write access to RESET bit S Slave address w ACK1 0Fh ACK2 01h ACK3 P RESET executes and it keeps between P from ACK3 After P RESET bit clears automatically reset area of circuit are the count down chain of 2 Hz from 16 kHz are cleared As for next update timing of a S...

Page 18: ...nd this flag bit s value changes from 0 to 1 when a time update interrupt event has occurred Once this flag bit s value is 1 its value is retained until a 0 is written to it Please refer to 8 7 Time Update Interrupt Function 12 AIE TIE UIE Alarm Wakeup Timer Update Interrupt Enable bit In case of Alarm or Wakeup Timer or Update occurs AIE TIE UIE bit controls INT output When a 1 is written to this...

Page 19: ...ersion of VDET VDET 0 1 0 1 VLF Inversion of VLF VLF 0 Other value than above combination Low 1 DC Selected Flag register value by FS2 1 0 is outputted at SOUT Output data is inversed by SRV bit Other FS2 1 0 combination makes SOUT low By this function RTC module inner status ex VLF is outputted to external controller device 8 2 6 Time Stamp Data Event Controller Register Table 29 Time Stamp Data ...

Page 20: ...ive High level 5 EPU bit Enable Pull up register EPU enables Pull up resistor of EVIN input terminal Table 32 EPU bit EPU Data Function Write Read 0 Pull up resistor is disabled 1 Pull up resistor is enabled 6 RCE bit Repeat Capture Enable RCE enables repeated times stamp capture Table 33 RCE bit RCE Data Function Write Read 0 After time stamp ECP bit is cleared to 0 automatically and Time stamp i...

Page 21: ...Even the EIE bit value is 0 another interrupt event may change the INT status to low or may hold INT L 1 In case of EVIN interrupt event interrupt signal is generated INT status changes from Hi Z to low There is no auto reset function like Wakeup timer interrupt and Update interrupt function INT low active signal is generated OR logic of Wakeup timer Alarm Update and EVIN interrupt 10 EVMON EVIN M...

Page 22: ... 0 0 0 0 STEP 2 operation Clearing VLF bit Retaining UF TF AF VDET bit Command Example WriteRX8804 0Eh 39h Target Address 0Eh 0 0 UF TF AF 0 VLF VDET Write Data 39h 0 0 1 1 1 0 0 1 STEP 3 operation VLF is outputted to SOUT pin as low active Command Example WriteRX8804 1Ah 0Dh Target Address 1Ah DCE DC 0 0 SRV FS2 FS1 FS0 Write Data 0Dh 0 0 0 0 1 1 0 1 STEP 4 operation Enabling SOUT function Comman...

Page 23: ... 19h 69h Target Address 19h SOE7 SOE6 SOE5 SOE4 SOE3 SOE2 SOE1 SOE0 Write Data 69h 0 1 1 0 1 0 0 1 STEP B operation Outputting High level at SOUT pin Command Example WriteRX8804 1Ah C0h Target Address 1Ah DCE DC 0 0 SRV FS2 FS1 FS0 Write Data C0h 1 1 0 0 0 0 0 0 STEP C operation Outputting High level at SOUT pin Command Example WriteRX8804 1Ah 80h Target Address 1Ah DCE DC 0 0 SRV FS2 FS1 FS0 Writ...

Page 24: ...her interrupts Command Example WriteRX8804 0Fh 40h Target Address 0Fh CSEL1 CSEL0 UIE TIE AIE 0 0 Reset Write Data 40h 0 1 0 0 0 0 0 STEP3 operation Clearing EF bit Command Example WriteRX8804 18h 00h Target Address 18h EF 0 0 0 EVMON 0 0 0 Write Data 00h 0 0 0 0 0 0 0 0 STEP4 operation Enabling EVIN interrupt Command Example WriteRX8804 17h A8h Target Address 17h ECP EHL EPU RCE EIE 0 ET1 ET0 Wri...

Page 25: ...iately changes from low to Hi Z After the EVIN interrupt occurs and during the EF bit value is 1 the INT status can be controlled via the EIE bit 6 If the EF bit value is changed from 1 to 0 while INT is low the INT status immediately changes from low to Hi Z 7 If the EIE bit value is 0 when an EVIN interrupt occurs the INT pin status remains Hi Z 8 4 3 INT pin Operation when an Interrupt Occurs 1...

Page 26: ...register In such cases be sure to write 0 to the AIE bit When the AIE bit value is 1 and the Alarm registers Reg 08h to 0Ah is being used as a RAM register INT may be changed to low level unintentionally 1 Alarm registers The minute hour day and date when an alarm interrupt event is set using this register and the WADA bit In the WEEK alarm Day alarm register Reg 0Ah the setting selected via the W...

Page 27: ...iption Write Read 0 1 When an alarm interrupt event occurs an interrupt signal is not generated or is canceled INT status remains Hi Z 2 When an alarm interrupt event occurs the interrupt signal is canceled INT status changes from low to Hi Z Even when the AIE bit value is 0 another interrupt event may change the INT status to low or may hold INT L 1 When an alarm interrupt event occurs an interru...

Page 28: ... the WADA bit Note Even if the current date time is used as the setting the alarm will not occur until the counter counts up to the current date time i e an alarm will occur next time not immediately 2 When a time update interrupt event occurs the AF bit values becomes 1 3 When the AF bit 1 its value is retained until it is cleared to zero 4 If AIE 1 when an alarm interrupt occurs the INT pin outp...

Page 29: ...Timer Function 8 6 2 Wakeup Timer Interruption Registers The wakeup timer interrupt generation function generates an interrupt event periodically at any wakeup set between 244 14 s and 16777215 minutes Table 44 Wakeup Timer Register Address Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Read Write 0B Timer Counter 0 128 64 32 16 8 4 2 1 0C Timer Counter 1 32768 16384 8192 4096 2048 1024 ...

Page 30: ... it is loaded with the first source clock of a timer counter after having set TE 5 Therefore two periods of source clocks are needed at the maximum till the first countdown starts after TE 1 Delay TE Period of Clock Source Clock TF is Set TF 3 2 1 Undefined Down Counter 3 3 Preset Value Load Preset Value Delay of the first countdown Preset value is 3 When timer count value is 0 from 1 preset value...

Page 31: ...up timer interrupt event occurs when the TF bit value changes from 0 to 1 this bit s value specifies whether an interrupt signal is generated INT status changes from Hi Z to low or is not generated INT status remains Hi Z Table 50 TIE bit TIE Data Description Write Read 0 1 When a wakeup timer interrupt event occurs an interrupt signal is not generated or is canceled INT status remains Hi Z 2 When...

Page 32: ...n 2048 500 00 ms 32 000 s 2048 s 2048 min 2560 625 00 ms 40 000 s 2560 s 2560 min 3200 0 7813 s 50 000 s 3200 s 3200 min 3840 0 9375 s 60 000 s 3840 s 3840 min 4095 0 9998 s 63 984 s 4095 s 4095 min 16777215 4096 s 3 days 49 min 4 s 194 days 32 years 8 3 5 Wakeup Timer Interrupt Timing Chart TIE bit INT output TF bit Event occurs TE bit tRTN tRTN tRTN period period period tRTN period 1 0 1 0 Hi Z ...

Page 33: ...p timer interrupt occurs INT pin output goes low If the TIE bit 0 when a wakeup timer interrupt occurs INT pin output remains Hi Z 6 Output from the INT pin remains low during the tRTN period following each event after which it is automatically cleared to Hi Z status INT is again set low when the next interrupt event occurs 7 When a 0 is written to the TE bit the wakeup timer function is stopped a...

Page 34: ... these bits Before entering settings for operations we recommend writing a 0 to the UIE bit to prevent hardware interrupts from occurring inadvertently while entering settings When the RESET bit value is 1 time update interrupt events do not occur Although the time update interrupt function cannot be fully stopped if 0 is written to the UIE bit the time update interrupt function can be prevented f...

Page 35: ...RTN tRTN tRTN period period period tRTN period 1 0 Hi Z L 1 0 INT status does not change when UF bit is cleared to zero Operation in RTC int operation Write operation 1 2 3 4 1 5 6 7 Figure 19 Update Interrupt Timing Chart 1 A time update interrupt event occurs when the internal clock s value matches either the second update time or the minute update time The USEL bit s specification determines wh...

Page 36: ...he supply voltage range VTEM 8 8 2 Related Registers for Temperature Compensation Function Table 56 Temperature Compensation Register Address Function bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0F Control 2 CSEL1 CSEL0 UIE TIE AIE RESET 1 CSEL1 CSEL0 Compensation Interval Select 1 0 bit This bit sets an interval of a temperature compensation operation Current consumption decreases when increa...

Page 37: ...s matches the slave address in the received data In either case the data is transferred via the SCL line at a rate of one bit per clock pulse 8 9 2 System Configuration All ports connected to the I2 C Bus must be either open drain or open collector ports in order to enable AND connections to multiple devices SCL and SDA are both connected to the VDD line via a pull up resistance Consequently SCL a...

Page 38: ...cibly stopped at any time while in progress However this is only when this RTC module is in receiver mode data reception mode SDA released 3 When communicating with this RTC module the series of operations from transmitting the START condition to transmitting the STOP condition should occur within 1 second A RESTART condition may be sent between a START condition and STOP condition but even in suc...

Page 39: ... low active each time an 8 bit data segment is received If there is no ACK signal from the receiver it indicates that normal communication has not been established This does not include instances where the master device intentionally does not generate an ACK signal Immediately after the falling edge of the clock pulse corresponding to the 8th bit of data on the SCL line the transmitter releases th...

Page 40: ...tion slave address R W specification The receiving device responds to this communication only when the specified slave address it has received matches its own slave address Slave addresses have a fixed length of 7 bits This RTC s slave address is 0110 010 An R W bit above is added to each 7 bit slave address during 8 bit transfers Table 58 I2 C Bus Slave Address Transfer data Slave address R W bit...

Page 41: ... 7 CPU transfers RX8804CE s slave address with the R W bit set to read mode 8 Check for ACK signal from RX8804CE from this point on the CPU is the receiver and the RX8804CE is the transmitter 9 Data from address specified at 4 above is output by the RX8804CE 10 CPU transfers ACK signal to RX8804CE 11 Repeat 9 and 10 if necessary Read addresses are automatically incremented 12 CPU transfers ACK sig...

Page 42: ... If such communication requires 2 seconds Max or longer the I2 C Bus interface is reset by the internal bus timeout function When bus time out occur SDA turns to Hi Z input mode readout data of a clock is stable anytime and there isn t contradiction And it does not occur that data of a clock delay even if access time is prolonged Table 59 VDD sequence characteristics Item symbol Condition Min Typ ...

Page 43: ...in to read VLF bit first If VLF bit returns 1 please initialize all registers Please perform initial setting only tSTA oscillation start time when the built in oscillation is stable Access is prohibited about 30 ms from the VCLK voltage VCLK clock supply voltage VDD 1 5 V If VLF bit returns 0 access is possible without waiting time Before the internal crystal oscillator has stabilized tSTA no cloc...

Page 44: ...a RAM register In such cases be sure to write 0 to the AIE bit Setting the Timer function Set the fixed cycle Timer function When the fixed cycle timer function is not being used the Timer Counter register can be used as a RAM register In such cases stop the fixed cycle timer function by writing 0 to the TE and TIE bits Cleart TE bit to 0 Clear TEST bit to 0 Setup FSEL1 0 bit optionally Setting th...

Page 45: ...on starts 0 writing of VLF is approved Start up complete power on Wait Wait time of 30 ms is necessary at least Whether it is a return from the state of the backup is confirmed VLF 1 YES YES NO Clear VLF to 0 Wait VLF 0 Software reset Initialize NO Please set waiting time depending on load of a system optionally Figure 28 Flow ex 2 ...

Page 46: ...t RESET to 1 Set RESET bit to 1 to prevent timer update in time setting Figure 29 Flow ex 3 4 The reading of the clock and calendar Next process Reading of the clock Read clock Please complete access within 1 second At the time of a communication start the Clock Calendar data are fixed hold the carry operation and it is automatically revised at the time of the communication end The access to a clo...

Page 47: ...iagram 8 14 When Used as a Clock Source 32 768 kHz DTCXO RX8804CE VDD T2 GND 0 1 F FOUT INT SCL SDA FOE VDD 32 768 kHz OE SOUT EVIN Figure 32 32 768 kHz DTCXO Connection RX8804CE I2 C Bus master MCU SCL SCL SDA SDA GND GND VDD VDD SCL SDA 0 1 µF R 2 kΩ to 10 kΩ VDD EVIN VDD VDD Sensor Module ...

Page 48: ...onnect or short circuit these pads In addition please avoid short circuit between these metal parts by dew condensation or particle adhesion Figure 33 Package Dimension 9 1 2 Marking Layout RX8804CE 1 Pin Mark Logo Production lot E8804X 123A Type XA X XB Y Frequency Stability Contents displayed indicate the general markings and display but are not the standards for the fonts sizes and positioning ...

Page 49: ... specification of pin exposition when it was specified N C or open by pin exposition 2 Notes on packaging 1 Soldering heat resistance If the temperature within the package exceeds 260 C the characteristics of the crystal oscillator will be degraded and it may be damaged The reflow conditions within our reflow profile is recommended Therefore always check the mounting temperature and time before mo...

Page 50: ...ackup sequence 38 Figure 27 Flow ex 1 39 Figure 28 Flow ex 2 40 Figure 29 Flow ex 3 41 Figure 30 Flow ex 4 41 Figure 31 Circuit Diagram 42 Figure 32 32 768 kHz DTCXO Connection 42 Figure 33 Package Dimension 43 Figure 34 Marking 43 Figure 35 Soldering Profile 44 12 Tables Table 1 Pin Functions 2 Table 2 Absolute Maximum Rating 3 Table 3 Recommended Operating Conditions 3 Table 4 Frequency Characte...

Page 51: ...x 1 22 Table 43 Alarm Setting ex 2 23 Table 43 Wakeup Timer Register 24 Table 45 TESL bit 25 Table 46 TSTP bit 25 Table 47 TRES bit 25 Table 48 TE bit 26 Table 49 TF bit 26 Table 50 TIE bit 26 Table 51 Wakeup Timer Interrupt Interval 27 Table 52 Update Interrupt Function Register 29 Table 53 USEL bit 29 Table 54 UF bit 29 Table 55 UIE bit 30 Table 56 Temperature Compensation Register 31 Table 57 C...

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