2 CROSS ASSEMBLER ASM6011
4
EPSON
E0C6011 DEVELOPMENT TOOL MANUAL
2 CROSS ASSEMBLER ASM6011
2.1 ASM6011 Outline
The ASM6011 cross assembler is an assembler program
for generating the machine code used by the E0C6011 4-
bit, single-chip microcomputers. The Cross Assembler
ASM6011 will assemble the program source files which
have been input by the user's editor and will generate
an object file in Intel-Hex format and assembly list file.
In this assembler, program modularization has been
made possible through macro definition functions and
programming independent of the ROM page structure
has been made possible through the auto page set
function. In addition, consideration has also been given
to precise error checks for program capacity (ROM
capacity) overflows, undefined codes and the like, and
for debugging of such things as label tables for assembly
list files and cross reference table supplements.
2.2 E0C6011 Restrictions
Note the following when generating a program by the E0C6011:
Fig. 2.1.1 ASM6011 execution flow
☞
The format of the source file and its operating method are same as for the E0C62 Family. Refer to the
"E0C62 Family Development Tool Reference Manual" for details.
■
ROM area
The capacity of the E0C6011
ROM is 1,536 steps (0000H to
05FFH).
Therefore, the specification
range of the memory setting
pseudo-instructions and PSET
instruction is restricted.
Memory configuration:
Bank: Only bank 0, Page: 6 pages (0 to 5H), each 256 steps
Significant specification range:
ORG
pseudo-instruction:
0000H to 05FFH
PAGE pseudo-instruction:
00H to 05H
BANK pseudo-instruction:
Only 0H
PSET
instruction:
00H to 05H
A>EDLIN C011XXX.DAT
Create the source file
A>ASM6011 C011XXX
Execute the cross assembler
C011XXX
.DAT
C011XXX
.PRN
C011XXXL
.HEX
C011XXXH
.HEX
Error
message
Error
message
Assembly
listing file
Object file
■
RAM area
The capacity of the E0C6011 RAM
is 144 words (000H to 06FH, 080H
to 09FH, 4 bits/word). Memory
access is invalid when the unused
area of the index register is
specified.
Example:
LD
X,0A0H
A0H is loaded into the IX register, but an
unused area has been specified so that the
memory accessible with the IX register
(MX) is invalid.
LD
Y,0B7H
B7H is loaded into the IY register, but an
unused area has been specified so that the
memory accessible with the IY register
(MY) is invalid.
■
Undefined codes
The following instructions have not
been defined in the E0C6011
instruction sets.
PUSH
XP
PUSH
YP
POP
XP
POP
YP
LD
XP,r
LD
YP,r
LD
r,XP
LD
r,YP
