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CHAPTER 4: PERIPHERAL CIRCUITS AND OPERATION (Output Port)

I-29

Special output port data (0F3H D0)

Controls the FOUT (clock) output.

When 1 is written: Clock output

When 0 is written: Low level (DC) output

Reading:

Valid

FOUT output can be controlled by writing data to R00. After

an initial reset, this register is set to 0.

Figure 4.4.3 shows the output waveform for FOUT output.

R00 (when FOUT is

selected)

Fig. 4.4.3

FOUT output waveform

FOUT frequency control (0FDH D0, 0FDH D1)

Selects the output frequency when R00 port is set for FOUT

output.

XFOUT0, XFOUT1

Table 4.4.4

FOUT frequency selection

After an initial reset, these registers are set to 0.

XFOUT1

XFOUT0

Frequency Selection

R00 register

FOUT output
waveform

Summary of Contents for E0C6001

Page 1: ...MF943 02 CMOS 4 BIT SINGLE CHIP MICROCOMPUTER E0C6001 TECHNICAL MANUAL E0C6001 Technical Hardware E0C6001 Technical Software ...

Page 2: ...license to any intellectual property rights is granted by implication or otherwise and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party This material or portions thereof may contain technology or the subject relating to strategic products under the control of the Foreign Exchange and F...

Page 3: ...he software of the E0C6001 I E0C6001 Technical Hardware This part explains the function of the E0C6001 the circuit configura tions and details the controlling method II E0C6001 Technical Software This part explains the programming method of the E0C6001 Hardware Software ...

Page 4: ...Hardware E0C6001 I Technical Hardware ...

Page 5: ...escription I 5 CHAPTER 2 POWER SUPPLY AND INITIAL RESET I 6 2 1 Power Supply I 6 2 2 Initial Reset I 8 Oscillation detection circuit I 9 Reset pin RESET I 9 Simultaneous high input to input ports K00 K03 I 9 Internal register following initialization I 10 2 3 Test Pin TEST I 10 CHAPTER 3 CPU ROM RAM I 11 3 1 CPU I 11 3 2 ROM I 12 3 3 RAM I 12 ...

Page 6: ...utput port I 28 4 5 I O Port P00 P03 I 31 Configuration of I O port I 31 I O control register and I O mode I 32 Mask option I 32 Control of I O port I 33 4 6 LCD Driver COM0 COM3 SEG0 SEG19 I 35 Configuration of LCD driver I 35 Cadence adjustment of oscillation frequency I 41 Mask option segment allocation I 42 Control of LCD driver I 44 4 7 Clock Timer I 45 Configuration of clock timer I 45 Inter...

Page 7: ...6 ELECTRICAL CHARACTERISTICS I 58 6 1 Absolute Maximum Rating I 58 6 2 Recommended Operating Conditions I 59 6 3 DC Characteristics I 60 6 4 Analog Circuit Characteristics and Power Current Consumption I 62 6 5 Oscillation Characteristics I 66 CHAPTER 7 PACKAGE I 68 7 1 Plastic Package I 68 7 2 Ceramic Package for Test Samples I 69 CHAPTER 8 PAD LAYOUT I 70 8 1 Diagram of Pad Layout I 70 8 2 Pad C...

Page 8: ...0 R01 one 4 bit I O port P00 P03 and one timer clock timer Because of their low voltage operation and low power con sumption the E0C6001 Series are ideal for a wide range of applications Configuration The E0C6001 Series are configured as follows depending on the supply voltage CHAPTER 1 1 1 Table 1 1 1 Configuration of the E0C6001 Series Model Supply Voltage Oscillation Circuits 3 0 V 1 5 V E0C600...

Page 9: ...common duty 1 system clock timer Input port interrupt 1 system Timer interrupt 1 system 1 5 V 1 2 2 0 V E0C60L01 3 0 V 1 8 3 6 V E0C6001 1 0 µA Crystal oscillation CLK 32 768 kHz when halted 2 5 µA Crystal oscillation CLK 32 768 kHz when executing QFP12 48pin plastic or chip 1 2 Built in oscillation circuit Instruction set ROM capacity RAM capacity data RAM Input port Output port Input output port...

Page 10: ... LCD Driver RAM 80 4 Interrupt Generator I Port Test Port I O Port O Port Timer Core CPU E0C6200B ROM 1 024 12 OSC System Reset Control RESET OSC1 COM0 COM3 SEG0 SEG19 VDD VL1 VL3 CA CB VS1 VSS K00 K03 TEST P00 P03 R00 R01 OSC2 FOUT BUZZER FOUT BUZZER BUZZER Block Diagram ...

Page 11: ...18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 25 26 27 28 29 30 31 32 33 34 35 36 TEST RESET SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 37 38 39 40 41 42 43 44 45 46 47 48 COM0 COM1 COM2 COM3 VL3 VL2 VL1 CA CB VSS VDD OSC1 Pin No Pin Name Pin No Pin Name Pin No Pin No Pin Name Pin Name Fig 1 4 1 Pin assignment QFP12 48pin 25 36 13 24 INDEX 12 1 48 37 Pin Layout Diagram ...

Page 12: ... terminal LCD system reducer output terminal VL2 1 2 LCD system reducer output terminal VL3 1 3 LCD system booster output terminal VL1 2 LCD system reducer output terminal VL3 2 3 LCD system booster output terminal VL1 3 LCD system booster output terminal VL2 3 2 Booster capacitor connecting terminal Crystal or CR oscillation input terminal Crystal or CR oscillation output terminal Input terminal ...

Page 13: ...ltage booster reducer generates VL1 and VL3 When 3 0 V LCD panel is selected the E0C6001 short circuits between VL3 and VSS and the voltage reducer generates VL1 and VL2 The E0C60L01 short circuits between VL1 and VSS and the voltage booster generates VL2 and VL3 The voltage VS1 for the internal circuit that is generated by the regulated voltage circuit is 1 2 V VDD standard Figure 2 1 1 shows the...

Page 14: ...2 bias E0C60L01 4 5 V LCD panel 3 V LCD panel 1 4 1 3 1 2 duty 1 3 bias 1 4 1 3 1 2 duty 1 2 bias Note VL1 is shorted to VSS inside the IC Fig 2 1 1 External element configuration of power system Note VL3 is shorted to VSS inside the IC VDD VS1 VL1 VL2 VL3 CA CB VSS 3 V VDD VS1 VL1 VL2 VL3 CA CB VSS 3 V VDD VS1 VL1 VL2 VL3 CA CB VSS 3 V VDD VS1 VL1 VL2 VL3 CA CB VSS 1 5 V VDD VS1 VL1 VL2 VL3 CA CB...

Page 15: ...ut to pins K00 K03 depending on mask option Figure 2 2 1 shows the configuration of the initial reset circuit Fig 2 2 1 Configuration of initial reset circuit 2 2 Vss RESET K03 K02 K01 K00 OSC2 OSC1 OSC1 Oscillation circuit Vss Oscillation detection circuit Noise rejection circuit Initial reset Noise rejection circuit Note Be sure to use reset function 2 or 3 at power on because the initial reset ...

Page 16: ...goes low the CPU begins to operate Another way of invoking an initial reset externally is to input a high signal simultaneously to the input ports K00 K03 selected with the mask option The specified input port pins must be kept high for at least 4 sec when oscillating fre quency fosc 32 kHz because of the noise rejection circuit Table 2 2 1 shows the combinations of input ports K00 K03 that can be...

Page 17: ...r A General register B Interrupt flag Decimal flag Zero flag Carry flag Signal PCS PCP NPP SP X Y RP A B I D Z C Number of Bits 8 4 4 8 8 8 4 4 4 1 1 1 1 Setting Value 00H 1H 1H Undefined Undefined Undefined Undefined Undefined Undefined 0 0 Undefined Undefined Peripheral Circuits Name RAM Display memory Other peripheral circuit Number of Bits 80 4 20 4 Setting Value Undefined Undefined 1 1 See se...

Page 18: ...anual for details of the E0C6200B Note the following points with regard to the E0C6001 Series 1 The SLEEP operation is not provided so the SLP instruc tion cannot be used 2 Because the ROM capacity is 1 024 words 12 bits per word bank bits are unnecessary and PCB and NBP are not used 3 The RAM page is set to 0 only so the page part XP YP of the index register that specifies addresses is invalid PU...

Page 19: ...ry for storing a variety of data has a capacity of 80 words 4 bit words When programming keep the following points in mind 1 Part of the data memory is used as stack area when saving subroutine return addresses and registers so be careful not to overlap the data area and stack area 2 Subroutine calls and interrupts take up three words on the stack 3 Data memory 000H 00FH is the memory area pointed...

Page 20: ...13 words to I O memory Figure 4 1 1 show the overall memory map for the E0C6001 Series and Tables 4 1 1 a d the memory maps for the peripheral circuits I O space 4 1 Unused area Fig 4 1 1 Memory map Note Memory is not mounted in unused area within the memory map and in memory area not indicated in this chapter For this reason normal operation cannot be assured for programs that have been prepared ...

Page 21: ...EIK01 EIK00 0 0 0 0 Enable Enable Enable Enable Mask Mask Mask Mask Timer data clock timer 2 Hz Timer data clock timer 4 Hz Timer data clock timer 8 Hz Timer data clock timer 16 Hz Input port K00 K03 High High High High Low Low Low Low Interrupt mask register K03 Interrupt mask register K02 Interrupt mask register K01 Interrupt mask register K00 High High High High Low Low Low Low 2 2 2 2 0 EIT2 E...

Page 22: ...0 0 0 IK0 0 0 IT2 IT8 IT32 0 0 0 Yes Yes Yes Interrupt factor flag K00 K03 Interrupt factor flag clock timer 2 Hz Interrupt factor flag clock timer 8 Hz Interrupt factor flag clock timer 32 Hz Yes No R R 5 5 5 4 0F6H P03 P02 P01 P00 P03 P02 P01 P00 I O port P00 P03 High High High High Low Low Low Low 2 2 2 2 R W 5 4 4 4 5 5 No No No 0F3H 0 0 R01 R00 0 0 R01 BUZZER R00 FOUT 0 0 0 0 High ON High ON ...

Page 23: ...ead 6 Refer to main manual Address Comment Register D3 D2 D1 D0 Name SR 1 1 0 0F9H 0FAH 0 TMRST 0 0 HLMOD 0 0 0 W 0 TMRST 0 0 Reset HLMOD 0 0 0 0 Clock timer reset Heavy load protection mode register Reset R R R R W Heavy load Normal load 5 5 5 0FBH 0FCH CSDC 0 0 0 0 0 0 IOC R R 0 0 0 0 IOC 0 I O port P00 P03 Input Output LCD drive switch Static Dynamic Output Input 5 5 5 5 5 5 R W R W CSDC 0 0 0 ...

Page 24: ... Reset 0 immediately after being read 5 Constantly 0 when being read 6 Refer to main manual Address Comment Register D3 D2 D1 D0 Name SR 1 1 0 0FDH XBZR 0 XFOUT1 XFOUT0 R XBZR 0 XFOUT1 XFOUT0 0 0 0 Buzzer frequency control 2 kHz High High 4 kHz Low Low R W R W 5 FOUT frequency control XFOUT1 0 XFOUT0 0 F1 XFOUT1 0 XFOUT0 1 F2 XFOUT1 1 XFOUT0 0 F3 XFOUT1 1 XFOUT0 1 F4 ...

Page 25: ...e block diagram of the crystal oscillation circuit 4 2 Fig 4 2 1 Crystal oscillation circuit Crystal oscillation circuit As Figure 4 2 1 indicates the crystal oscillation circuit can be configured simply by connecting the crystal oscillator X tal between the OSC1 and OSC2 pins and the trimmer capacitor CG between the OSC1 and VDD pins CG X tal OSC2 OSC1 To CPU and peripheral circuits The E0C6001 S...

Page 26: ...ption Figure 4 2 2 is the block diagram of the CR oscillation circuit Fig 4 2 2 CR oscillation circuit As Figure 4 2 2 indicates the CR oscillation circuit can be configured simply by connecting the register R between pins OSC1 and OSC2 since capacity C is built in See Chapter 6 ELECTRICAL CHARACTERISTICS for R value OSC2 OSC1 C To CPU and peripheral circuits The E0C6001 Series R ...

Page 27: ...n key matrix and so forth When pull down resistance disabled is selected the port can be used for slide switch input and interfacing with other LSIs 4 3 Configuration of input port Fig 4 3 1 Configuration of input port All four input port bits K00 K03 provide the interrupt function The conditions for issuing an interrupt can be set by the software for the four bits Also whether to mask the interru...

Page 28: ...When using an input interrupt if you rewrite the content of the mask register when the value of the input terminal which becomes the interrupt input is in the active status input terminal high status the factor flag for input interrupt may be set For example a factor flag is set with the timing of shown in Figure 4 3 3 However when clearing the content of the mask register with the input terminal ...

Page 29: ...ows 1 An internal pull down resistance can be selected for each of the four bits of the input ports K00 K03 Having selected pull down resistance disabled take care that the input does not float Select pull down resistance enabled for input ports that are not being used 2 The input interrupt circuit contains a noise rejection circuit to prevent interrupts form occurring through noise The mask optio...

Page 30: ... 0 0 0 0 Interrupt mask register K03 Interrupt mask register K02 Interrupt mask register K01 Interrupt mask register K00 Enable Enable Enable Enable Mask Mask Mask Mask 0EDH 0 0 IK0 R 0 0 0 IK0 0 Interrupt factor flag K00 K03 Yes No 0 K00 K03 Input port data 0E0H The input data of the input port pins can be read with these registers When 1 is read High level When 0 is read Low level Writing Invali...

Page 31: ... 1 is read Interrupt has occurred When 0 is read Interrupt has not occurred Writing Invalid The interrupt factor flag IK0 is associated with K00 K03 From the status of this flag the software can decide whether an input interrupt has occurred This flag is reset when the software has read it Reading of interrupt factor flag is available at EI but be careful in the following cases If the interrupt ma...

Page 32: ...th the mask option Two kinds of output specifi cations are available complementary output and Pch open drain output Also the mask option enables the output ports R00 and R01 to be used as special output ports Figure 4 4 1 shows the configuration of the output port Configuration of output port 4 4 Fig 4 4 1 Configuration of output port Register Data bus Address VDD VSS Rxx Complementary Pch open dr...

Page 33: ...ed a voltage exceeding the source voltage must not be applied to the output port 2 Special output In addition to the regular DC output special output can be selected for output ports R00 and R01 as shown in Table 4 4 1 Figure 4 4 2 shows the structure of output ports R00 and R01 Mask option Table 4 4 1 Special output FOUT or BUZZER BUZZER R00 R01 Pin Name When Special Output is Selected Fig 4 4 2 ...

Page 34: ...s set to BUZZER output In such case whether ON OFF of the BUZZER output is done through R00 register or is con trolled through R01 simultaneously with BUZZER output is also selected by mask option The frequency of buzzer output may be selected by software to be either 2 kHz or 4 kHz Table 4 4 2 FOUT clock frequency A hazard may occur when the FOUT signal is turned on or off Note D1 D0 XFOUT1 XFOUT...

Page 35: ...sters are set to 0 R00 R01 Table 4 4 3 lists the output port control bits and their ad dresses Table 4 4 3 Control bits of output port Control of output port Address Comment Register D3 D2 D1 D0 Name SR 1 0 0F3H 0 0 R01 R00 0 0 R01 BUZZER R00 FOUT 0 0 0 0 High ON High ON Low OFF Low OFF R01 output port data Buzzer ON OFF control register R00 output port data Frequency output ON OFF control registe...

Page 36: ...er an initial reset this register is set to 0 Figure 4 4 3 shows the output waveform for FOUT output R00 when FOUT is selected Fig 4 4 3 FOUT output waveform FOUT frequency control 0FDH D0 0FDH D1 Selects the output frequency when R00 port is set for FOUT output XFOUT0 XFOUT1 Table 4 4 4 FOUT frequency selection After an initial reset these registers are set to 0 0 0 1 1 XFOUT1 0 1 0 1 XFOUT0 F1 F...

Page 37: ...al reset these registers are set to 0 Figure 4 4 4 shows the output waveform for buzzer output R00 R01 when BUZZER and BUZZER is selected Fig 4 4 4 Buzzer output waveform Buzzer frequency control 0FDH D3 Selects the frequency of the buzzer signal When 1 is written 2 kHz When 0 is written 4 kHz Reading Valid When R00 and R01 port is set to buzzer output the fre quency of the buzzer signal can be se...

Page 38: ...5 1 shows the configuration of the I O port The four bits of the I O port P00 P03 can be set to either input mode or output mode The mode can be set by writing data to the I O control register IOC 4 5 Configuration of I O port Fig 4 5 1 Configuration of I O port Address Address Register Input control I O control register IOC Data bus Pxx Vss ...

Page 39: ...n I O port set to output mode works as an output port it outputs a high signal VDD when the port output data is 1 and a low signal VSS when the port output data is 0 After an initial reset the I O control register is set to 0 and the I O port enters the input mode The output specification during output mode IOC 1 of the I O port can be set with the mask option for either comple mentary output or P...

Page 40: ...n an I O port is set to the output mode the written data is output from the I O port pin unchanged When 1 is written as the port data the port pin goes high VDD and when 0 is written the level goes low VSS Port data can also be written in the input mode When reading data When 1 is read High level When 0 is read Low level P00 P03 Address Comment Register D3 D2 D1 D0 Name SR 1 0 0F6H P03 P02 P01 P00...

Page 41: ...onstant of the capacitive load of the input line and the built in pull down resistance load is greater than the read out time When the input data is being read the time that the input line is pulled down is equivalent to 0 5 cycles of the CPU system clock Hence the electric poten tial of the pins must settle within 0 5 cycles If this condition cannot be met some measure must be devised such as arr...

Page 42: ...he mask option drive duty can also be selected from 1 4 1 3 or 1 2 1 2 bias drive is effective when the LCD system regulated voltage circuit is not used The VL1 terminal and the VL2 terminal should be connected outside of the IC The frame frequency is 32 Hz for 1 4 duty and 1 2 duty and 42 7 Hz for 1 3 duty in the case of fosc 32 768 kHz Figure 4 6 1 shows the drive waveform for 1 4 duty 1 3 bias ...

Page 43: ... TECHNICAL HARDWARE I 36 Fig 4 6 1 Drive waveform for 1 4 duty 1 3 bias LCD lighting status COM0 COM1 COM2 COM3 Not lit Lit VDD VL1 VL2 VL3 COM0 COM1 COM2 COM3 SEG 0 19 Frame frequency SEG0 19 VDD VL1 VL2 VL3 ...

Page 44: ...AL CIRCUITS AND OPERATION LCD Driver I 37 Fig 4 6 2 Drive waveform for 1 3 duty 1 3 bias Frame frequency SEG 0 19 COM3 COM2 COM1 COM0 VDD VL1 VL2 VL3 Not lit Lit SEG0 19 LCD lighting status COM0 COM1 COM2 VDD VL1 VL2 VL3 ...

Page 45: ...C6001 TECHNICAL HARDWARE I 38 Fig 4 6 3 Drive waveform for 1 2 duty 1 3 bias COM0 COM1 COM2 COM3 SEG 0 19 Frame frequency VDD VL1 VL2 VL3 VDD VL1 VL2 VL3 Not lit Lit SEG0 19 LCD lighting status COM0 COM1 ...

Page 46: ... CIRCUITS AND OPERATION LCD Driver I 39 LCD lighting status Not lit Lit SEG 0 19 SEG0 19 Frame frequency COM0 COM1 COM2 COM3 COM0 COM1 COM2 COM3 VDD VL1 L2 VL3 VDD VL1 L2 VL3 Fig 4 6 4 Drive waveform for 1 4 duty 1 2 bias ...

Page 47: ...SEG0 19 COM0 COM1 COM2 COM0 COM1 COM2 COM3 VDD VL1 L2 VL3 VDD VL1 L2 VL3 COM0 COM1 COM0 COM1 COM2 COM3 VDD VL1 L2 VL3 VDD VL1 L2 VL3 LCD lighting status Not lit Lit SEG 0 19 Frame frequency SEG0 19 Fig 4 6 5 Drive waveform for 1 3 duty 1 2 bias Fig 4 6 6 Drive waveform for 1 2 duty 1 2 bias ...

Page 48: ...he mask option the display data corresponding to all COM are valid during 1 1 duty driving Hence for 1 1 duty drive set the same value for all display memory corresponding to COMs 0 through 3 For cadence adjustment set the display data corresponding to COMs 0 through 3 so that all the LCD segments go on Figure 4 6 7 shows the 1 1 duty drive waveform 1 3 bias Figure 4 6 8 shows the 1 1 duty drive w...

Page 49: ...ree of freedom with which the liquid crystal panel can be designed Figure 4 6 9 shows an example of the relationship be tween the LCD segments on the panel and the display memory in the case of 1 3 duty Mask option segment allocation Fig 4 6 9 Segment allocation a a f f g g e e d d p p c b b c SEG10 SEG11 SEG12 Common 0 Common 1 Common 2 09AH 09BH 09CH 09DH Address d p d p D3 c g c g D2 b f b f D1...

Page 50: ...ation The segment pins SEG0 SEG19 are selected by mask option in pairs for either segment signal output or DC output VDD and VSS binary output When DC output is selected the data corresponding to COM0 of each segment pin is output When DC output is selected either complementary output or Pch open drain output can be selected for each pin by mask option The pin pairs are the combination of SEG 2 n ...

Page 51: ...an be selected with this switch When 1 is written Static drive When 0 is written Dynamic drive Reading Valid After an initial reset dynamic drive CSDC 0 is selected 090H 0AFH The LCD segments are turned on or off according to this data When 1 is written On When 0 is written Off Reading Invalid By writing data into the display memory allocated to the LCD segment on the panel the segment can be turn...

Page 52: ...rce clock from the dividing circuit The four high order bits 16 Hz 2 Hz can be read by the soft ware Figure 4 7 1 is the block diagram of the clock timer 4 7 Configuration of clock timer Normally this clock timer is used for all kinds of timing purpose such as clocks Fig 4 7 1 Block diagram of clock timer 128 Hz 32 Hz Data bus 32 Hz 8 Hz 2 Hz 256 Hz Clock timer reset signal OSC oscillation circuit...

Page 53: ...nerated on the falling edge of the 32 Hz 8 Hz and 2 Hz frequencies When this happens the corresponding interrupt event flag IT32 IT8 IT2 is set to 1 Masking the separate interrupts can be done with the interrupt mask register EIT32 EIT8 EIT2 However regardless of the interrupt mask register setting the interrupt event flags will be set to 1 on the falling edge of their corresponding signal e g the...

Page 54: ...me SR 1 0 0E4H TM3 TM2 TM1 TM0 R TM3 TM2 TM1 TM0 Timer data clock timer 2 Hz Timer data clock timer 4 Hz Timer data clock timer 8 Hz Timer data clock timer 16 Hz High High High High Low Low Low Low 0EBH 0 EIT2 EIT8 EIT32 R 0 EIT2 EIT8 EIT32 0 0 0 Enable Enable Enable Mask Mask Mask Interrupt mask register clock timer 2 Hz Interrupt mask register clock timer 8 Hz Interrupt mask register clock timer...

Page 55: ...interrupt However even if the interrupt is masked the flags are set to 1 on the falling edge of the signal These flags can be reset when the register is read by the software Reading of interrupt factor flags is available at EI but be careful in the following cases If the interrupt mask register value corresponding to the interrupt factor flags to be read is set to 1 an interrupt request will be ge...

Page 56: ...load protection mode The normal mode changes to the heavy load protection mode in the following case When the software changes the mode to the heavy load protection mode HLMOD 1 In the heavy load protection mode the internally regulated voltage is switched to the high stability mode from the low current consumption mode Consequently more current is consumed in the heavy load protection mode than i...

Page 57: ... 1 is written Heavy load protection mode on When 0 is written Heavy load protection mode off Reading Valid When HLMOD is set to 1 the IC enters the heavy load protection mode In the heavy load protection mode the consumed current becomes larger Unless necessary do not select the heavy load protection mode with the software HLMOD Address Comment Register D3 D2 D1 D0 Name SR 1 0 0FAH HLMOD 0 0 0 HLM...

Page 58: ...ts the interrupt flag must be set to 1 EI and the necessary related interrupt mask registers must be set to 1 enable When an interrupt occurs the interrupt flag is automatically reset to 0 DI and interrupts after that are inhibited When a HALT instruction is input the CPU operating clock stops and the CPU enters the halt state The CPU is reacti vated from the halt state when an interrupt request o...

Page 59: ...ation of interrupt circuit K00 EIK00 K01 EIK01 K02 EIK02 K03 EIK03 IT2 EIT2 IT8 EIT8 IT32 EIT32 IK0 MSB LSB Program counter of CPU three low order bits Interrupt vector Interrupt factor flag Interrupt mask register Interrupt flag INT Interrupt request ...

Page 60: ...n initial reset the interrupt factor flags are reset to 0 Interrupt factors Reading of interrupt factor flags is available at EI but be careful in the following cases If the interrupt mask register value corresponding to the interrupt factor flags to be read is set to 1 an interrupt request will be generated by the interrupt factor flags set timing or an interrupt request will not be generated Be ...

Page 61: ...clock Interrupt vectors Note The interrupt factor flags can be masked by the correspond ing interrupt mask registers The interrupt mask registers are read write registers They are enabled interrupt en abled when 1 is written to them and masked interrupt disabled when 0 is written to them After an initial reset the interrupt mask register is set to 0 Table 4 9 2 shows the correspondence between int...

Page 62: ...errupt mask register K00 Enable Enable Enable Enable Mask Mask Mask Mask Interrupt mask register clock timer 2 Hz Interrupt mask register clock timer 8 Hz Interrupt mask register clock timer 32 Hz R W 0EDH 0 0 IK0 0 0 0 IK0 0 Interrupt factor flag K00 K03 Yes No 0 0EFH 0 IT2 IT8 IT32 0 IT2 IT8 IT32 0 0 0 Enable Enable Enable Mask Mask Mask Interrupt factor flag clock timer 2 Hz Interrupt factor fl...

Page 63: ...lator Trimmer capacitor Capacitor Capacitor 32 768 kHz CI MAX 35 kΩ 5 25 pF 0 1 µF 3 3 µF C1 CG C5 X tal 1 5 V or 3 0 V Piezo Buzzer R01 K00 K03 P00 P03 R00 I I O O SEG0 SEG19 COM0 COM3 LCD PANEL Coil CA CB VL1 VL2 VL3 VDD OSC1 OSC2 VS1 RESET TEST VSS Cp Connection depending on power supply and LCD panel specification Please refer to page I 7 ...

Page 64: ...PANEL CA CB VL1 VL2 VL3 VDD OSC1 OSC2 VS1 RESET TEST VSS Cp 1 5 V or 3 0 V Piezo Buzzer R01 R00 K00 K03 P00 P03 Connection depending on power supply and LCD panel specification Please refer to page I 7 X tal CG C1 C5 Cp Crystal oscillator Trimmer capacitor Capacitor Capacitor 32 768 kHz CI MAX 35 kΩ 5 25 pF 0 1 µF 3 3 µF ...

Page 65: ... Soldering temperature Time Allowable dissipation 2 VSS VI VIOSC IVSS Topr Tstg Tsol PD 5 0 to 0 5 Vss 0 3 to 0 5 Vss 0 3 to 0 5 10 20 to 70 65 to 150 260 C 10sec lead section 250 V V V mA C C mW VDD 0V Item Symbol Rated Value Unit 1 The permissible total output current is the sum total of the current average current that simultaneously flows from the output pins or is draw in 2 In case of QFP12 4...

Page 66: ...V Crystal oscillation CR oscillation R 470kΩ Min 3 6 50 0 1 0 1 0 1 0 1 0 1 Typ 3 0 32 768 65 Unit V kHz kHz µF µF µF µF µF Max 1 8 80 Ta 20 to 70 C Item Power voltage Oscillation frequency Booster capacitor Capacitor between VDD and VL1 Capacitor between VDD and VL2 Capacitor between VDD and VL3 Capacitor between VDD and VS1 Symbol VSS fOSC1 fOSC2 C1 C2 C3 C4 C5 Condition VDD 0V Crystal oscillati...

Page 67: ...ST P00 P03 R00 R01 P00 P03 R00 R01 COM0 COM3 SEG0 SEG19 SEG0 SEG19 High level input voltage 1 High level input voltage 2 Low level input voltage 1 Low level input voltage 2 High level input current 1 High level input current 2 High level input current 3 Low level input current High level output current 1 High level output current 2 Low level output current 1 Low level output current 2 Common outpu...

Page 68: ...0 P03 R00 R01 P00 P03 R00 R01 COM0 COM3 SEG0 SEG19 SEG0 SEG19 High level input voltage 1 High level input voltage 2 Low level input voltage 1 Low level input voltage 2 High level input current 1 High level input current 2 High level input current 3 Low level input current High level output current 1 High level output current 2 Low level output current 1 Low level output current 2 Common output cur...

Page 69: ...dition Connect 1MΩ load resistor between VDD and VL1 without panel load Connect 1MΩ load resistor between VDD and VL2 without panel load Connect 1MΩ load resistor between VDD and VL3 without panel load Min 1 2 VL2 0 1 3 2 VL2 0 1 Typ VSS 1 0 2 5 Unit V V V µA µA Max 1 2 VL2 0 9 3 2 VL2 0 9 2 5 5 0 During HALT During execution Without panel load Item Internal voltage Power current consumption Symbo...

Page 70: ...load resistor between VDD and VL1 without panel load Connect 1MΩ load resistor between VDD and VL2 without panel load Connect 1MΩ load resistor between VDD and VL3 without panel load Min 2 VL1 0 1 3 VL1 0 1 Typ VSS 1 0 2 5 Unit V V V µA µA Max 2 VL1 0 9 3 VL1 0 9 2 5 5 0 During HALT During execution Without panel load Item Internal voltage Power current consumption Symbol VL1 VL2 VL3 IOP Condition...

Page 71: ...ndition Connect 1MΩ load resistor between VDD and VL1 without panel load Connect 1MΩ load resistor between VDD and VL2 without panel load Connect 1MΩ load resistor between VDD and VL3 without panel load Min 1 2 VL2 0 1 3 2 VL2 0 1 Typ VSS 8 0 15 0 Unit V V V µA µA Max 1 2 VL2 0 9 3 2 VL2 0 9 15 0 20 0 During HALT During execution Without panel load Item Internal voltage Power current consumption S...

Page 72: ...VL2 VL3 IOP Condition Connect 1MΩ load resistor between VDD and VL1 without panel load Connect 1MΩ load resistor between VDD and VL2 without panel load Connect 1MΩ load resistor between VDD and VL3 without panel load Min 2 VL1 0 1 3 VL1 0 1 Typ VSS 8 0 15 0 Unit V V V µA µA Max 2 VL1 0 9 3 VL1 0 9 15 0 20 0 During HALT During execution Without panel load Item Internal voltage Power current consump...

Page 73: ...tion start voltage Allowable leak resistance Symbol Vsta Vss Vstp Vss CD f V f IC f CG Vhho Vss Rleak Condition Min 1 8 1 8 10 40 200 Typ 20 Unit V V pF ppm ppm ppm V MΩ Max 5 10 3 6 tsta 5sec tstp 10sec Including the parasitic capacity inside the IC Vss 1 8 to 3 6V CG 5 25pF CG 5pF Between OSC1 and VDD Item Oscillation start voltage Oscillation stop voltage Built in capacity drain Frequency volta...

Page 74: ...ion frequency dispersion Oscillation start voltage Oscillation start time Oscillation stop voltage Symbol fosc Vsta tsta Vstp Condition Vss 1 8 to 3 6V Min 20 1 8 1 8 Typ 65kHz 3 Unit V ms V Max 20 Item Oscillation frequency dispersion Oscillation start voltage Oscillation start time Oscillation stop voltage Symbol fosc Vsta tsta Vstp Condition Vss 1 2 to 2 0V Min 20 1 2 1 2 Typ 65kHz 3 Unit V ms ...

Page 75: ...C6001 TECHNICAL HARDWARE I 68 CHAPTER 7 PACKAGE 7 1 Plastic Package Plastic QFP12 48pin 7 0 1 9 0 4 25 36 7 0 1 9 0 4 13 24 INDEX 0 18 12 1 48 37 1 4 0 1 0 1 1 7 max 1 0 5 0 2 0 10 0 125 0 05 0 5 0 1 0 05 ...

Page 76: ...1 32 Pin Name VL1 CA CB VSS VDD OSC1 OSC2 N C N C VS1 N C N C N C P00 P01 P02 Pin No 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Pin Name P03 K00 K01 K02 K03 N C N C N C N C N C R01 R00 SEG19 SEG18 SEG17 SEG16 Pin No 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 N C No Connection Pin Name SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 N C N C N C TEST RESET SEG9 SEG8 SEG7 SEG6 N C 1 2 Pin No Index Mark...

Page 77: ...E0C6001 TECHNICAL HARDWARE I 70 CHAPTER 8 8 1 PAD LAYOUT Diagram of Pad Layout Chip size 2 640 µm X x 2 180 µm Y Y X 0 0 1 5 10 15 20 25 30 35 40 45 Die No ...

Page 78: ... SEG1 Pad Name SEG0 COM0 COM1 COM2 COM3 VL3 VL2 VL1 CA CB VSS VDD OSC1 OSC2 VS1 P00 P01 P02 P03 K00 K01 K02 K03 X 759 629 401 271 141 11 119 249 379 509 639 769 1 151 1 151 1 151 1 151 1 151 1 151 1 151 1 151 1 151 1 151 1 151 X 1 151 1 126 988 858 727 597 466 336 206 76 570 700 835 987 1 140 1 151 1 151 1 151 1 151 1 151 1 151 1 151 1 151 Y 923 923 923 923 923 923 923 923 923 923 923 923 789 657 ...

Page 79: ...Software E0C6001 II Technical Software ...

Page 80: ...APTER 3 PERIPHERAL CIRCUITS II 13 3 1 Input Port II 13 Input port memory map II 13 Control of the input port II 14 Examples of input port control program II 14 3 2 Output Port II 16 Output port memory map II 16 Control of the output port II 16 Examples of output port control program II 17 3 3 Special Use Output Port II 19 Special use output port memory map II 19 Control of the special use output p...

Page 81: ...I 35 3 7 Heavy Load Protection Function II 37 Heavy load protection function memory map II 37 Heavy load protection function II 37 Examples of heavy load protection function control program II 38 3 8 Interrupt and Halt II 39 Interrupt memory map II 39 Control of interrupts and halt II 40 Examples of interrupt and halt control program II 48 CHAPTER 4 SUMMARY OF PROGRAMMING POINTS II 50 APPENDIX A T...

Page 82: ...ler LCD Driver RAM 80 4 Interrupt Generator I Port Test Port I O Port O Port Timer Core CPU E0C6200B ROM 1 024 12 OSC System Reset Control RESET OSC1 COM0 COM3 SEG0 SEG19 VDD VL1 VL3 CA CB VS1 VSS K00 K03 TEST P00 P03 R00 R01 OSC2 FOUT BUZZER FOUT BUZZER BUZZER Fig 1 1 1 E0C6001 block diagram ...

Page 83: ...ity of 1 024 steps 12 bits for program storage The configuration of the ROM is shown in Figure 1 2 1 1 2 Fig 1 2 1 Configuration of built in ROM 00H step 07H step 08H step FFH step 12 bits Program start address Interrupt vector area Bank 0 Program area 0 page 1 page 2 page 3 page 01H step ...

Page 84: ...oaded into the program counter 3 The branch instruction written in the vector is executed to branch to the software interrupt processing routine Steps 1 and 2 require 12 cycles of the CPU system clock The interrupt vectors are shown in Table 1 3 1 1 3 Note Table 1 3 1 Interrupt requests and vectors Addesses start address of interrupt processing routines to jump to are written into the addresses av...

Page 85: ...he stack 2 Data memory addresses 000H 00FH are memory register areas that are addressed with register pointer RP Fig 1 4 1 Data memory map 1 4 Address Page High Low 0 1 2 3 4 5 6 7 8 9 A B C D E F M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF 3 0 1 2 4 5 6 7 8 9 A B C D E F 0 RAM 80 words x 4 bits R W Unused area I O memory Display memory Unused area Memory is not mounted in unused area within t...

Page 86: ...K01 EIK00 0 0 0 0 Enable Enable Enable Enable Mask Mask Mask Mask Timer data clock timer 2 Hz Timer data clock timer 4 Hz Timer data clock timer 8 Hz Timer data clock timer 16 Hz Input port K00 K03 High High High High Low Low Low Low Interrupt mask register K03 Interrupt mask register K02 Interrupt mask register K01 Interrupt mask register K00 High High High High Low Low Low Low 2 2 2 2 0 EIT2 EIT...

Page 87: ...T2 IT8 IT32 0 0 0 Yes Yes Yes Interrupt factor flag K00 K03 Interrupt factor flag clock timer 2 Hz Interrupt factor flag clock timer 8 Hz Interrupt factor flag clock timer 32 Hz Yes No R R 5 5 5 4 0F6H P03 P02 P01 P00 P03 P02 P01 P00 I O port P00 P03 High High High High Low Low Low Low 2 2 2 2 R W 5 4 4 4 5 5 No No No 0F3H 0 0 R01 R00 0 0 R01 BUZZER R00 FOUT 0 0 0 0 High ON High ON Low OFF Low OFF...

Page 88: ...d 6 Refer to main manual Address Comment Register D3 D2 D1 D0 Name SR 1 1 0 0F9H 0FAH 0 TMRST 0 0 HLMOD 0 0 0 W 0 TMRST 0 0 Reset HLMOD 0 0 0 0 Clock timer reset Heavy load protection mode register Reset R R R R W Heavy load Normal load 5 5 5 0FBH 0FCH CSDC 0 0 0 0 0 0 IOC R R 0 0 0 0 IOC 0 I O port P00 P03 Input Output LCD drive switch Static Dynamic Output Input 5 5 5 5 5 5 R W R W CSDC 0 0 0 5 ...

Page 89: ...mediately after being read 5 Always 0 when being read 6 Refer to main manual Address Comment Register D3 D2 D1 D0 Name SR 1 1 0 0FDH XBZR 0 XFOUT1 XFOUT0 R XBZR 0 XFOUT1 XFOUT0 0 0 0 Buzzer frequency control 2 kHz High High 4 kHz Low Low R W R W 5 FOUT frequency control XFOUT1 0 XFOUT0 0 F1 XFOUT1 0 XFOUT0 1 F2 XFOUT1 1 XFOUT0 0 F3 XFOUT1 1 XFOUT0 1 F4 ...

Page 90: ...er SP 8 Undefined Index register X 8 Undefined Index register Y 8 Undefined Register pointer RP 4 Undefined General register A 4 Undefined General register B 4 Undefined Interrupt flag I 1 0 Decimal flag D 1 0 Zero flag Z 1 Undefined Carry flag C 1 Undefined Internal Data Initial Value Memory Area Following Reset RAM data 4 80 Undefined 000H 05FH Display memory 4 20 Undefined 090H 0AFH Internal I ...

Page 91: ...initial values of some internal registers and internal data memory area locations are undefined after a reset Set them as necessary to the proper initial values in the pro gram The peripheral I O functions memory mapped I O are assigned to internal data memory area addresses 0E0H to 0FDH Each address represents a 4 bit internal I O register allowing access to the peripheral functions in 1 word 4 b...

Page 92: ...o INIT ORG 110H INIT RST F 0011B Interrupt mask decimal adjustment off LD X 0 RAMCLR LDPX MX 0 CP XH 5H JP NZ RAMCLR LD X 90H LCDCLR LDPX MX 0 CP XH 0BH JP NZ LCDCLR LD A 0 LD B 4 LD SPL A LD SPH B LD X 0F9H OR MX 0100B LD X 0EBH OR MX 0111B LD X 0E8H OR MX 1111B LD X 0 LD Y 0 LD A 0 LD B 0 RST F 0 EI Enable interrupt Clear RAM 00H 4FH Enable timer interrupt Enable input interrupt K03 K00 Clear LC...

Page 93: ...flow chart for this program Fig 2 2 1 Flow chart of the initialization program Initialization Reset I Interrupt flag D Decimal adjustment flag Clear RAM Set SP Reset timer Enable timer interrupt Enable input interrupt Reset registers X Y A B flags I Z D C EI enable interrupt I Interrupt flag D Decimal adjustment flag Clear data RAM 00H to 04FH Clear segment RAM 90H to 0AFH Set stack pointer to 40H...

Page 94: ...ing read 5 Always 0 when being read 6 Refer to main manual Input Port Address Comment Register D3 D2 D1 D0 Name SR 1 1 0 0E0H K03 K02 K01 K00 R K03 K02 K01 K00 Input port K00 K03 High High High High Low Low Low Low 2 2 2 2 0E8H EIK03 EIK02 EIK01 EIK00 R W EIK03 EIK02 EIK01 EIK00 0 0 0 0 Interrupt mask register K03 Interrupt mask register K02 Interrupt mask register K01 Interrupt mask register K00 ...

Page 95: ... condition flag See Section 3 8 Interrupt and Halt for details Loading K00 K03 into the A register Label Mnemonic operand Comment LD Y 0E0H Setaddressofport LD A MY Aregister K00 K03 As shown in Figure 3 1 1 the two instruction steps above load the data of the input port into the A register Control of the input port Examples of input port control program D3 K03 D2 K02 D1 K01 D0 K00 A register The ...

Page 96: ...becomes 1 This program loopes until a rising edge is input to input port K01 The input port can be addressed using the X register instead of the Y register When the input port is changed from high level to low level with a pull down resistor the signal falls following a certain delay caused by the time constants of the pull down resistance and the input gate capacitance It is therefore necessary t...

Page 97: ... port is a read write register output pins provide the con tents of the register The states of the output ports R00 R01 are decided by the data of address 0F3H Output ports can also be read and output control is possible using the operation instructions AND OR etc The output ports are all initialized to low level 0 after an initial reset Control of the output port Address Comment Register D3 D2 D1...

Page 98: ... shown in Figure 3 2 1 the two instruction steps above load the data of the B register into the output ports Examples of output port control program D3 D2 D1 D0 Data register R00 Data register R01 B register 0 when being read 0 when being read Fig 3 2 1 Control of the output port The output data can be taken from the A register MX or immediate data instead of the B register ...

Page 99: ...erand Comment LD Y 0F3H Set address of port OR MY 0010B Set R01 to 1 AND MY 1110B Set R00 to 0 The three instruction steps above cause the output port to be set as shown in Figure 3 2 2 Fig 3 2 2 Setting of the output port 0 0 R01 R00 Sets 0 Sets 1 Unused Unused Address 0F3H D3 D2 D1 D0 ...

Page 100: ...main manual Address Comment Register D3 D2 D1 D0 Name 1 0 0F3H 0 0 R01 R00 0 0 R01 BUZZER R00 FOUT 0 0 0 0 High ON High ON Low OFF Low OFF R01 output port data Buzzer ON OFF control register R00 output port data Frequency output ON OFF control register R W R BUZZER FOUT 0FDH XBZR 0 XFOUT1 XFOUT0 R XBZR 0 XFOUT1 XFOUT0 0 0 0 Buzzer frequency control 2 kHz High High 4 kHz Low Low R W R W FOUT freque...

Page 101: ...ble 3 3 2 Figure 3 3 1 shows the structure of output ports R00 and R01 Control of the spe cial use output port Table 3 3 2 Special output Fig 3 3 1 Structure of output ports R00 R01 FOUT or BUZZER BUZZER R00 R01 Pin Name When Special Output is Selected Address 0F3H Data bus Mask option R01 R00 Register R01 Register R00 FOUT BUZZER BUZZER ...

Page 102: ...t for BUZZER it performs 2 048 Hz or 4 096 Hz selected by register XBZR 0FDH D3 Label Mnemonic operand Comment LD Y 0FDH Set address of BUZZER frequency control register LD MY 1000B Select 2 048 Hz LD Y 0F3H Set address of output port OR MY 0010B Turn on BUZZER AND MY 1101B Turn off BUZZER Examples of special use output port control program ...

Page 103: ...own in Table 3 3 3 For example mask option is set to Set 4 Label Mnemonic operand Comment LD Y 0FDH Set address of FOUT frequency control register LD MY 0011B Select 16 384 Hz LD Y 0F3H Set address of output port OR MY 0001B Turn on FOUT AND MY 1110B Turn off FOUT Mask Option Sets Clock Frequency Hz Set 4 256 fosc 128 512 fosc 64 1 024 fosc 32 2 048 fosc 16 512 fosc 64 1 024 fosc 32 2 048 fosc 16 ...

Page 104: ...et in the circuit 3 Undefined 4 Reset 0 immediately after being read 5 Always 0 when being read 6 Refer to main manual Address Comment Register D3 D2 D1 D0 Name SR 1 1 0 0F6H P03 P02 P01 P00 P03 P02 P01 P00 I O port P00 P03 High High High High Low Low Low Low 2 2 2 2 R W 0FCH 0 0 0 IOC R 0 0 0 IOC 0 I O port P00 P03 Input Output Output Input 5 5 5 R W ...

Page 105: ... P03 is decided by the data of address 0F6H In the input mode the port level is read directly How to set an output port Set 1 in the I O port control register and the I O port is set as an output port The state of the I O port is decided by the data of address 0F6H This data is held by the register and can be set regardless of the contents of the I O control register The data can be set whether P0...

Page 106: ...ess of I O control port AND MY 1110B Set port as input port LD Y 0F6H Set address of port LD A MY A register P00 P03 As shown in Figure 3 4 1 the four instruction steps above load the data of the I O ports into the A register D3 P03 D2 P02 D1 P01 D0 P00 A register Examples of I O port control program Fig 3 4 1 Loading into the A register ...

Page 107: ...LD Y 0F6H Set the address of port LD A MY A register P00 P03 As shown in Figure 3 4 2 the four instruction steps above load the data of the I O ports into the A register P03 P02 P01 P00 Data register P00 Data register P01 Data register P02 Data register P03 A register D3 D2 D1 D0 Fig 3 4 2 Control of I O port input Data can be loaded from the I O port into the B register or MX instead of the A reg...

Page 108: ...0 P03 B register As shown in Figure 3 4 3 the four instruction steps above load the data of the B register into the I O ports D3 D2 D1 D0 Data register P00 Data register P01 Data register P02 Data register P03 B register The output data can be taken from the A register MX or immediate data instead of the B register Bit unit operation for the I O port is identical to that for the input ports K00 K0...

Page 109: ...y memory write only 32 words x 4 bits Table 3 5 1 I O memory map Address Comment Register D3 D2 D1 D0 Name SR 1 1 0 0FBH CSDC 0 0 0 R 0 LCD drive switch Static Dynamic 5 5 5 R W CSDC 0 0 0 1 Initial value following initial reset 2 Not set in the circuit 3 Undefined 4 Reset 0 immediately after being read 5 Always 0 when being read 6 Refer to main manual ...

Page 110: ...ot output even when data is written An LCD segment is on with 1 set in the display memory and off with 0 set in the display memory Note that the display memory is a write only LCD drive control register CSDC The LCD drive control register CSDC address 0FBH D3 can set the 1 1 duty drive Set 0 in CSDC for 1 4 duty 1 3 duty or 1 1 duty drive Set 1 in CSDC and the same value in the registers correspon...

Page 111: ... pattern is controlled by writing data to display memory addresses 090H and 091H g f e 091H d c b a 090H D3 D2 D1 D0 Address Register a g f b e c d SEG 0 19 COM 0 3 Frame frequency LCD lighting status COM0 COM1 COM2 COM3 SEG0 19 VDD VL1 VL2 VL3 VDD VL1 VL2 VL3 VDD VL1 VL2 VL3 Not lit Lit Fig 3 5 2 1 1 duty drive control 1 3 bias ...

Page 112: ...ay memory JPBA When the above routine is called by the CALL or CALZ instruction with any number from 0 to 9 set in the A register for the assignment of Figure 3 5 4 seven segments are displayed according to the contents of the A register The RETD instruction can be used to write data to the display memory only if it is addressed using the X register Addressing using the Y register is invalid Note ...

Page 113: ... Change buffer data LD MY MX SEG B OFF For manipulation of the display memory in bit units for the assignment of Figure 3 5 5 a buffer must be provided in RAM to hold data Note that since the display memory is write only data cannot be changed directly using an ALU instruction for example AND or OR After manipulating the data in the buffer write it into the corresponding display memory using the t...

Page 114: ...lock timer 4 Hz Timer data clock timer 8 Hz Timer data clock timer 16 Hz High High High High Low Low Low Low 0EBH 0 EIT2 EIT8 EIT32 R 0 EIT2 EIT8 EIT32 0 0 0 Enable Enable Enable Mask Mask Mask Interrupt mask register clock timer 2 Hz Interrupt mask register clock timer 8 Hz Interrupt mask register clock timer 32 Hz R W 0EFH 0 IT2 IT8 IT32 0 IT2 IT8 IT32 0 0 0 Yes Yes Yes No No No Interrupt factor...

Page 115: ...waveform See Figure 3 6 1 The timer can also interrupt the CPU on the falling edges of the 32 Hz 8 Hz and 2 Hz signals For details see Section 3 8 Inter rupt and Halt Control of the timer The timer is reset by setting 1 in TMRST address 0F9H D2 The 128 Hz to 2 Hz of the internal divider is initialized by resetting the timer Fig 3 6 1 Output waveform of timer and interrupt timing Note Clock timer t...

Page 116: ...timer The TMRST register is cleared to 0 by hardware 1 clock after it is set to 1 Loading the timer Label Mnemonic operand Comment LD Y 0E4H Set address of the timer data TM0 to TM3 LD A MY Load the data of TM0 to TM3 into A register As shown in Table 3 6 2 the two instruction steps load the data of TM0 to TM3 into the A register Table 3 6 2 Loading the timer data Examples of timer control program...

Page 117: ...e timer data buffer LD MY A Set the data of A register into the timer data buffer JP Z RETURN Jump if the Z flag is 1 ADD MX 0FH Decrement the timer edge counter RETURN RET Return This program takes a subroutine form It is called at short intervals and decrements the data at address TMSTAT every 125 ms until the data reaches 0 The timing chart is shown in Figure 3 6 2 The timer can be addressed us...

Page 118: ...oad Normal load SR 1 5 5 5 Heavy load protec tion function The E0C6001 has the heavy load protection function for when the battery load becomes heavy and the source voltage changes such as when an external buzzer sounds or an external lamp lights The state where the heavy load protec tion function is in effect is called the heavy load protection mode Compared with the normal operation mode this mo...

Page 119: ...mode LD Y 0F3H Sets the address of R0n port OR MY 0001B Turns lamp ON LD Y 0F3H Sets the R0n port address AND MY 1110B Turns the lamp OFF CALL WT1S 1 second waiting time software timer AND MX 0111B Cancels the heavy load protection mode In the above program the heavy load protection mode is canceled after 1 sec waiting time provided as the time for the battery voltage to stabilize after the lamp i...

Page 120: ...EIT2 EIT8 EIT32 0 0 0 Enable Enable Enable Mask Mask Mask Interrupt mask register K03 Interrupt mask register K02 Interrupt mask register K01 Interrupt mask register K00 Enable Enable Enable Enable Mask Mask Mask Mask Interrupt mask register clock timer 2 Hz Interrupt mask register clock timer 8 Hz Interrupt mask register clock timer 32 Hz R W 0EDH 0 0 IK0 R R 0 0 0 IK0 0 Interrupt factor flag K00...

Page 121: ...bled or masked dis abled by interrupt mask registers The EI and DI instruc tions can be used to set or reset the interrupt flag I which enables or disables all the interrupts at the same time When an interrupt is accepted the interrupt flag I is reset and cannot accepts any other interrupts DI state Restart from the halt state created by the HALT instruction is done by interrupt Control of interru...

Page 122: ...nding interrupt mask register EIK00 EIK03 is 1 The contents of the IK0 flag can be loaded by software to determine whether the K00 K03 input interrupts have occured The flag is reset when loaded by software See Figure 3 8 1 IK0 Fig 3 8 1 K00 K03 Input interrupt circuit D0 D1 D2 D3 Address 0E8H Input interrupt mask register EIK00 EIK03 Input interrupt factor flag register IK0 INT Interrupt request ...

Page 123: ...re to determine whether an 8 Hz timer interrupt has occured The flag is reset when it is loaded by software See Figure 3 8 2 This flag is set to 1 when a falling edge is detected in the timer TM1 2 Hz signal The contents of the IT2 flag can be loaded by software to determine whether a 2 Hz timer interrupt has occured The flag is reset when it is loaded by software See Figure 3 8 2 IT32 Fig 3 8 2 T...

Page 124: ...h becomes the interrupt input is in the active status input terminal high status the factor flag for input interrupt may be set For example a factor flag is set with the timing of shown in Figure 3 8 3 However when clearing the content of the mask register with the input terminal kept in the high status and then setting it the factor flag of the input inter rupt is again set at the timing that has...

Page 125: ...gure 3 8 2 EIT8 This register enables or masks the 8 Hz timer interrupt The CPU is interrupted if it is in the EI state when the interrupt mask register EIT8 is set to 1 and the interrupt condition flag IT8 is 1 See Figure 3 8 2 This register enables or masks the 2 Hz timer interrupt The CPU is intterrupted if it is in the EI state when the interrupt mask register EIT2 is set to 1 and the interrup...

Page 126: ...entified by software Similarly the K00 K03 input interrupts must be identified by software When an interrupt is generated the hardware resets the interrupt flag I to enter the DI state Execute the EI in struction as necessary to recover the EI state after interrupt processing Set the EI state at the start of the interrupt processing routine to allow nesting of the interrupts The interrupt factor f...

Page 127: ...ion error if read in the EI state The timer interrupt factor flags IT32 IT8 IT2 and the stopwatch interrupt factor flags ISW1 ISW0 are set whether the corresponding interrupt mask register is set or not The input interrupt factor flag IK0 is allowed to be set in the condition when the corresponding interrupt mask regis ter EIK00 EIK03 is set to 1 interrupt is enabled See Figure 3 8 5 Table 3 8 2 s...

Page 128: ...g 3 8 5 Internal interrupt circuit K00 EIK00 K01 EIK01 K02 EIK02 K03 EIK03 IT2 EIT2 IT8 EIT8 IT32 EIT32 IK0 MSB LSB Program counter of CPU three low order bits Interrupt vector Interrupt factor flag Interrupt mask register Interrupt flag INT Interrupt request ...

Page 129: ...pt CALL TINT2 Call 2 Hz timer interrupt service routine TI8RQ LD Y TMFSK Address of timer factor flag buffer FAN MY 0010B Check 8 Hz timer interrupt JP Z TI32RQ Jump if not 8 Hz timer interrupt CALL TINT8 Call 8 Hz timer interrupt service routine Restart from halt state by interrupt Mainroutine Label Mnemonic operand Comment LD X 0E8H Set address of K00 to K03 interrupt mask register OR MX 1111B E...

Page 130: ...after the interrupt processing is completed The processing proceeds by repeating the halt interrupt halt interrupt cycle The interrupt factor flag is reset when load by the software Thus when using interrupts which interrupt factor flags are in the same address at the same time flag check must be done after storing the data For example store the 1 word including the factor flag in the RAM If check...

Page 131: ...ata area and the stack area do not overlap The stack area consumes 3 words during a sub routine call or interrupt Address 00H 0FH in the RAM is the memory register area addressed by the register pointer RP Memory is not mounted in unused area within the mem ory map and in memory area not indicated in this man ual For this reason normal operation cannot be assured for programs that have been prepar...

Page 132: ...put terminal high status the factor flag for input interrupt may be set For example a factor flag is set with the timing of shown in Figure 4 1 However when clearing the content of the mask register with the input terminal kept in the high status and then setting it the factor flag of the input interrupt is again set at the timing that has been set Consequently when the input terminal is in the ac...

Page 133: ... Hence the electric potential of the pins must settle within 0 5 cycles If this condition cannot be met some measure must be devised such as arranging a pull down resis tance externally or performing multiple read outs LCD Driver Because the display memory is for writing only re writing the contents with computing instructions e g AND OR etc which come with read out operations is not possible To p...

Page 134: ...are Not resetting the interrupt factor flag and interrupt mask register being 1 will cause the same interrupt to occur again The interrupt factor flag will be reset by reading through the software Because of this when multiple interrupt factor flags are to be assigned to the same address perform the flag check after the contents of the address has been stored in the RAM Direct checking with the FA...

Page 135: ... r0 r0 r0 r0 r0 r0 r0 i0 i0 i0 i0 p s C s NC s Z s NZ s s s l X Y X x Y y XH r XL r YH r YL r r XH r XL r YH r YL XH i XL i YH i YL i PSET JP JPBA CALL CALZ RET RETS RETD NOP5 NOP7 HALT INC LD ADC Branch instructions System control instructions Index operation instructions Classification Operand I D Z C 5 5 5 5 5 5 5 7 7 7 12 12 5 7 5 5 5 5 5 5 5 5 5 5 5 5 5 7 7 7 7 Clock Operation Code Flag NBP p...

Page 136: ...1 i1 i1 0 1 1 0 0 1 0 1 1 1 r1 0 1 0 0 1 r1 0 1 0 i0 i0 i0 i0 i0 q0 n0 n0 n0 n0 i0 q0 i0 q0 l0 i0 i0 1 0 0 1 0 1 0 1 1 1 r0 1 0 0 1 0 r0 1 0 XH i XL i YH i YL i r i r q A Mn B Mn Mn A Mn B MX i r q MY i r q MX l F i F i SP SP r XH XL YH YL F r XH XL CP LD LDPX LDPY LBPX SET RST SCF RCF SZF RZF SDF RDF EI DI INC DEC PUSH POP Index operation instructions Data transfer instructions Flag operation ins...

Page 137: ... 1 2 0 0 0 0 0 1 1 i2 r0 i2 r0 r0 i2 r0 i2 r0 i2 r0 i2 r0 i2 r0 i2 r0 r0 1 n2 n2 0 1 0 1 1 1 0 0 1 r1 r1 r1 r1 i1 q1 i1 q1 q1 i1 q1 i1 q1 i1 q1 i1 q1 i1 q1 i1 q1 r1 r1 n1 n1 r1 r1 r1 r1 1 0 0 1 0 r0 r0 r0 r0 i0 q0 i0 q0 q0 i0 q0 i0 q0 i0 q0 i0 q0 i0 q0 i0 q0 r0 r0 n0 n0 r0 r0 r0 r0 1 YH YL F SPH r SPL r r SPH r SPL r i r q r i r q r q r i r q r i r q r i r q r i r q r i r q r i r q r r Mn Mn MX r ...

Page 138: ... IY SP Stack pointer SP SPH High order four bits of stack pointer SP SPL Low order four bits of stack pointer SP MX M X Data memory whose address is specified with index register IX MY M Y Data memory whose address is specified with index register IY Mn M n Data memory address 000H 00FH address specified with immediate data n of 00H 0FH M SP Data memory whose address is specified with stack pointe...

Page 139: ...I Interrupt flag Flag reset Flag set Flag set or reset p Five bit immediate data or label 00H 1FH s Eight bit immediate data or label 00H 0FFH l Eight bit immediate data 00H 0FFH i Four bit immediate data 00H 0FH Add Subtract Logical AND Logical OR Exclusive OR Add subtract instruction for decimal operation when the D flag is set Symbols associated with program counter Symbols associated with flag...

Page 140: ... YES YES YES NO NO NO TIMER INTERRUPT FACTOR FLAG 2 Hz TIMER INTERRUPT FACTOR FLAG 8 Hz TIMER INTERRUPT FACTOR FLAG 32 Hz IT32 R IT8 R IT2 R 0 R EF AD DRESS D0 D1 D2 D3 0 1 SR NAME COMMENT DATA YES NO 0 0 0 R01 BUZZER R00 FOUT 0 0 0 0 HIGH ON HIGH ON LOW OFF LOW OFF R01 OUTPUT PORT DATA BUZZER ON OFF CONTROL REGISTER R00 OUTPUT PORT DATA FREQUENCY OUTPUT ON OFF CONTROL REGISTER R00 FOUT R W R01 BU...

Page 141: ...ep instruction from a address Displays only the final step of T a n Sets Break at program address a Breakpoint is canceled Break condition is set for data RAM Breakpoint is canceled Break condition is set for EVA62XXCPU internal registers Breakpoint is canceled Combined break conditions set for program data RAM address and registers Cancel combined break conditions for program data ROM address and...

Page 142: ...ndicates history acquisition program area Retrieves and indicates the history information which executed a program address a Retrieves and indicates the history information which wrote or read the data area address a Save contents of memory to program file Save contents of memory to data file Load ICE6200 set condition from file Save ICE6200 set condition to file Terminate ICE and return to operat...

Page 143: ...llocate data to label To define location counter To allocate data to label data can be changed To define ROM data To define boundary of page To define boundary of section To terminate assembly To define macro To make local specification of label during macro definition To end macro definition ABC EQU 9 CHECK MACRO DATA LOCAL LOOP LOOP CP MX DATA JP NZ LOOP ENDM CHECK 1 BCD EQU ABC 1 ORG 100H ORG 2...

Page 144: ...one 33 0 1 64862350 Fax 33 0 1 64862355 ASIA HONG KONG CHINA EPSON HONG KONG LTD 20 F Harbour Centre 25 Harbour Road Wanchai HONG KONG Phone 852 2585 4600 Fax 852 2827 4346 Telex 65542 EPSCO HX CHINA SHANGHAI EPSON ELECTRONICS CO LTD 4F Bldg 27 No 69 Gui Jing Road Caohejing Shanghai CHINA Phone 21 6485 5552 Fax 21 6485 0775 TAIWAN R O C EPSON TAIWAN TECHNOLOGY TRADING LTD 10F No 287 Nanking East R...

Page 145: ...ursuit of Saving Technology Epson electronic devices Our lineup of semiconductors liquid crystal displays and quartz devices assists in creating the products of our customers dreams Epson IS energy savings ...

Page 146: ...ELECTRONIC DEVICES MARKETING DIVISION Electronic devices information on the Epson WWW server http www epson co jp First issue FEBRUARY 1997 Printed AUGUST 1998 in Japan M A ...

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