Epson DFX-5000+, Service Manual

Page: 92 / 223

Operating Principles
Table 2-7. RF Motor Specifications
Specification Description
720
PG Motor Driver Circuit
Figure 2-29 shows a block diagram PG motor driver circuit, and Table 2-8
provides PG motor specifications. The motor phase switching signals are output
from the PGA port and input to the PGBN port
gate array. The motor
common voltage (PGCOM) alternates between drive mode VDC) and hold
mode VDC) using the pulses from port PGI gate array. The phase driver
IC (QM2) is turned on when the motor pulse switching data is LOW.
The phase A output pulse from the platen gap encoder (ENCA) is input to general
purpose port ENCA
gate array and the phase B output pulse from the
platen gap encoder (ENCB) is input to general purpose port ENCB gate
array. The gate array counts these pulses using the internal counter and
determines the amount and direction
rotation.
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