Operating Principles
VDC reset circuit
Reset IC
monitors the
VDC line on the Cl 17 MAIN board assembly.
If it drops to 4.2 VDC, the reset IC outputs a LOW signal to the CPU, gate array,
and optional interface board. The gate array outputs the RESET signal to the
reset port
CPU and also to the gate array itself, via the delay control circuit
(CR circuit). The delay control circuit consists of R26 and C72 and controls the
reset timing for the CPU and Type B interface card.
VDC reset circuit
Reset IC M51955 monitors the
VDC line. Normally, the dividing resistors
(R27 and R28) input approximately 1.7 VDC to pin 2. When the detection level is
1.7 VDC, the
VDC line drops into the 22.9 V to 30.0 V range.
voltage level drops to
VDC, the RESET signal (LOW level) is output
to the CPU’s
port. When the printer is turned off, this circuit operates and
manages writing to the EEPROM.
NMI
CPU
Figure 2-20. Reset Circuit Block Diagram
2-26
EPSON DFX-5000+ Service Manual
Summary of Contents for DFX-5000+
Page 1: ...EPSON Service Manual Epson America Inc TM DFX5K ...
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Page 212: ...Appendix Table A S CN7 C117 MAIN Board Assembly A 8 EPSON DFX 5000 Service Manual ...
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Page 219: ...Appendix DFX 5000 Exploded Diagram 1 EPSON DFX 5000 Service Manual A 15 ...
Page 220: ...Appendix Figure A 5 Exploded Diagram 2 A 16 EPSON DFX 5000 Service Manual ...
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Page 222: ...Appendix A 18 EPSON DFX 5000 Service Manual ...
Page 223: ...Appendix Figure A 7 C117 MAIN Board Circuit Diagram EPSON DFX 5000 Service Manual A 19 ...