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Appendix
Pin No.
1
2
3
4
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
Table A-3. CN5 Pin Assignments
Signal
Name
NC
NC
MCLK
AO
A2
A3
A4
A5
A6
AlO
NC
A7
NC
A8
WR
WR
1
I/o
—
I/o
—
I/o
o
—
o
0
0
0
0
0
0
0
0
—
I/o
o
I/o
o
o
0
—
—
o
0
0
0
0
0
0
0
—
o
0
0
0
0
0
0
0
0
Description
Ground
Data bus bit O
for CPU
Data bus bit 1
Not connected
Data bus bit 2
Not
Data bus bit 3
Clock
+5
Read strobe
Address bit O
Address bit 1
Address bit 2
Address bit 3
Address bit 4
Address bit 5
Address bit 6
Address bit 10
Data bus bit 4
Not connected
Data bus 5
Address bit 22
Data bus bit 6
Address bit 21
Data bus bit 7
Address bit 20
Address bit 7
Not connected
bit 8
bit 9
strobe
strobe
bit 11
bit 13
bit 14
bit 12
bit 18
bit 17
bus bit
8
Rev.