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Epson 0C88832, Technical Manual

The Epson 0C88832 Technical Manual is a comprehensive guide that provides detailed instructions and troubleshooting tips for the Epson 0C88832 product. Easily downloadable for free from our website, this manual ensures hassle-free usage and optimal performance for your Epson 0C88832, making it an essential resource for every user.

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EPSON

E0C88832/88862 TECHNICAL MANUAL

5  PERIPHERAL CIRCUITS AND THEIR OPERATION (Serial Interface)

ESTRA, ESREC, ESERR: 00FF23H•D0, D1, D2

Enables or disables the generation of an interrupt
for the CPU.

When "1" is written: Interrupt enabled
When "0" is written: Interrupt disabled
Reading:

Valid

ESTRA, ESREC and ESERR are interrupt enable
registers that respectively correspond to the
interrupt factors for transmitting complete, receiv-
ing complete and receiving error. Interrupts set to
"1" are enabled and interrupts set to "0" are disa-
bled.
At initial reset, this register is set to "0" (interrupt
disabled).

FSTRA, FSREC, FSERR: 00FF25H•D0, D1, D2

Indicates the serial interface interrupt generation status.

When "1" is read:

Interrupt factor present

When "0" is read:

Interrupt factor not present

When "1" is written: Resets factor flag
When "0" is written: Invalid

FSTRA, FSREC and FSERR are interrupt factor flags
that respectively correspond to the interrupts for
transmitting complete, receiving complete and
receiving error and are set to "1" by generation of
each factor.
Transmitting complete interrupt factor is generated
at the point where the data transmitting of the shift
register has been completed.
Receiving complete interrupt factor is generated at
the point where the received data has been trans-
ferred into the received data buffer.
Receive error interrupt factor is generated when a
parity error, framing error or overrun error has
been detected during data receiving.
When set in this manner, if the corresponding
interrupt enable register is set to "1" and the
corresponding interrupt priority register is set to a
higher level than the setting of interrupt flags (I0
and I1), an interrupt will be generated to the CPU.
Regardless of the interrupt enable register and
interrupt priority register settings, the interrupt
factor flag will be set to "1" by the occurrence of an
interrupt generation condition.
To accept the subsequent interrupt after interrupt
generation, re-setting of the interrupt flags (set
interrupt flag to lower level than the level indicated
by the interrupt priority registers, or execute the
RETE instruction) and interrupt factor flag reset are
necessary. The interrupt factor flag is reset to "0" by
writing "1".
At initial reset, this flag is reset to "0".

5.7.10 Programming notes

(1) Be sure to initialize the serial interface mode in

the transmitting/receiving disable status (TXEN
= RXEN = "0").

(2) Do not perform double trigger (writing "1") to

TXTRG (RXTRG) when the serial interface is in
the transmitting (receiving) operation. Further-
more, do not execute the SLP instruction. (When
executing the SLP instruction, set TXEN =
RXEN = "0".)

(3) In the clock synchronous mode, since one clock

line (SCLK) is shared for both transmitting and
receiving, transmitting and receiving cannot be
performed simultaneously. (Half duplex only is
possible in clock synchronous mode.)
Consequently, be sure not to write "1" to
RXTRG (TXTRG) when TXTRG (RXTRG) is "1".

(4) When a parity error or flaming error is gener-

ated during receiving in the asynchronous
mode, the receiving error interrupt factor flag
FSERR is set to "1" prior to the receiving
complete interrupt factor flag FSREC for the
time indicated in Table 5.7.10.1. Consequently,
when an error is generated, you should reset the
receiving complete interrupt factor flag FSREC
to "0" by providing a wait time in error process-
ing routines and similar routines.
When an overrun error is generated, the
receiving complete interrupt factor flag FSREC
is not set to "1" and a receiving complete
interrupt is not generated.

Table 5.7.10.1  Time difference between FSERR

       and FSREC on error generation

(5) When the demultiplied signal of the OSC3

oscillation circuit is made the clock source, it is
necessary to turn the OSC3 oscillation ON, prior
to using the serial interface.
A time interval of several 100 

µ

sec to several 10

msec, from the turning ON of the OSC3 oscilla-
tion circuit to until the oscillation stabilizes, is
necessary, due to the oscillation element that is
used. Consequently, you should allow an
adequate waiting time after turning ON of the
OSC3 oscillation, before starting transmitting/
receiving of serial interface. (The oscillation
start time will vary somewhat depending on the
oscillator and on the externally attached parts.
Refer to the oscillation start time example
indicated in Chapter 7, "ELECTRICAL CHAR-
ACTERISTICS".)
At initial reset, the OSC3 oscillation circuit is set
to OFF status.

Clock source

Time difference

f

OSC3

 / n

Programmable timer

1/2 cycles of f

OSC3

 / n

1 cycle of timer 1 underflow

Summary of Contents for 0C88832

Page 1: ...MF1215 01 CMOS 8 BIT SINGLE CHIP MICROCOMPUTER E0C88832 88862TECHNICAL MANUAL E0C88832 88862 Technical Hardware ...

Page 2: ...uiring high level reliability such as medical products Moreover no license to any intellectual property rights is granted by implication or otherwise and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party This material or portions thereof may contain technology or the subject relating to...

Page 3: ...ls K00 K03 15 4 1 3 Supply voltage detection SVD circuit 16 4 1 4 Initial reset sequence 16 4 2 Initial Settings After Initial Reset 17 5 PERIPHERAL CIRCUITS AND THEIR OPERATION 18 5 1 I O Memory Map 18 5 2 Watchdog Timer 27 5 2 1 Configuration of watchdog timer 27 5 2 2 Interrupt function 27 5 2 3 Control of watchdog timer 27 5 2 4 Programming notes 27 5 3 Oscillation Circuits and Operating Mode ...

Page 4: ...tion 60 5 7 9 Control of serial interface 62 5 7 10 Programming notes 66 5 8 Clock Timer 67 5 8 1 Configuration of clock timer 67 5 8 2 Interrupt function 67 5 8 3 Control of clock timer 69 5 8 4 Programming notes 71 5 9 Stopwatch Timer 72 5 9 1 Configuration of stopwatch timer 72 5 9 2 Count up pattern 72 5 9 3 Interrupt function 73 5 9 4 Control of stopwatch timer 74 5 9 5 Programming notes 76 5...

Page 5: ... 113 5 14 1 Interrupt generation conditions 114 5 14 2 Interrupt factor flag 114 5 14 3 Interrupt enable register 115 5 14 4 Interrupt priority register and interrupt priority level 115 5 14 5 Exception processing vectors 116 5 14 6 Control of interrupt 117 5 14 7 Programming notes 118 5 15 Notes for Low Current Consumption 119 6 BASIC EXTERNAL WIRING DIAGRAM 120 7 ELECTRICAL CHARACTERISTICS 122 7...

Page 6: ......

Page 7: ...oltage Like all the equipment in the E0C Family these microcomput ers have low power consumption 1 1 Configuration In this manual the E0C88832 88862 is associated with E0C88832 and E0C88862 In these models there are differences in built in ROM capacity number of output ports and number of LCD drive segments but the other peripheral circuits are made with the same configuration Table 1 1 1 Configur...

Page 8: ... signal and FOUT output 8 bits 4 bits can be set for serial interface input output 1ch Optional clock synchronous system or asynchronous system Programmable timer 8 bits 1ch can be set as a an event counter or 2ch as a 16 bits programmable timer for 1ch Clock timer 8 bits Stopwatch timer 8 bits Built in booster type 5 potentials 4 potentials Dot matrix type compatible with 5 8 or 5 5 fonts 51 segm...

Page 9: ...ator SEG0 SEG40 COM16 COM31 SEG66 SEG51 COM0 COM15 P14 P17 CA CG Selectable by mask option E0C88832 Fig 1 3 1 E0C88832 block diagram E0C88862 Fig 1 3 2 E0C88862 block diagram Core CPU E0C88 Interrupt Controller Input Port Oscillator OSC1 2 OSC3 4 Reset Test Watchdog Timer K00 K07 K10 EVIN I O Port Serial Interface Output Port Programmable Timer Event Counter Clock Timer Stopwatch Timer Power Gener...

Page 10: ...E CD CC CB CA VC5 VC4 VC3 VC2 VC1 Pin No Pin name 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 N C SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 N C No Connection Pin No Pin name 97 98 99 100 101 102 103 104 105 106 107...

Page 11: ...on external clock input with mask option OSC3 oscillation output terminal Input terminals K00 K07 Input terminal K10 or event counter external clock input terminal EVIN Output terminal R26 or programmable timer underflow signal inverted output terminal TOUT selectable by mask option Output terminal R27 or programmable timer underflow signal output terminal TOUT Output terminal R34 or clock output ...

Page 12: ...M16 SEG66 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 N C VOSC VD1 VDD VSS OSC1 OSC2 TEST RESET K10 EVIN K07 K06 K05 K04 K03 K02 K01 K00 P17 P16 P15 P14 P13 SRDY P12 SCLK P11 SOUT P10 SIN R26 TOUT R27 TOUT R50 BZ R51 BZ N C N C 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127...

Page 13: ...nput with mask option OSC3 oscillation output terminal Input terminals K00 K07 Input terminal K10 or event counter external clock input terminal EVIN Output terminal R26 or programmable timer underflow signal inverted output terminal TOUT selectable by mask option Output terminal R27 or programmable timer underflow signal output terminal TOUT Output terminal R50 or buzzer output terminal BZ Output...

Page 14: ...tails 5 Input port pull up resistor This mask option can select whether the pull up resistor for the input port terminal is used or not It is possible to select for each bit of the input ports Refer to Section 5 4 Input Ports K ports for details 6 R26 R51 output port specifications The R26 port can be configured as a general purpose output port or as the TOUT output port TOUT inverted output The R...

Page 15: ...LTIPLE KEY ENTRY RESET Combination 1 Not Use 2 Use K00 K01 3 Use K00 K01 K02 4 Use K00 K01 K02 K03 4 SVD RESET 1 Not Use 2 Use 5 INPUT PORT PULL UP RESISTOR K00 1 With Resistor 2 Gate Direct K01 1 With Resistor 2 Gate Direct K02 1 With Resistor 2 Gate Direct K03 1 With Resistor 2 Gate Direct K04 1 With Resistor 2 Gate Direct K05 1 With Resistor 2 Gate Direct K06 1 With Resistor 2 Gate Direct K07 1...

Page 16: ...OWER SUPPLY 1 Internal TYPE A VC2 Standard 1 5 Bias 4 5 V 2 External 3 Internal TYPE B VC2 Standard 1 5 Bias 5 5 V 4 Internal TYPE C VC2 Standard 1 4 Bias 4 5 V 5 Internal TYPE D VC1 Standard 1 4 Bias 4 5 V 9 R51 OUTPUT PORT SPECIFICATION 1 With BZ Use 2 Without BZ Not Use 10 R26 OUTPUT PORT SPECIFICATION 1 With TOUT Use 2 Without TOUT Not Use ...

Page 17: ...5 3 Oscillation Circuits and Operating Mode for the switching of operating mode The oscillation system voltage regulator generates the operating voltage VOSC for the OSC1 oscillation circuit The LCD system power supply circuit generates the LCD drive voltages VC1 to VC5 In 1 5 bias mode VC1 is generated by halving VC2 output from the LCD system voltage regulator and VC3 to VC5 are generated by boo...

Page 18: ...omes valid when the peripheral circuits are in the following status 1 The OSC3 oscillation circuit is switched ON OSCC 1 and not in SLEEP 2 The buzzer output is switched ON BZON 1 or BZSHT 1 SLEEP status Heavy load protection mode OSCC BZON BZSHT Fig 2 3 1 Configuration of heavy load protection mode control circuit For details of the OSC3 oscillation circuit and buzzer output see 5 3 Oscillation C...

Page 19: ...ress 000000H 007FFFH 000000H 00EFFFH 3 2 2 RAM The internal ROM capacity is shown in Table 3 2 2 1 Table 3 2 2 1 Internal ROM capacity Model E0C88832 E0C88862 RAM capacity 1 5K bytes 1 5K bytes Address 00F000H 00F5FFH 00F000H 00F5FFH 3 2 3 I O memory A memory mapped I O method is employed in the E0C88832 88862 for interfacing with internal peripheral circuit Peripheral circuit control bits and dat...

Page 20: ... timer 32 Hz interrupt Clock timer 8 Hz interrupt Clock timer 2 Hz interrupt Clock timer 1 Hz interrupt System reserved cannot be used Software interrupt For each vector address and the address after it the start address of the exception processing routine is written into the subordinate and super ordinate sequence When an exception processing factor is generated the exception processing routine i...

Page 21: ...se 2 K00 K01 3 K00 K01 K02 4 K00 K01 K02 K03 For instance if mask option 4 K00 K01 K02 K03 is selected initial reset will take place when the input level at input ports K00 K03 is simultane ously LOW When using this function make sure that the designated input ports do not simultaneously switch to LOW level while the system is in normal operation 4 INITIAL RESET Initial reset in the E0C88832 88862...

Page 22: ...l sampling time 248 fOSC1 sec is added as additional waiting time Figure 4 1 4 1 shows the operating sequence following initial reset release Also when using the initial reset by simultaneous LOW level input into the input port you should be careful of the following points 1 During SLEEP status since the time authoriza tion circuit is bypassed an initial reset is triggered immediately after a LOW ...

Page 23: ...H Bit length 8 8 8 8 16 16 16 16 8 1 1 1 1 1 1 1 1 8 8 8 8 8 4 2 Initial Settings After Initial Reset The CPU internal registers are initialized as follows during initial reset Table 4 2 1 Initial settings Reset exception processing loads the preset values stored in 0 bank 000000H 000001H into the PC At the same time 01H of the NB initial value is loaded into CB Initialize the registers which are ...

Page 24: ...al purpose register General purpose register General purpose register General purpose register General purpose register General purpose register Reserved register Note 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W 1 0 00FF02 D7 D6 D5 D4 D3 D2 D1 D0 EBR WT2 WT1 WT0 CLKCHG OSCC VDC1 VDC0 General purpose register General purpose register General purpose register General purpose register CPU operati...

Page 25: ...ampling 2 Initial values are set according to the supply voltage detected at first sampling by hardware Until conclusion of first sampling SVD0 SVD3 data are undefined 00FF20 D7 D6 D5 D4 D3 D2 D1 D0 PK01 PK00 PSIF1 PSIF0 PSW1 PSW0 PTM1 PTM0 K00 K07 interrupt priority register Serial interface interrupt priority register Stopwatch timer interrupt priority register Clock timer interrupt priority reg...

Page 26: ...timer 0 interrupt enable register K10 interrupt enable register K04 K07 interrupt enable register K00 K03 interrupt enable register Serial I F error interrupt enable register Serial I F receiving interrupt enable register Serial I F transmitting interrupt enable register 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W Interrupt enable Interrupt disable 00FF30 D7 D6 D5 D4 D3 D2 D1 D0 MODE16 CHSEL P...

Page 27: ...Prescaler dividing ratio Source clock 64 Source clock 16 Source clock 4 Source clock 1 D7 D6 D5 D4 D3 D2 D1 D0 RLD17 RLD16 RLD15 RLD14 RLD13 RLD12 RLD11 RLD10 Timer 1 reload data D7 MSB Timer 1 reload data D6 Timer 1 reload data D5 Timer 1 reload data D4 Timer 1 reload data D3 Timer 1 reload data D2 Timer 1 reload data D1 Timer 1 reload data D0 LSB 1 1 1 1 1 1 1 1 R W R W R W R W R W R W R W R W H...

Page 28: ...8 Hz 16 Hz 32 Hz 64 Hz 128 Hz FOUT2 0 0 0 0 1 1 1 1 FOUT1 0 0 1 1 0 0 1 1 FOUT0 0 1 0 1 0 1 0 1 Frequency fOSC1 1 fOSC1 2 fOSC1 4 fOSC1 8 fOSC3 1 fOSC3 2 fOSC3 4 fOSC3 8 00FF42 D7 D6 D5 D4 D3 D2 D1 D0 SWRST SWRUN Stopwatch timer reset Stopwatch timer Run Stop control Constantly 0 when being read 0 W R W Reset Run No operation Stop 00FF43 D7 D6 D5 D4 D3 D2 D1 D0 SWD7 SWD6 SWD5 SWD4 SWD3 SWD2 SWD1 S...

Page 29: ...EPR PMD SCS1 SCS0 SMD1 SMD0 ESIF Parity enable register Parity mode selection Clock source selection Serial I F mode selection Serial I F enable register 0 when being read Only for asynchronous mode In the clock synchro nous slave mode external clock is selected 0 0 0 0 0 0 0 R W R W R W R W R W R W R W With parity Odd Serial I F Non parity Even I O port SCS1 1 1 0 0 SCS0 1 0 1 0 Clock source Prog...

Page 30: ...R W Interrupt enable Interrupt disable 00FF51 D7 D6 D5 D4 D3 D2 D1 D0 SIK11 SIK10 General purpose register K10 interrupt selection register Constantly 0 when being read Reserved register 0 0 R W R W 1 Enable 0 Disable 00FF53 D7 D6 D5 D4 D3 D2 D1 D0 KCP11 KCP10 General purpose register K10 input comparison register Constantly 0 when being read Reserved register 1 1 R W R W 1 Falling edge 0 Rising e...

Page 31: ...D5 D4 D3 D2 D1 D0 HZR51 HZR50 HZR4H HZR4L HZR1H HZR1L HZR0H HZR0L R51 high impedance control R50 high impedance control General purpose register General purpose register General purpose register General purpose register General purpose register General purpose register Reserved register 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W Hi Z 1 Output 0 00FF71 D7 D6 D5 D4 D3 D2 D1 D0 HZR27 HZR26 HZR25...

Page 32: ...ister 00FF76 2 D7 D6 D5 D4 D3 D2 D1 D0 R37D R36D R35D R34D R33D R32D R31D R30D General purpose register General purpose register General purpose register R34 output port data General purpose register General purpose register General purpose register General purpose register 1 1 1 1 1 1 1 1 R W R W R W R W R W R W R W R W 1 High 1 0 Low 0 00FF78 D7 D6 D5 D4 D3 D2 D1 D0 R51D R50D R51 output port dat...

Page 33: ...Since WDRST is for writing only it is constantly set to 0 during readout 5 2 4 Programming notes 1 The watchdog timer must reset within 3 second cycles by software 2 Do not execute the SLP instruction for 2 msec after a NMI interrupt has occurred when fOSC1 is 32 768 kHz Table 5 2 3 1 Watchdog timer control bits timer Fig 5 2 1 1 Block diagram of watchdog timer By running watchdog timer reset duri...

Page 34: ...e CPU operating clock and OSC3 oscillation circuit is in a stopped state ON OFF switching of the OSC3 oscillation circuit and switching of the system clock between OSC1 and OSC3 are control led in software OSC3 circuit is utilized when high speed operation of the CPU and some peripheral circuits become necessary Otherwise OSC1 should be used to generate the operating clock and OSC3 circuit placed ...

Page 35: ...3 5 Operating mode You can select three types of operating modes using software to obtain a stable operation and good characteristics operating frequency and current consumption over a broad operation voltage Here below are indicated the features of the respective modes Normal mode VDD 2 4 V 5 5 V This mode is set following the initial reset It permits the OSC3 oscillation circuit Max 4 2 MHz to b...

Page 36: ...s case since several 100 µsec to several 10 msec are necessary for the oscillation to stabilize after turning the OSC3 oscillation circuit ON you should switch over the clock after stabilization time has elapsed The oscillation start time will vary somewhat depending on the oscilla tor and on the externally attached parts Refer to the oscillation start time example indicated in Chapter 7 ELECTRICA...

Page 37: ...Hz 8 2 MHz VD1 2 2 V 1 3 V 3 3 V VDC1 0 0 1 VDC0 0 1 Normal mode Low power mode High speed mode Max Max Max Operating mode Power voltage The VD1 voltage is the value where VSS has been made the standard GND At initial reset this register is set to 0 normal mode OSCC 00FF02H D2 Controls the ON and OFF settings of the OSC3 oscillation circuit When 1 is written OSC3 oscillation ON When 0 is written O...

Page 38: ...n circuit ON status as this will cause faulty operation 3 When turning ON the OSC3 oscillation circuit after switching the operating mode you should allow a minimum waiting time of 5 msec 4 Since several 100 µsec to several 10 msec are necessary for the oscillation to stabilize after turning the OSC3 oscillation circuit ON Consequently you should switch the CPU operating clock OSC1 OSC3 after allo...

Page 39: ...e direct K06 With resistor Gate direct K07 With resistor Gate direct K10 With resistor Gate direct Input ports K00 K07 and K10 are all equipped with pull up resistors The mask option can be used to select With resistor or Gate direct for each port bit The With resistor option is rendered suitable for purposes such as push switch or key matrix input When changing the input terminal from LOW level t...

Page 40: ...l registers for the above and on operations subsequent to interrupt generation see 5 14 Interrupt and Standby Status The exception processing vectors for each interrupt factor are set as follows K10 input interrupt 00000AH K04 K07 input interrupt 00000CH K00 K03 input interrupt 00000EH Figure 5 4 3 1 shows the configuration of the input interrupt circuit Data bus K00 Input comparison register KCP0...

Page 41: ...een the input terminal data K01 K03 where interrupt is permitted and the data from the input comparison registers KCP01 KCP03 generates an interrupt In line with the explanation above since the change in the contents of input data and input comparison registers KCP from a conformity state to a non conformity state introduces an interrupt generation condition switching from one non conformity state...

Page 42: ...le 0 Disable 00FF53 D7 D6 D5 D4 D3 D2 D1 D0 KCP11 KCP10 General purpose register K10 input comparison register Constantly 0 when being read Reserved register 1 1 R W R W 1 Falling edge 0 Rising edge 00FF52 D7 D6 D5 D4 D3 D2 D1 D0 KCP07 KCP06 KCP05 KCP04 KCP03 KCP02 KCP01 KCP00 K07 input comparison register K06 input comparison register K05 input comparison register K04 input comparison register K0...

Page 43: ...timer interrupt priority register Clock timer interrupt priority register 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W PK01 PSIF1 PSW1 PTM1 1 1 0 0 PK00 PSIF0 PSW0 PTM0 1 0 1 0 Priority level Level 3 Level 2 Level 1 Level 0 00FF21 D7 D6 D5 D4 D3 D2 D1 D0 PPT1 PPT0 PK11 PK10 Programmable timer interrupt priority register K10 interrupt priority register Constantly 0 when being read 0 0 0 0 R W R ...

Page 44: ...t will be generated to the CPU Regardless of the interrupt enable register and interrupt priority register settings the interrupt factor flag will be set to 1 by the occurrence of an interrupt generation condition To accept the subsequent interrupt after interrupt generation re setting of the interrupt flags set interrupt flag to lower level than the level indicated by the interrupt priority regis...

Page 45: ... terminal switches to HIGH VDD level and when 0 is written it switches to LOW VSS level When output is in a high impedance state the data written to the data register is output from the terminal at the instant when output is switched to complementary 5 5 5 Special output Besides normal DC output each output port can also be assigned special output function in software R27 R34 R50 or mask option R2...

Page 46: ...ignal to an external device a FOUT signal divided clock of oscillation clock fOSC1 or fOSC3 can be output from the output port terminal R34 Figure 5 5 5 3 shows the configuration of output port R34 Register R34D Register FOUTON R34 output FOUT signal Fig 5 5 5 3 Configuration of R34 The output control for the FOUT signal is done by the register FOUTON When you set 1 for the FOUTON the FOUT signal ...

Page 47: ...BZON Register BZSHT Register R50D R51 output Mask option Register R51D Fig 5 5 5 5 Configuration of R50 and R51 The output control for the BZ BZ signal is done by the registers BZON BZSHT and BZSTP When you set 1 for the BZON or BZSHT the BZ BZ signal is output from the output port terminal R50 R51 When 0 is set for the BZON or 1 is set for the BZSTP the R50 goes LOW VSS and the R51 goes HIGH VDD ...

Page 48: ...HZR31 HZR30 General purpose register General purpose register General purpose register R34 high impedance control General purpose register General purpose register General purpose register General purpose register 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W 1 Hi Z 1 0 Output 0 Reserved register Reserved register 00FF75 D7 D6 D5 D4 D3 D2 D1 D0 R27D R26D R25D R24D R23D R22D R21D R20D R27 output ...

Page 49: ... timer reset Clock timer Run Stop control 0 when being read This is just R W register on E0C88862 Constantly 0 when being read 0 0 0 0 0 R W R W R W R W W W R W On Reset Reset Run Off No operation No operation Stop FOUT2 0 0 0 0 1 1 1 1 FOUT1 0 0 1 1 0 0 1 1 FOUT0 0 1 0 1 0 1 0 1 Frequency fOSC1 1 fOSC1 2 fOSC1 4 fOSC1 8 fOSC3 1 fOSC3 2 fOSC3 4 fOSC3 8 00FF44 D7 D6 D5 D4 D3 D2 D1 D0 BZSTP BZSHT SH...

Page 50: ...rol PTOUT 00FF30H D2 Controls the TOUT programmable timer output clock signal output When 1 is written TOUT signal output ON When 0 is written TOUT signal output OFF Reading Valid PTOUT is the output control register for TOUT signal When 1 is set to the register the TOUT TOUT signal is output from the output port terminal R27 R26 When 0 is set the R27 goes HIGH VDD and the R26 goes LOW VSS To outp...

Page 51: ...ly stops the one shot buzzer output When 1 is written Forcibly stop When 0 is written No operation Reading Constantly 0 By writing 1 into BZSTP the one shot buzzer output can be stopped prior to the elapsing of the time set with SHTPW Writing 0 is invalid and writing 1 except during one shot output is also invalid When 1 is written to BZSHT and BZSTP simulta neously BZSTP takes precedence and one ...

Page 52: ... the pull up resistor goes ON when the port is in input mode When changing the port terminal from LOW level to HIGH with the built in pull up resistor a delay in the waveform rise time will occur depending on the time constant of the pull up resistor and the load capacitance of the terminal It is necessary to set an appropriate wait time for introduction of an I O port Make this wait time the amou...

Page 53: ...rt P1x to output mode and writing 0 will switch it to input mode At initial reset this register is set to 0 input mode The data registers of I O ports set for the input terminal of serial interface can be used as general purpose registers with read write capabilities which do not affect I O activities of the terminals 5 6 5 Programming note When changing the port terminal from LOW level to HIGH wi...

Page 54: ...rminal Furthermore the settings for the corresponding I O control registers for the I O ports become invalid SIN and SOUT are serial data input and output terminals which function identically in clock synchronous system and asynchronous system SCLK is exclusively for use with clock synchronous system and functions as a synchronous clock input output terminal SRDY is exclusively for use in clock sy...

Page 55: ...his mode a synchronous clock from the external master side serial input output device is utilized and clock synchronous 8 bit serial transfers can be performed with this serial interface as the slave The synchronous clock is input to the SCLK terminal and is utilized by this interface as the synchronous clock Furthermore the SRDY signal indicating the transmit receive ready status is output from t...

Page 56: ...ternally attached parts Refer to the oscillation start time example indicated in Chapter 7 ELEC TRICAL CHARACTERISTICS At initial reset the OSC3 oscillation circuit is set to OFF status Transfer rate bps 9 600 4 800 2 400 1 200 600 300 150 OSC3 oscillation frequency Programmable timer settings fOSC3 3 072 MHz PSC1X 0 1 1 0 1 1 0 1 1 0 1 1 0 1 1 1 1 4 1 1 4 RLD1X 09H 13H 27H 4FH 9FH 4FH 9FH fOSC3 4...

Page 57: ...t is generated when the transmission is completed If there is subsequent data to be transmitted it can be sent using this interrupt In addition TXTRG can be read as the status When set to 1 it indicates transmitting operation and 0 indicates transmitting stop For details on timing see the timing chart which gives the timing for each mode When not transmitting set TXEN to 0 to disable transmitting ...

Page 58: ...g Mode SCLK Data D0 D1 D2 D3 D4 D5 D6 D7 LSB MSB Fig 5 7 6 1 Transfer data configuration using clock synchronous mode Below is a description of initialization when performing clock synchronous transfer transmit receive control procedures and operations With respect to serial interface interrupt see 5 7 8 Interrupt function Initialization of serial interface When performing clock synchronous transf...

Page 59: ...slave mode it waits for the synchronous clock to be input from the SCLK terminal The transmitting data of the shift register shifts one bit at a time at each falling edge of the synchronous clock and is output from the SOUT terminal When the final bit MSB is output the SOUT terminal is maintained at that level until the next transmitting begins The transmitting complete interrupt factor flag FSTRA...

Page 60: ...to be input from the SCLK terminal The received data input from the SIN terminal is successively incorporated into the shift register in synchronization with the rising edge of the synchronous clock At the point where the data of the 8th bit has been incorporated at the final 8th rising edge of the synchronous clock the content of the shift register is sent to the received data buffer and the rece...

Page 61: ...atus such as during transmit receive operation The SRDY signal changes the 1 to 0 immedi ately after writing 1 into the transmit control bit TXTRG or the receive control bit RXTRG and returns from 0 to 1 at the point where the first synchronous clock has been input falling edge When you have set in the master mode control the transfer by inputting the same signal from the slave side using the inpu...

Page 62: ...must be written to the serial interface enable register ESIF in order to set these terminals for serial interface use SCLK and SRDY terminals set in the clock synchronous mode are not used in the asynchro nous mode These terminals function as I O port terminals P12 and P13 3 Setting of transfer mode Select the asynchronous mode by writing the data as indicated below to the two bits of the mode sel...

Page 63: ...l bit TXTRG and start transmitting This control causes the shift clock to change to enable and a start bit LOW is output to the SOUT terminal in synchronize to its rising edge The transmitting data set to the shift register is shifted one bit at a time at each rising edge of the clock thereafter and is output from the SOUT terminal After the data output it outputs a stop bit HIGH and HIGH level is...

Page 64: ... point When an overrun error is generated the interrupt factor flag FSREC is not set to 1 and a receiving complete interrupt is not generated If with parity check has been selected a parity check is executed when data is transferred into the received data buffer from the shift register and if a parity error is detected the error inter rupt factor flag is set to 1 When the interrupt has been enable...

Page 65: ...ne with the stop bit set at 0 the serial interface judges the synchronization to be off and a framing error is generated When this error is generated the framing error flag FER and the error interrupt factor flag FSERR are set to 1 When interrupt has been enabled an error interrupt is generated at this point The FER flag is reset to 0 by writing 1 Even when this error has been generated the receiv...

Page 66: ...ters PSIF0 and PSIF1 For details on the above mentioned interrupt control register and the operation following generation of an interrupt see 5 14 Interrupt and Standby Status Figure 5 7 8 1 shows the configuration of the serial interface interrupt circuit Transmitting complete interrupt This interrupt factor is generated at the point where the sending of the data written into the shift register h...

Page 67: ...pt factor flag FSREC is set to 1 The interrupt factor flag FSREC is reset to 0 by writing 1 The generation of this interrupt factor permits the received data to be read Also the interrupt factor flag is set to 1 when a parity error or framing error is generated The exception processing vector address for this interrupt factor is set at 000012H Error interrupt This interrupt factor is generated at ...

Page 68: ...arity error flag Overrun error flag Receive trigger status Receive enable Transmit trigger status Transmit enable 0 when being read Only for asynchronous mode 0 0 0 0 0 0 0 R W R W R W R W R W R W R W Error Reset 0 Error Reset 0 Error Reset 0 Run Trigger Enable Run Trigger Enable No error No operation No error No operation No error No operation Stop No operation Disable Stop No operation Disable R...

Page 69: ...a is considered to be the parity bit and a parity check is executed A parity bit is added to the transmitting data When 0 is written neither checking is done nor is a parity bit added Parity is valid only in asynchronous mode and the EPR setting becomes invalid in the clock synchro nous mode At initial reset EPR is set to 0 non parity SMD1 SMD0 Mode 1 1 0 0 1 0 1 0 Asynchronous system 8 bit Asynch...

Page 70: ...ding Valid When 1 is written to RXEN the serial interface shifts to the receiving enable status and shifts to the receiving disable status when 0 is written Set RXEN to 0 when making the initial settings of the serial interface and similar operations At initial reset RXEN is set to 0 receiving disable RXTRG 00FF49H D3 Functions as the receiving start trigger or prepara tion for the following data ...

Page 71: ...es the generation of an overrun error and becomes 1 when an error has been generated An overrun error is generated when the receiving of data has been completed prior to the writing of 1 to RXTRG in the asynchronous mode OER is reset to 0 by writing 1 At initial reset and when RXEN is 0 OER is set to 0 no error PER 00FF49H D5 Indicates the generation of a parity error When 1 is read Error When 0 i...

Page 72: ...ecessary The interrupt factor flag is reset to 0 by writing 1 At initial reset this flag is reset to 0 5 7 10 Programming notes 1 Be sure to initialize the serial interface mode in the transmitting receiving disable status TXEN RXEN 0 2 Do not perform double trigger writing 1 to TXTRG RXTRG when the serial interface is in the transmitting receiving operation Further more do not execute the SLP ins...

Page 73: ... FTM8 FTM2 and FTM1 at the falling edge of the 32 Hz 8 Hz 2 Hz and 1 Hz signals to 1 Interrupt can be prohibited by the setting the interrupt enable registers ETM32 ETM8 ETM2 and ETM1 corre sponding to each interrupt factor flag In addition a priority level of the clock timer interrupt for the CPU can be optionally set at levels 0 to 3 by the interrupt priority registers PTM0 and PTM1 For details ...

Page 74: ... factor flag FTM32 Address Interrupt enable register ETM32 Address 8 Hz falling edge Interrupt factor flag FTM8 Address Interrupt enable register ETM8 Address 2 Hz falling edge Interrupt factor flag FTM2 Address Interrupt enable register ETM2 Interrupt priority level judgement circuit Address Interrupt priority register PTM0 PTM1 Address 1 Hz falling edge Interrupt factor flag FTM1 Address Interru...

Page 75: ...M1 PTM0 K00 K07 interrupt priority register Serial interface interrupt priority register Stopwatch timer interrupt priority register Clock timer interrupt priority register 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W PK01 PSIF1 PSW1 PTM1 1 1 0 0 PK00 PSIF0 PSW0 PTM0 1 0 1 0 Priority level Level 3 Level 2 Level 1 Level 0 00FF22 D7 D6 D5 D4 D3 D2 D1 D0 ESW100 ESW10 ESW1 ETM32 ETM8 ETM2 ETM1 Stop...

Page 76: ... settings At initial reset this register is set to 0 level 0 ETM1 ETM2 ETM8 ETM32 00FF22H D0 D3 Enables or disables the generation of an interrupt for the CPU When 1 is written Interrupt enabled When 0 is written Interrupt disabled Reading Valid The ETM1 ETM2 ETM8 and ETM32 are interrupt enable registers that respectively correspond to the interrupt factors for 1 Hz 2 Hz 8 Hz and 32 Hz Interrupts ...

Page 77: ...ounter is incremented 1 The TMRUN maintains 1 for reading until the timer actually shifts to STOP status Figure 5 8 4 1 shows the timing chart of the RUN STOP control Fig 5 8 4 1 Timing chart of RUN STOP control 2 The SLP instruction is executed when the clock timer is in the RUN status TMRUN 1 The clock timer operation will become unstable when returning from SLEEP status Therefore when shifting ...

Page 78: ...er SWD4 SWD7 generates a 1 Hz signal by counting the approximate 10 Hz signal generated by the 1 100 sec counter at 25 256 sec and 26 256 sec intervals in 4 6 ratios The count up is made approximately 1 10 sec counting by 25 256 sec and 26 256 sec intervals 5 9 2 Count up pattern The stopwatch timer is respectively composed of the 4 bit BCD counters SWD0 SWD3 and SWD4 SWD7 Data bus Interrupt reque...

Page 79: ...pt control registers and the operation following generation of an interrupt see 5 14 Interrupt and Standby Status The exception processing vector addresses of each interrupt factor are respectively set as shown below 100 Hz interrupt 000016H 10 Hz interrupt 000018H 1 Hz interrupt 00001AH Figure 5 9 3 2 shows the timing chart for the stopwatch timer SWD0 SWD1 SWD2 SWD3 100 Hz interrupt 10 Hz interr...

Page 80: ...PK01 PSIF1 PSW1 PTM1 1 1 0 0 PK00 PSIF0 PSW0 PTM0 1 0 1 0 Priority level Level 3 Level 2 Level 1 Level 0 00FF22 D7 D6 D5 D4 D3 D2 D1 D0 ESW100 ESW10 ESW1 ETM32 ETM8 ETM2 ETM1 Stopwatch timer 100 Hz interrupt enable register Stopwatch timer 10 Hz interrupt enable register Stopwatch timer 1 Hz interrupt enable register Clock timer 32 Hz interrupt enable register Clock timer 8 Hz interrupt enable reg...

Page 81: ...ttings PSW1 PSW0 Interrupt priority level 1 1 0 0 1 0 1 0 Level 3 IRQ3 Level 2 IRQ2 Level 1 IRQ1 Level 0 None At initial reset this register is set to 0 level 0 ESW1 ESW10 ESW100 00FF22H D4 D5 D6 Enables or disables the generation of an interrupt for the CPU When 1 is written Interrupt enabled When 0 is written Interrupt disabled Reading Valid The ESW1 ESW10 and ESW100 are interrupt enable registe...

Page 82: ...e counter is incremented 1 The SWRUN maintains 1 for reading until the timer actually shifts to STOP status Figure 5 9 5 1 shows the timing chart of the RUN STOP control SWRUN WR SWDX 27 28 29 30 31 32 SWRUN RD 256 Hz Fig 5 9 5 1 Timing chart of RUN STOP control 2 The SLP instruction is executed when the stopwatch timer is in the RUN status SWRUN 1 The stopwatch timer operation will become unstabl...

Page 83: ...and 1 each have a down counter and reload data register The reload data registers RLD00 RLD07 timer 0 and RLD10 RLD17 timer 1 are registers that set the initial value of the counter By writing 1 to the preset control bit PSET0 timer 0 or PSET1 timer 1 the down counter loads the initial value set in the reload register RLD Therefore down counting is executed from the stored initial value according ...

Page 84: ...UN1 timer 1 This mode is suitable for single time measurement for example The registers PRUN0 timer 0 and PRUN1 timer 1 are provided to control the RUN STOP for timers 0 and 1 After the reload data has been preset into the counter down counting is begun by writing 1 to this register When 0 is written the clock input is prohibited and the count stops The control of this RUN STOP has no affect on th...

Page 85: ...e input clock for each by dividing the source clock signal from the OSC1 or OSC3 oscillation circuit The source clock and the dividing ratio of the prescaler can be selected individually for timer 0 and timer 1 in software The input clocks are set by the below sequence 1 Selection of source clock Select the source clock OSC1 or OSC3 for each prescaler This is done with the source clock selection r...

Page 86: ... n 2 n 3 EVIN input K10 2 048 Hz When 0 is set into register PLPOL Fig 5 10 5 2 Count down timing with noise rejecter The event counter mode is the same as the timer mode except that the clock is external EVIN See 5 10 2 Count operation and setting basic mode for the basic operation and control 5 10 6 Pulse width measurement timer mode Timer 0 includes a pulse width measurement function that measu...

Page 87: ...terrupt flag In addition a priority level of the programmable timer interrupt for the CPU can be optionally set at levels 0 to 3 by the interrupt priority registers PPT0 and PPT1 For details on the above mentioned interrupt control registers and the operation following generation of an interrupt see 5 14 Interrupt and Standby Status The exception processing vector addresses of each interrupt facto...

Page 88: ... Example of transmission rate setting The output control for the TOUT TOUT signal is done by the register PTOUT When you set 1 for the PTOUT the TOUT TOUT signal is output from the R27 R26 output port terminal When 0 is set the R27 goes HIGH VDD and the R26 goes LOW VSS To output the TOUT signal 1 must always be set for the data register R27D The data register R26D does not affect the TOUT output ...

Page 89: ...surement With noise rejector Rising edge of K10 input High level measurement for K10 input Continuous Preset Run Timer Normal mode Without noise rejector Falling edge of K10 input Low level measurement for K10 input One shot No operation Stop In timer mode In event counter mode Down count timing in event counter mode In pulse width measurement mode PSC01 1 1 0 0 PSC00 1 0 1 0 Prescaler dividing ra...

Page 90: ...SB 1 1 1 1 1 1 1 1 R R R R R R R R High Low 00FF36 00FF21 D7 D6 D5 D4 D3 D2 D1 D0 PPT1 PPT0 PK11 PK10 Programmable timer interrupt priority register K10 interrupt priority register Constantly 0 when being read 0 0 0 0 R W R W R W R W PPT1 PK11 1 1 0 0 PPT0 PK10 1 0 1 0 Priority level Level 3 Level 2 Level 1 Level 0 D7 D6 D5 D4 D3 D2 D1 D0 00FF25 D7 D6 D5 D4 D3 D2 D1 D0 FPT1 FPT0 FK1 FK0H FK0L FSER...

Page 91: ...en 1 is written to EVCNT the event counter mode is selected and when 0 is written the timer mode is selected At initial reset EVCNT is set to 0 timer mode FCSEL 00FF31H D6 Selects the function for each counter mode of timer 0 In timer mode When 1 is written Pulse width measurement timer mode When 0 is written Normal mode Reading Valid In the timer mode select whether timer 0 will be used as a puls...

Page 92: ...o 0 when the counter underflow is generated At initial reset this register is set to 0 one shot mode RLD00 RLD07 00FF33H RLD10 RLD17 00FF34H Sets the initial value for the counter RLD00 RLD07 Reload data for Timer 0 RLD10 RLD17 Reload data for Timer 1 The reload data set in this register is loaded into the respective counters and is counted down with that as the initial value Reload data is loaded...

Page 93: ...not affect the TOUT output At initial reset PTOUT is set to 0 DC output The TOUT signal can be output from R26 only when the function is selected by mask option PPT0 PPT1 00FF21H D2 D3 Sets the priority level of the programmable timer interrupt The two bits PPT0 and PPT1 are the interrupt priority register corresponding to the programma ble timer interrupt Table 5 10 10 3 shows the interrupt prior...

Page 94: ...is turning ON until oscillation stabilizes an interval of several 100 µsec to several 10 msec is necessary Consequently you should allow an adequate waiting time after turning the OSC3 oscillation circuit ON before starting the count of the programmable timer The oscillation start time will vary somewhat depending on the oscillator and on external parts Refer to the oscillation start time example ...

Page 95: ...d select the default setting of 1 32 1 16 duty a VC2 standard 5 11 2 Mask option The drive duty for the built in LCD driver can be selected whether it will be 1 32 and 1 16 software switched or fixed at 1 8 by the mask option VC2 VC3 VC4 VC5 CA CB CC CD CE CF CG VSS VC1 LC3 LC2 LC1 LC0 DTFNT VC1 VC3 VC5 LCDC1 LCDC0 LDUTY DSPAR VC2 LCD system voltage booster reducer LCD system voltage regulator LCD...

Page 96: ... maximum 1 632 dots in the E0C88832 and 41 segments 32 commons maximum 1 312 dots in the E0C88862 can be driven When 1 16 duty is selected the combined com mon segment output terminal is switched to the segment terminal An LCD panel with 67 segments 16 commons maximum 1 072 dots in the E0C88832 and 57 segments 16 commons maximum 912 dots in the E0C88862 can be driven When 1 8 duty is selected the ...

Page 97: ...COM1 COM2 SEG0 SEG1 COM0 SEG0 COM0 SEG1 COM0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 SEG0 1 2 3 4 32 Hz VDD VSS VC5 VC4 VC3 VC2 VC1 VSS VC5 VC4 VC3 VC2 VC1 VSS VC5 VC4 VC3 VC2 VC1 VSS VC5 VC4 VC3 VC2 VC1 VSS VC5 VC4 VC3 VC2 VC1 VSS VC5 VC4 VC3 VC2 VC1 VSS GND VC5 VC4 VC3 VC2 VC1 VSS GND VC1 VC2 VC3 VC4 VC5 VC1 VC2 VC3 VC4 VC5 ...

Page 98: ... 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SEG0 1 2 3 4 15 3 2 1 0 15 3 2 1 0 FR COM0 COM1 COM2 SEG0 SEG1 COM0 SEG0 COM0 SEG1 32 Hz VDD VSS VC5 VC4 VC3 VC2 VC1 VSS VC5 VC4 VC3 VC2 VC1 VSS VC5 VC4 VC3 VC2 VC1 VSS VC5 VC4 VC3 VC2 VC1 VSS VC5 VC4 VC3 VC2 VC1 VSS VC5 VC4 VC3 VC2 VC1 VSS GND VC5 VC4 VC3 VC2 VC1 VSS GND VC1 VC2 VC3 VC4 VC5 VC1 VC2 VC3 VC4 VC5 ...

Page 99: ...ction register DTFNT when 0 is written to DTFNT 5 8 dots is selected and when 1 is written 5 5 dots is selected The correspondence between the display memory bits set according to the drive duty and font size and the common segment terminals are shown in Figures 5 11 5 1 5 11 5 6 When 1 is written to the display memory bit corresponding to the dot on the LCD panel the dot goes ON and when 0 is wri...

Page 100: ...5 46 47 48 49 50 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 0 1 2 3 4 D0 D1 D2 D3 D4 D5 D6 D7 Display area D0 D1 D2 D3 D4 D5 D6 D7 Display area D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 Display area D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 SEG COM 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1...

Page 101: ... 50 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 0 1 2 3 4 D0 D1 D2 D3 D4 D5 D6 D7 Display area D0 D1 D2 D3 D4 D5 D6 D7 Display area D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 Display area D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 SEG COM 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23...

Page 102: ...4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 0 1 2 3 4 D0 D1 D2 D3 D4 D5 D6 D7 Display area 0 when 0 is set into DSPAR D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 SEG COM 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14...

Page 103: ...8 9 A B C D E F 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 0 1 2 3 4 D0 D1 D2 D3 D4 D5 D6 D7 Display area 0 when 0 is set into DSPAR D0 D1 D2 D3 D4 D5 D6 D7 Display area 0 when 0 is set into DSPAR D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 Display area 1 when 1 is set into DSPAR D0 D1 D2 D3 D4 D5 D6 D7 Display area 1 when 1 is set into DSPAR D0 D1 D2 D3 D4 D5 D6 D7 ...

Page 104: ...9 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 0 1 2 3 4 D0 D1 D2 D3 D4 D5 D6 D7 Display area 0 when 0 is set into DSPAR D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 SEG COM 0 1 2 3 4 5...

Page 105: ... 62 63 64 65 66 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 0 1 2 3 4 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 SEG COM 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 Display area 0 when 0 is set into DSPAR Display area 0 w...

Page 106: ...is dynamic drive you can brink the entire LCD display without changing display memory data LCDC1 LCDC0 LCD display 1 1 0 0 1 0 1 0 All LCDs lit Static All LCDs out Dynamic Normal display Drive OFF LC3 LC0 Contrast 1 1 1 0 0 0 1 0 1 0 1 0 Dark Light LC1 1 1 0 1 0 0 LC2 1 1 1 0 0 0 Selecting LCD drive OFF turns the LCD drive power circuit OFF and all the VC1 VC5 terminals go to VSS level However if ...

Page 107: ...ected and the combined common segment output terminal is switched to the common termi nal When 1 is written to LDUTY 1 16 duty is selected and the combined common segment output terminal is switched to the segment terminal When 1 8 duty is selected by the mask option the combined common segment terminals are fixed to the segment terminals and the setting of LDUTY becomes invalid The correspondence...

Page 108: ...n be made without changing the display memory data At initial reset and in the SLEEP status this register is set to 0 drive off LC0 LC3 00FF11H D0 D3 Adjusts the LCD contrast Table 5 11 7 3 LCD contract adjustment LCDC1 LCDC0 LCD display 1 1 0 0 1 0 1 0 All LCDs lit Static All LCDs out Dynamic Normal display Drive OFF LC3 LC0 Contrast 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0...

Page 109: ...or BZ R51 Dividing circuit 256 Hz Envelope addition circuit Programmable dividing circuit BZFQ0 BZFQ2 DUTY0 DUTY2 Duty ratio control circuit ENRTM BZON ENON ENRST OSC1 oscillation circuit fOSC1 BZSHT One shot buzzer control circuit SHTPW BZSTP Buzzer output control circuit Output port R50 R51 BZ R50 Available when selected by mask option BZ signal R S Q One shot time up R50 output Register BZSTP R...

Page 110: ...l 7 Level 8 Min 12 28 11 28 10 28 9 28 8 28 7 28 6 28 5 28 4096 0 2048 0 3276 8 1638 4 2730 7 1365 3 2340 6 1170 3 DUTY0 DUTY2 DUTY1 8 20 7 20 6 20 5 20 4 20 3 20 2 20 1 20 0 1 0 1 0 1 0 1 0 0 0 0 1 1 1 1 8 16 7 16 6 16 5 16 4 16 3 16 2 16 1 16 12 24 11 24 10 24 9 24 8 24 7 24 6 24 5 24 0 0 1 1 0 0 1 1 Duty ratio by buzzer frequencies Hz Level 1 MAX Level 2 Level 3 Level 4 Level 5 Level 6 Level 7 ...

Page 111: ...onization with 256 Hz signal by writing 1 to the one shot forced stop bit BZSTP Since the one shot output has a short duration an envelope cannot be added When 1 is written to BZSHT ENON is automatically reset to 0 Consequently only the frequency and sound level can be set for one shot output The control for the one shot output is invalid during normal buzzer output Figure 5 12 5 1 shows the timin...

Page 112: ... can be selected from among the above 8 types that have divided the OSC1 clock At initial reset this register is set at 0 4096 0 Hz Address Bit Name SR R W Function Comment 1 0 00FF44 D7 D6 D5 D4 D3 D2 D1 D0 BZSTP BZSHT SHTPW ENRTM ENRST ENON BZON One shot buzzer forcibly stop One shot buzzer trigger status One shot buzzer duration width selection Envelope attenuation time Envelope reset Envelope ...

Page 113: ...2 5 msec 7 437 5 msec Reading Valid The attenuation time of the digital envelope is determined by the time for changing the duty ratio The duty ratio is changed in 125 msec 8 Hz units when 1 is written to ENRTM and in 62 5 msec 16 Hz units when 0 is written This setting becomes invalid when an envelope has been set to OFF ENON 0 At initial reset ENRTM is set to 0 0 5 sec SHTPW 00FF44H D4 Selects t...

Page 114: ...tput from R51 only when the function is selected by mask option BZSTP 00FF44H D6 Forcibly stops the one shot buzzer output When 1 is written Forcibly stop When 0 is written No operation Reading Constantly 0 By writing 1 into BZSTP the one shot buzzer output can be stopped prior to the elapsing of the time set with SHTPW Writing 0 is invalid and writing 1 except during one shot output is also inval...

Page 115: ... instruction while the SVD circuit is operating the stop operation of the OSC1 oscillation circuit is kept waiting until the sampling is completed The two bits of SVDON and SVDSP are automatically reset to 0 by hardware while waiting for completion of sampling To reduce current consumption turn the SVD circuit OFF when it is not necessary Detection result The SVD circuit A D converts the supply vo...

Page 116: ...nuous sampling and the result in SVD0 SVD3 is updated every 4 seconds Cancellation of 1 4 Hz auto sampling is done by writing 0 to SVDSP If the SVD circuit is sampling SVD circuit waits until completion and then turns OFF In addition 1 is read from SVDON while the SVD circuit is sampling Figure 5 13 2 2 shows the timing chart of the 1 4 Hz auto sampling Timing of sampling Next we will explain the ...

Page 117: ...ming chart of the initial reset signal generation Example when using 1 4 Hz auto sampling Supply voltage Internal initial reset SVDON R SVD3 SVD2 SVD1 SVD0 Level 2 Level 0 Reset status 4 sec Fig 5 13 2 3 Timing chart of the initial reset signal generation 5 13 3 Control of SVD circuit Table 5 13 3 1 shows the SVD circuit control bits Table 5 13 3 1 SVD circuit control bits Address Bit Name SR R W ...

Page 118: ...ial reset and in the SLEEP status SVDSP is set to 0 auto sampling OFF SVD0 SVD3 00FF12H D0 D3 The detection result of the SVD is set The reading data correspond to the detection levels as shown in Table 5 13 3 2 and the data is main tained until the next sampling Table 5 13 3 2 Supply voltage detection results For the correspondence between the detection level and the supply voltage see 7 ELECTRIC...

Page 119: ...rupt priority register has been provided for each system of interrupts and the priority of interrupt processing can be set to 3 levels in each system Figure 5 14 1 shows the configuration of the interrupt circuit Refer to the explanations of the respective periph eral circuits for details on each interrupt Fig 5 14 1 Configuration of interrupt circuit FTM32 ETM32 32 Hz FTM8 ETM8 8 Hz FTM2 ETM2 2 H...

Page 120: ...terrupts of the 6 systems and the CPU accepts only interrupts above the level that has been indicated with the interrupt flags I0 and I1 Consequently the following three conditions are necessary for the CPU to accept the interrupt 1 The interrupt factor flag has been set to 1 by generation of an interrupt factor 2 The interrupt enable register corresponding to the above has been set to 1 3 The int...

Page 121: ...ty levels The interrupt priority level between each system can optionally be set to three levels by the interrupt priority register However when more than one system is set to the same priority level they are processed according to the default priority level Table 5 14 4 2 Setting of interrupt priority level Table 5 14 3 1 Interrupt enable registers and interrupt factor flags Table 5 14 4 1 Interr...

Page 122: ...Table 5 14 5 1 Vector address and exception processing correspondence The set interrupt flags are reset to their original value on return from the interrupt processing routine Consequently multiple interrupts up to 3 levels can be controlled by the initial settings of the interrupt priority registers alone Additional multiplexing can be realized by rewriting the interrupt flags and interrupt enabl...

Page 123: ...t enable register 0 when being read 0 0 0 0 0 0 0 R W R W R W R W R W R W R W Interrupt enable Interrupt disable D7 D6 D5 D4 D3 D2 D1 D0 00FF24 D7 D6 D5 D4 D3 D2 D1 D0 FSW100 FSW10 FSW1 FTM32 FTM8 FTM2 FTM1 Stopwatch timer 100 Hz interrupt factor flag Stopwatch timer 10 Hz interrupt factor flag Stopwatch timer 1 Hz interrupt factor flag Clock timer 32 Hz interrupt factor flag Clock timer 8 Hz inte...

Page 124: ...ne 2 Beware If the interrupt flags I0 and I1 have been rewritten set to lower priority prior to resetting an interrupt factor flag after an interrupt has been generated the same interrupt will be generated again 3 An exception processing vector is fixed at 2 bytes so it cannot specify a branch destination bank address Consequently to branch from multiple banks to a common exception process ing rou...

Page 125: ...it systems operation can be controlled and their control registers instructions are explained You should refer to these when programming See Chapter 7 ELECTRICAL CHARACTERIS TICS for the current consumption Table 5 15 1 Circuit systems and control registers Circuit type CPU Oscillation circuit Operating mode LCD controller SVD circuit Status at time of initial resetting Operation status OSC1 clock...

Page 126: ...tor for RESET terminal 0 1 µF 0 1 µF 0 1 µF 0 1 µF 0 1 µF 0 1 µF 0 1 µF 3 3 µF 0 47 µF N C E0C88832 88862 LCD panel 51 41 x 32 VSS VOSC OSC1 OSC2 OSC3 OSC4 VD1 VC1 VC2 VC3 VC4 VC5 CA CB CC CD CE CF CG RESET VDD TEST K00 K01 K02 K03 K04 K05 K06 K07 K10 R26 TOUT R27 TOUT R34 FOUT R51 BZ P10 SIN P11 SOUT P12 SCLK P13 SRDY P14 P15 P16 P17 CG2 CG1 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 X tal1 Rf Cres 3 V CP R5...

Page 127: ...d VC5 Booster reducer capacitors Booster reducer capacitors Booster reducer capacitors Capacitor for power supply Capacitor for RESET terminal Protection resistance 0 1 µF 0 1 µF 0 1 µF 0 1 µF 0 1 µF 0 1 µF 0 1 µF 0 1 µF 3 3 µF 0 47 µF 100 Ω E0C88832 88862 LCD panel 51 41 x 32 K00 K01 K02 K03 K04 K05 K06 K07 K10 R26 TOUT R27 TOUT R34 FOUT R51 BZ P10 SIN P11 SOUT P12 SCLK P13 SRDY P14 P15 P16 P17 S...

Page 128: ...speed mode Liquid crystal power voltage Capacitor between VD1 and VSS Capacitor between VC1 and VSS Capacitor between VC2 and VSS Capacitor between VC3 and VSS Capacitor between VC4 and VSS Capacitor between VC5 and VSS Capacitor between CA and CB Capacitor between CA and CC Capacitor between CD and CE Capacitor between CF and CG VDD VDD VDD fOSC1 fOSC3 fOSC1 fOSC1 fOSC3 VC5 C1 C2 C3 C4 C5 C6 C7 C...

Page 129: ... Input leak current Output leak current Input pull up resistance Input terminal capacitance Segment Common output current VIH1 VIL1 VIH2 VIH2 VIH2 VIL2 VIL2 VIL2 VT VT IOH IOL ILI ILO RIN CIN ISEGH ISEGL 0 8VDD 0 1 6 1 0 2 4 0 0 0 0 5VDD 0 1VDD 0 5 1 1 100 5 300 7 VDD 0 2VDD VDD VDD VDD 0 6 0 3 0 9 0 9VDD 0 5VDD 0 5 1 1 500 15 5 V V V V V V V V V V mA mA µA µA kΩ pF µA µA Kxx Pxx Kxx Pxx OSC3 OSC1...

Page 130: ...wise specified VDD VC2 LCX FH 0 1 to 5 5 V VSS 0 V Ta 25 C C1 C10 0 1 µF LCX 0H LCX 1H LCX 2H LCX 3H LCX 4H LCX 5H LCX 6H LCX 7H LCX 8H LCX 9H LCX AH LCX BH LCX CH LCX DH LCX EH LCX FH VC2 VC5 TYPE A Note 1 Fixing the LCD contrast is not recommended A contrast adjustment function should be included in the software Item Symbol Min Typ Max Unit Condition LCD drive voltage Typ 0 94 0 412VC5 4 20 4 34...

Page 131: ... FH VC2 VC5 TYPE C Note 1 Fixing the LCD contrast is not recommended A contrast adjustment function should be included in the software Item Symbol Min Typ Max Unit Condition LCD drive voltage Typ 0 94 0 260VC5 3 80 3 88 3 96 4 03 4 15 4 22 4 30 4 38 4 45 4 53 4 65 4 72 4 80 4 88 4 95 5 07 Typ 1 06 V V V V V V V V V V V V V V V V V When 1 MΩ load resistor is connected between VSS and VC1 no panel l...

Page 132: ...evel 9 Level 8 Level 10 Level 9 Level 11 Level 10 Level 12 Level 11 Level 13 Level 12 Level 14 Level 13 Level 15 Level 14 Note 1 1 1 2 2 2 3 3 3 4 4 4 4 4 4 VSVD Level 0 VSVD Level 1 VSVD Level 2 VSVD Level 3 VSVD Level 4 VSVD Level 5 VSVD Level 6 VSVD Level 7 VSVD Level 8 VSVD Level 9 VSVD Level 10 VSVD Level 11 VSVD Level 12 VSVD Level 13 VSVD Level 14 VSVD Level 15 Unless otherwise specified VD...

Page 133: ... Non heavy load protection mode C1 C10 0 1 µF No panel load 1 2 3 4 1 2 3 1 2 3 5 1 2 3 4 5 1 2 3 4 OSC1 Stop OSC1 Oscillating OSC1 Oscillating OSC1 Oscillating See 7 8 Characteristics Curves for current consumption with an operating frequency other than 4 MHz OSC1 Oscillating See 7 8 Characteristics Curves for current consumption with an operating frequency other than 8 MHz The LCD drive circuit ...

Page 134: ...SC1 fOSC3 tcy tcy tcy 30 000 0 03 30 000 30 000 0 03 25 50 75 100 125 150 0 5 1 0 1 4 1 9 2 4 2 9 0 2 0 5 0 7 1 0 1 2 1 5 32 768 32 768 32 768 61 122 183 244 305 366 80 000 4 2 80 000 80 000 8 2 67 133 200 267 333 400 66 7 133 3 200 0 266 7 333 3 400 0 66 7 133 3 200 0 266 7 333 3 400 0 kHz MHz kHz kHz MHz µS µS µS µS µS µS µS µS µS µS µS µS µS µS µS µS µS µS VDD 2 4 to 5 5 V VDD 1 8 to 3 5 V VDD ...

Page 135: ... VIH1 0 8VDD VIL1 0 2VDD VOH 0 8VDD VOL 0 2VDD Item Symbol Min Typ Max Unit Transmitting data output delay time Receiving data input set up time Receiving data input hold time tsmd tsms tsmh µS µS µS Note 10 5 5 Condition VDD 1 8 to 3 5 V VSS 0 V Ta 40 to 85 C VIH1 0 8VDD VIL1 0 2VDD VOH 0 8VDD VOL 0 2VDD Item Symbol Min Typ Max Unit Transmitting data output delay time Receiving data input set up ...

Page 136: ...m inputting the start bit until internal sampling begins operating Time as far as AC is excluded Erroneous start bit detection range time is a logical range to detect whether a LOW level start bit has been input again after a start bit has been detected and the internal sampling clock has started When a HIGH level is detected the start bit detection circuit is reset and goes into a wait status unt...

Page 137: ...Cycle time H pulse width L pulse width Condition VDD 2 4 to 5 5 V VSS 0 V Ta 40 to 85 C VIH2 1 6 V VIL2 0 6 V Item Symbol Min Typ Max Unit OSC3 input clock time Input clock rising time Input clock falling time to3cy to3h to3l tosr tosf nS nS nS nS nS Note 125 62 5 62 5 32 000 16 000 16 000 25 25 Cycle time H pulse width L pulse width Condition VDD 3 5 to 5 5 V VSS 0 V Ta 40 to 85 C VIH2 2 4 V VIL2...

Page 138: ...n Typ Max Unit SCLK input clock time EVIN input clock time With noise rejector EVIN input clock time Without noise rejector Input clock rising time Input clock falling time tsccy tsch tscl tevcy tevh tevl tevcy tevh tevl tckr tckf µS µS µS S S S µS µS µS nS nS Note 2 1 1 64 fOSC1 32 fOSC1 32 fOSC1 2 1 1 25 25 Cycle time H pulse width L pulse width Cycle time H pulse width L pulse width Cycle time ...

Page 139: ...T input time tsr µS Note 100 Item Condition VDD 1 8 to 5 5 V VSS 0 V Ta 40 to 85 C VIH 0 5VDD VIL 0 1VDD Symbol Min Typ Max Unit Operating power voltage RESET input time Vsr tpsr V mS Note 2 4 10 Item Condition VSS 0 V Ta 40 to 85 C Symbol Min Typ Max Unit Stabilization time tvdc mS Note 1 5 Item Condition VDD 1 8 to 5 5 V VSS 0 V Ta 40 to 85 C Note 1 Stabilization time is the time from switching ...

Page 140: ...itor built in is selected by the mask option Min Typ Max tsta f IC 25 100 25 µS RCR constant Oscillation start time Frequency IC deviation Item Symbol Unit Condition Note Unless otherwise specified VDD 1 8 to 5 5 V VSS 0 V Ta 40 to 85 C Min Typ Max Oscillation start time Normal mode Oscillation start time High speed mode tsta tsta 10 10 mS mS 4 0 MHz crystal oscillator 8 0 MHz crystal oscillator 1...

Page 141: ...value High level output current voltage characteristic Low level output current voltage characteristic 0 0 0 1 2 3 4 5 6 7 0 2 0 4 0 6 VDD VOH V VDD 1 8 V VDD 2 4 V VDD 3 5 V I OH mA 0 8 1 0 1 0 7 6 5 4 3 2 1 0 0 8 0 6 0 4 VOL V VDD 1 8 V VDD 2 4 V VDD 3 5 V I OL mA 0 2 0 0 Ta 85 C Min value Ta 85 C Max value ...

Page 142: ...r is connected between VSS and VC5 no panel load Typ value Ta 25 C Typ value 7 0 6 5 6 0 5 5 5 0 4 5 4 0 3 5 3 0 2 5 2 1 5 2 0 2 5 3 0 3 5 VDD V V C5 V 4 0 4 5 5 0 5 5 TYPE A LCx FH TYPE A LCx 0H TYPE C LCx 0H TYPE D LCx 0H TYPE D LCx FH TYPE C LCx FH TYPE B LCx FH TYPE B LCx 0H 1 05VC5 1 04VC5 1 03VC5 1 02VC5 1 01VC5 VC5 0 99VC5 0 98VC5 0 97VC5 0 96VC5 0 95VC5 50 25 0 25 50 75 100 Ta C V C5 V ...

Page 143: ...racteristic LCD drive voltage load characteristic Ta 25 C Typ value LCX 8H Typ value 6 0 5 8 5 6 5 4 5 2 5 0 4 8 4 6 4 4 4 2 4 0 0 2 TYPEB TYPEA 4 6 8 10 IVC5 µA V C5 V TYPED TYPEC 1 05VSVD 1 04VSVD 1 03VSVD 1 02VSVD 1 01VSVD VSVD 0 99VSVD 0 98VSVD 0 97SVD 0 96VSVD 0 95VSVD 50 25 0 25 50 75 100 Ta C V SVD V ...

Page 144: ...operating OSC3 CR oscillation Ta 25 C Ta 25 C 6 5 4 3 2 1 0 0 1 2 3 4 5 6 7 8 fOSC3 MHz I VDD4 mA High speed operating mode MAX Normal mode MAX High speed operating mode TYP Normal mode TYP 5000 4500 4000 3500 3000 2500 2000 1500 1000 500 0 0 10 100 1000 RCR3 kΩ I VDD4 µA Normal mode MAX High speed operating mode MAX Normal mode TYP High speed operating mode TYP ...

Page 145: ...ent temperature characteristic CPU is under 32 768 kHz operation Typ value Typ value 5 0 4 0 3 0 2 0 1 0 0 0 50 25 0 25 50 75 100 Ta C I VDD2 µA Low power operating mode Normal operating mode High speed operating mode 25 0 20 0 15 0 10 0 5 0 0 0 50 25 0 25 50 75 100 Ta C I VDD3 µA Low power operating mode Normal operating mode High speed operating mode ...

Page 146: ... chip plastic package or ceramic package and board capacitance Therefore use the following charts for reference only and select the resistance value after evaluating the actual product The resistance value should be set to RCR3 15 kΩ Oscillation frequency resistor characteristic OSC1 RCR1 800 kΩ Ta 25 C Typ value Oscillation frequency temperature characteristic OSC1 100 10 20 50 200 500 1 000 2 00...

Page 147: ...y resistor characteristic OSC3 Oscillation frequency temperature characteristic OSC3 10 000 1 000 100 10 20 50 100 200 RCR3 kΩ f OSC3 kHz Normal operating mode High speed operating mode 10 000 1 000 50 10 20 30 40 50 60 70 80 90 100 40 30 20 10 0 Ta C f OSC3 kHz 2 000 5 000 Normal operating mode High speed operating mode ...

Page 148: ...C88832 88862 TECHNICAL MANUAL 8 PACKAGE 8 PACKAGE 8 1 Plastic Package QFP8 128pin Unit mm 28 0 1 31 2 0 4 65 96 28 0 1 31 2 0 4 33 64 INDEX 0 35 0 1 32 1 128 97 3 35 0 1 0 1 3 65 max 0 6 0 2 0 10 0 15 0 05 0 8 1 6 ...

Page 149: ...E0C88832 88862 TECHNICAL MANUAL EPSON 143 8 PACKAGE QFP15 128pin Unit mm 14 0 1 16 0 4 65 96 14 0 1 16 0 4 33 64 INDEX 0 16 32 1 128 97 1 4 0 1 0 1 1 7 max 1 0 5 0 2 0 10 0 125 0 4 0 1 0 05 0 05 0 025 ...

Page 150: ...144 EPSON E0C88832 88862 TECHNICAL MANUAL 8 PACKAGE 8 2 Ceramic Package QFP8 128pin Unit mm 28 0 28 32 0 4 28 0 28 32 0 4 0 8 0 35 0 2 3 05max 0 8 0 2 0 15 65 96 33 64 32 1 128 97 INDEX ...

Page 151: ...AL EPSON 145 9 PAD LAYOUT 9 PAD LAYOUT 9 1 Diagram of Pad Layout E0C88832 Chip thickness 0 4 mm Pad opening 95 µm Y X 0 0 1 5 10 15 20 25 35 40 45 50 55 60 65 70 75 80 85 90 95 100 105 110 115 120 125 127 30 5 07 mm 5 01 mm Die No ...

Page 152: ...EPSON E0C88832 88862 TECHNICAL MANUAL 9 PAD LAYOUT Y X 0 0 1 5 10 15 20 25 30 Die No 35 40 45 55 50 60 65 70 75 80 85 90 95 100 105 110 115 5 85 mm 5 16 mm E0C88862 Chip thickness 0 4 mm Pad opening 100 µm ...

Page 153: ...809 666 535 404 273 141 10 121 252 384 533 664 795 927 1 058 1 189 1 320 1 452 1 604 1 735 1 866 1 998 2 129 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 1 915 1 783 1...

Page 154: ...6 1 007 1 138 1 269 1 401 1 532 1 684 1 815 1 947 2 078 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 1 199 1 068 936 805 674 543 411 280 149 18 114 245 376 507 639 770 901 1 032 1 164 1 295 1 426 1 557 1...

Page 155: ...e keep enough distance between OSC1 OSC3 and VDD or other signals on the board pattern 10 PRECAUTIONS ON MOUNTING Reset Circuit The power on reset signal which is input to the RESET terminal changes depending on condi tions power rise time components used board pattern etc Decide the time constant of the capacitor and resistor after enough tests have been completed with the application product Whe...

Page 156: ...lly near circuits that are sensitive to noise such as the oscillation unit OSC4 OSC3 VSS Large current signal line High speed signal line Prohibited pattern example Precautions for Visible Radiation when bare chip is mounted Visible radiation causes semiconductor devices to change the electrical characteristics It may cause this IC to malfunction When developing products which use this IC consider...

Page 157: ... North RD DongSanHuan ChaoYang District Beijing CHINA Phone 64106655 Fax 64107320 SHANGHAI BRANCH 4F Bldg 27 No 69 Gui Jing Road Caohejing Shanghai CHINA Phone 21 6485 5552 Fax 21 6485 0775 HONG KONG CHINA EPSON HONG KONG LTD 20 F Harbour Centre 25 Harbour Road Wanchai HONG KONG Phone 852 2585 4600 Fax 852 2827 4346 Telex 65542 EPSCO HX TAIWAN EPSON TAIWAN TECHNOLOGY TRADING LTD 10F No 287 Nanking...

Page 158: ...ursuit of Saving Technology Epson electronic devices Our lineup of semiconductors liquid crystal displays and quartz devices assists in creating the products of our customers dreams Epson IS energy savings ...

Page 159: ...ELECTRONIC DEVICES MARKETING DIVISION EPSON Electronic Devices Website http www epson co jp device Issue JANUARY 2000 Printed in Japan M A ...

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