E0C88832/88862 TECHNICAL MANUAL
EPSON
65
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Serial Interface)
TRXD0–TRXD7: 00FF4AH
During transmitting
Write the transmitting data into the transmit shift
register.
When "1" is written: HIGH level
When "0" is written: LOW level
Write the transmitting data prior to starting
transmitting.
In the case of continuous transmitting, wait for the
transmitting complete interrupt, then write the data.
The TRXD7 becomes invalid for the asynchronous
7-bit mode.
Converted serial data for which the bits set at "1" as
HIGH (V
DD
) level and for which the bits set at "0"
as LOW (V
SS
) level are output from the SOUT
terminal.
During receiving
Read the received data.
When "1" is read:
HIGH level
When "0" is read:
LOW level
The data from the received data buffer can be read out.
Since the sift register is provided separately from
this buffer, reading can be done during the receive
operation in the asynchronous mode. (The buffer
function is not used in the clock synchronous mode.)
Read the data after waiting for the receiving
complete interrupt.
When performing parity check in the asynchronous
7-bit mode, "0" is loaded into the 8th bit (TRXD7)
that corresponds to the parity bit.
The serial data input from the SIN terminal is level
converted, making the HIGH (V
DD
) level bit "1"
and the LOW (V
SS
) level bit "0" and is then loaded
into this buffer.
At initial reset, the buffer content is undefined.
OER: 00FF49H•D4
Indicates the generation of an overrun error.
When "1" is read:
Error
When "0" is read:
No error
When "1" is written: Reset to "0"
When "0" is written: Invalid
OER is an error flag that indicates the generation of
an overrun error and becomes "1" when an error
has been generated.
An overrun error is generated when the receiving
of data has been completed prior to the writing of
"1" to RXTRG in the asynchronous mode.
OER is reset to "0" by writing "1".
At initial reset and when RXEN is "0", OER is set to
"0" (no error).
PER: 00FF49H•D5
Indicates the generation of a parity error.
When "1" is read:
Error
When "0" is read:
No error
When "1" is written: Reset to "0"
When "0" is written: Invalid
PER is an error flag that indicates the generation of
a parity error and becomes "1" when an error has
been generated.
When a parity check is performed in the asynchro-
nous mode, if data that does not match the parity is
received, a parity error is generated.
PER is reset to "0" by writing "1".
At initial reset and when RXEN is "0", PER is set to
"0" (no error).
FER: 00FF49H•D6
Indicates the generation of a framing error.
When "1" is read:
Error
When "0" is read:
No error
When "1" is written: Reset to "0"
When "0" is written: Invalid
FER is an error flag that indicates the generation of
a framing error and becomes "1" when an error has
been generated.
When the stop bit for the receiving of the asynchro-
nous mode has become "0", a framing error is
generated.
FER is reset to "0" by writing "1".
At initial reset and when RXEN is "0", FER is set to
"0" (no error).
PSIF0, PSIF1: 00FF20H•D4, D5
Sets the priority level of the serial interface interrupt.
The two bits PSIF0 and PSIF1 are the interrupt
priority register corresponding to the serial inter-
face interrupt. Table 5.7.9.4 shows the interrupt
priority level which can be set by this register.
Table 5.7.9.4 Interrupt priority level settings
At initial reset, this register is set to "0" (level 0).
PSIF1
PSIF0
Interrupt priority level
1
1
0
0
1
0
1
0
Level 3 (IRQ3)
Level 2 (IRQ2)
Level 1 (IRQ1)
Level 0 (None)
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