EDM01-07: DAG 3.7G Card User Guide
©2005
3
Version 7: May 2006
The DAG 3.7GF card is shown below:
Card
Architecture
Overview
The DAG 3.7G series card is designed for packet capture and generation on
Ethernet networks.
Ethernet data is received by a DAG 3.7G series card interfaces, and fed
through framers into the Xilinx FPGA.
This FPGA contains an Ethernet processor and the DUCK timestamp engine.
Because of close association of the components, packets are time-stamped
accurately. Time stamped packet records are stored by the FPGA, which
interfaces to the PCI bus. All packet records are written to host PC memory
during capture operations.
The following diagram shows the card’s major components and the flow data:
Summary of Contents for DAG 3.7G Series
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