Flash Type
Size
Manufacturer
S25FL512S
512 Mbit
Cypress (Spansion)
Table 27: QSPI Flash Type
Warning!
Other flash memory devices devices may be equipped in future revisions of the XU1 SoC
module. Please check the user manual regularly for updates.
2.16.2
Signal Description
The QSPI flash is connected to the PS MIO pins 0-5. Some of these signals are available on the module
connector, allowing the user to program the QSPI flash from an external source.
The reset of the QSPI flash is connected to the PS_POR#_LV power-on reset signal (note that modules revi-
sion 1 use PS_POR# signal).
Please refer to Section 3 for details on programming the flash memory.
Warning!
Special care must be taken when connecting the QSPI flash signals on the base board. Long traces or
high capacitance may disturb the data communication between the MPSoC and the flash device.
2.16.3
Configuration
The QSPI flash supports up to 50 MHz operation for standard read. For fast, dual and quad read speed
values, please refer to the flash device datasheet.
Note that the “Feedback Clk” option on pin MIO6 must be enabled in the Zynq configuration for clock rates
higher than 40 MHz.
Please refer to Zynq Ult MPSoC Technical Reference Manual [19] for details on booting from the
QSPI flash.
2.16.4
QSPI Flash Corruption Risk
There have been cases in which it was observed that the content of the flash device got corrupted. Ac-
cording to Cypress, this issue is caused by power loss during the Write Register (WRR) command. The most
common reason to use the WRR command is to turn the QUAD bit ON or OFF - this operation takes place
usually at the beginning of the boot process. If required, the bootloader code can be adjusted to set the
QUAD bit to a fixed value, without invoking this command during boot.
For additional information on this issue, please refer to the Cypress documentation and forum discussions
[25], [26].
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Version 13, 15.08.2019
