Emerson MVME3100 Series Installation And Use Manual Download Page 1

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Embedded Computing for

Business-Critical Continuity

MVME3100 Single Board Computer

Installation and Use

P/N: 6806800M28C
December 2012

Summary of Contents for MVME3100 Series

Page 1: ...Embedded Computing for Business Critical ContinuityTM MVME3100 Single Board Computer Installation and Use P N 6806800M28C December 2012 ...

Page 2: ...document and to make changes from time to time in the content hereof without obligation of Emerson to notify any person of such revision or changes Electronic versions of this material may be read online downloaded for personal use or referenced in another document as a URL to a Emerson website The text itself may not be published commercially in print or electronic form edited translated or other...

Page 3: ...I O Voltage Configuration 27 1 3 5 RTM SEEPROM Address Switch S1 27 1 4 Installing Hardware 28 1 5 Connecting to Peripherals 29 1 6 Completing the Installation 31 2 Startup and Operation 33 2 1 Introduction 33 2 2 Applying Power 33 2 3 Switches and Indicators 33 3 MOTLoad Firmware 39 3 1 Overview 39 3 2 Implementation and Memory Requirements 39 3 3 MOTLoad Commands 39 3 3 1 Utilities 39 3 3 2 Test...

Page 4: ...ithm 60 3 10 2 Image Flags 61 3 10 3 User Images 62 3 10 4 Alternate Boot Data Structure 63 3 10 5 Alternate Boot Images and Safe Start 63 3 10 6 Boot Image Firmware Scan 64 3 11 Startup Sequence 65 4 Functional Description 67 4 1 Overview 67 4 2 Features 67 4 3 Block Diagrams 71 4 4 Processor 72 4 5 System Memory 72 4 6 Local Bus Interface 73 4 6 1 Flash Memory 73 4 6 2 Control and Timers Logic 7...

Page 5: ... J14 J21 J23 85 5 2 4 Serial Port Connectors COM1 J41A COM2 COM5 J2A D 95 5 2 5 VMEbus P1 Connector 95 5 2 6 VMEbus P2 Connector 97 5 2 7 MVME721 PMC I O Module PIM Connectors J10 J14 98 5 2 8 Planar sATA Power Connector J30 100 5 2 9 USB Connector J27 100 5 2 10 sATA Connectors J28 and J29 101 5 3 Headers 101 5 3 1 Boundary Scan Header J24 101 5 3 2 Processor COP Header J25 102 6 Memory Maps 103 ...

Page 6: ... 118 6 1 16 3 Compare Registers 119 6 1 16 4 Counter Registers 120 6 1 17 Geographical Address Register 120 7 Programming Details 121 7 1 Introduction 121 7 2 MPC8540 Reset Configuration 122 7 3 MPC8540 Interrupt Controller 127 7 4 Local Bus Controller Chip Select Assignments 128 7 5 Two Wire Serial Interface 128 7 6 User Configuration EEPROM 129 7 7 VPD EEPROM 130 7 8 RTM VPD EEPROM 130 7 9 Ether...

Page 7: ...C 7 A 2 Environmental Specifications 137 A 3 Thermally Significant Components 138 B Related Documentation 141 B 1 Emerson Network Power Embedded Computing Documents 141 B 2 Manufacturers Documents 141 B 3 Related Specifications 143 Safety Notes 146 Sicherheitshinweise 150 ...

Page 8: ...MVME3100 Single Board Computer Installation and Use 6806800M28C Contents 8 Contents Contents ...

Page 9: ... Pin Assignment 85 Table 5 3 PMC Slot 1 Connector J11 Pin Assignments 85 Table 5 4 PMC Slot 1 Connector J12 Pin Assignments 87 Table 5 5 PMC Slot 1 Connector J13 Pin Assignments 88 Table 5 6 PMC Slot 1 Connector J14 Pin Assignments 89 Table 5 7 PMC Slot 2 Connector J21 Pin Assignments 91 Table 5 8 PMC Slot 2 Connector J22 Pin Assignments 92 Table 5 9 PMC Slot 2 Connector J23 Pin Assignments 93 Tab...

Page 10: ...ck Timer Control Registers 118 Table 6 19 Tick Timer Compare Registers 119 Table 6 20 Tick Timer Counter Registers 120 Table 7 1 MPC8540 Power on Reset Configuration Settings 122 Table 7 2 MPC8540 Interrupt Controller 127 Table 7 3 LBC Chip Select Assignments 128 Table 7 4 I2C Bus Device Addressing 128 Table 7 5 PHY Types and MII Management Bus Addresses 130 Table 7 6 Flash Options 131 Table 7 7 I...

Page 11: ...1 Figure 1 1 Board Layout 23 Figure 1 2 Geographical Address Switch Settings 25 Figure 2 1 Front Panel LEDs and Connectors 35 Figure 4 1 MVME3100 Block Diagram 71 Figure 4 2 MVME721 RTM Block Diagram 72 Figure A 1 Primary Side Components 139 Figure A 2 Secondary Side Components 140 ...

Page 12: ...MVME3100 Single Board Computer Installation and Use 6806800M28C 12 List of Figures ...

Page 13: ... provides information on memory maps and system and configuration registers Programming Details provides additional programming information including IDSEL mapping interrupt assignments for the MPC8540 interrupt controller Flash memory two wire serial interface addressing and other device and system considerations Specifications provides power requirements and environmental specifications Related ...

Page 14: ...512MB DDR SDRAM 128 MB flash Gigabit Ethernet SATA USB PCI expansion connector IEEE handles MVME721 101 Rear Transition Module direct connect 75 mm PIM socket for PMC 1 I O four serial 10 100 1000 Enet 10 100 Enet Abbreviation Description AC Alternating Current ASIC Application Specific Integrated Circuit ATA Advanced Technology Attachment BLT Block Transfer CMC Common Mezzanine Card COM Communica...

Page 15: ...dress GENET Gigabit Ethernet GEV Global Environment Variable GMII Gigabit Media Independent Interface GPCM General Purpose Chip select Machine IBCA Inter Board Communication Address IDE Integrated Drive Electronics I O Input Output IEEE Institute of Electrical and Electronics Engineers LBC Local Bus Controller LED Light Emitting Diode MB Megabyte MBLT Multiplexed Block Transfer MHz Megahertz MIIM ...

Page 16: ... PLD Programmable Logic Device PMC PCI Mezzanine Card IEEE P1386 1 POST Power On S Test PrPMC Processor PMC QUART Quad Universal Asynchronous Receiver Transmitter RAM Random Access Memory RTC Real Time Clock RTM Rear Transition Module RTOS Real Time Operating System SATA Serial AT Attachment SBC Single Board Computer SDRAM Synchronous Dynamic Random Access Memory SIG Special Interest Group SMT Sur...

Page 17: ... WP Write Protect Abbreviation Description Notation Description 0x00000000 Typical notation for hexadecimal numbers digits are 0 through F for example used for addresses and offsets 0b0000 Same for binary numbers digits are 0 and 1 bold Used to emphasize a word Screen Usedforon screenoutputandcoderelatedelements or commands in body text Courier Bold Used to characterize user input and to separate ...

Page 18: ...ary at the time being Ranges for example 0 4 means one of the integers 0 1 2 3 and 4 used in registers Logical OR Indicates a hazardous situation which if not avoided could result in death or serious injury Indicates a hazardous situation which if not avoided may result in minor or moderate injury Indicates a property damage message No danger encountered Pay attention to important information Nota...

Page 19: ...ges This manual has been revised and replaces all prior editions Part Number Publication Date Description 6806800M28C December 2012 Added Declaration of Conformity on page 22 6806800M28B August 2011 Updated Safety Notes on page 148 and Sicherheitshinweise on page 152 6806800M28A April 2011 EA version ...

Page 20: ...MVME3100 Single Board Computer Installation and Use 6806800M28C About this Manual 20 About this Manual ...

Page 21: ...external sATA connector and a combined reset and abort switch Rear panel connectors on the MVME721 board include one RJ 45 connector for each of the 10 100 and 10 100 1000 BaseT Ethernets and four RJ 45 connectors for the asynchronous serial ports The RTM also provides two planar connectors for one PIM with rear I O 1 2 Getting Started This section provides an overview of the steps necessary to in...

Page 22: ...e and software tasks that may need to be performed prior to installing the board in a chassis To produce the desired configuration and ensure proper operation of the MVME3100 you may need to carry out certain hardware modifications before installing the module Connect any other equipment you will be using Connecting to Peripherals on page 31 Verify the hardware is installed Completing the Installa...

Page 23: ...e jumper settings are described further on in this section If you are resetting the board jumpers from their default settings it is important to verify that all settings are reset properly 1 4 1 MVME3100 Layout Figure 1 1 on page 25 illustrates the placement of the jumpers headers connectors switches and various other components on the MVME3100 There are two switch blocks which have user selectabl...

Page 24: ...Hardware Preparation and Installation MVME3100 Single Board Computer Installation and Use 6806800M28C 24 TheMVME3100isfactorytestedandshippedwiththeconfigurationdescribedinthefollowing sections ...

Page 25: ...d Computer Installation and Use 6806800M28C 25 Figure 1 1 Board Layout J25 J24 J30 J28 J2 J13 J14 J11 J12 J23 J21 J22 P1 P2 U21 J4 U1012 U1003 U1010 U5000 U1014 U1020 U1019 U1049 U1050 U1024 U1012 U1000 U1007 U1052 U1025 U1026 U1027 U1046 U1047 U1051 1 1 S4 S3 ...

Page 26: ...s should be used Safe ENV settings should be used This switch status is readable from System Statusregister1 bit5 Software may check this bit and act accordingly BOOT BLOCK SELECT 2 Flash memory map is normal and boot block A is selected Boot block B is selected and mapped to the highest address FLASH BANK WP 3 Entire Flash is not write protected Flash is write protected Reserved 4 VME SCON AUTO M...

Page 27: ...will assert TRST Isolates the board HRESET from TRST and allows the board to reset without resetting the MPC8540 JTAG COP interface This switch should remain in the OFF position unless a MPC8540 emulator is attached Table 1 2 Configuration Switch S4 Settings continued Switch Pos Setting Notes OFF Factory Default ON Figure 1 2 Geographical Address Switch Settings 16 Not used PCI X mode GAP 0 GA4 0 ...

Page 28: ...4 0 SW3 SW4 SW5 SW6 SW7 SW8 1 1 11110 OFF OFF OFF OFF OFF ON 2 1 11101 OFF OFF OFF OFF ON OFF 3 0 11100 ON OFF OFF OFF ON ON 4 1 11011 OFF OFF OFF ON OFF OFF 5 0 11010 ON OFF OFF ON OFF ON 6 0 11001 ON OFF OFF ON ON OFF 7 1 11000 OFF OFF OFF ON ON ON 8 1 10111 OFF OFF ON OFF OFF OFF 9 0 10110 ON OFF ON OFF OFF ON 10 0 10101 ON OFF ON OFF ON OFF 11 1 10100 OFF OFF ON OFF ON ON 12 0 10011 ON OFF ON ...

Page 29: ...f PCI X mode The default factory configuration is for 3 3V PMC I O voltage 1 4 5 RTM SEEPROM Address Switch S1 A 4 position SMT configuration switch is located on the RTM to set the device address of the RTM serial EEPROM device The switch settings are defined in the following table 20 0 01011 ON ON OFF ON OFF OFF 21 1 01010 OFF ON OFF ON OFF ON Table 1 4 Slot Geographical Address Settings continu...

Page 30: ...roduct or the additional devices or modules z Before installing or removing additional devices or modules read the respective documentation Damage of Circuits z Electrostatic discharge and incorrect installation and removal of the product can damage circuits or shorten their life z Before touching the product make sure that your are working in an ESD safe environment or wear an ESD wrist strap or ...

Page 31: ...VME3100 into the guides of the chassis 4 Ensure that the levers of the two injector ejectors are in the outward position 5 Slide the MVME3100 into the chassis until resistance is felt 6 Simultaneously move the injector ejector levers in an inward direction 7 Verify that the MVME3100 is properly seated and secure it to the chassis using the two screws located adjacent to the injector ejector levers...

Page 32: ...l devices or modules z Before installing or removing additional devices or modules read the respective documentation and use appropriate tools Table 1 7 MVME3100 Connectors Connector Function J4 PMC expansion connector J11 J12 J13 J14 PCI mezzanine card PMC slot 1 connector J21 J22 J23 PCI mezzanine card PMC slot 2 connector J24 Boundary scan header J25 COP header J27 USB connector J28 Front panel...

Page 33: ...cablesconnectedareappropriatefor your system configuration Replace the chassis or system cover reconnect the system to the AC or DC power source and turn the equipment power on J2A 10 100 1000Mb s Ethernet connector J2B 10 100Mb s Ethernet connector J10 PIM power ground J14 PIM I O P2 VME backplane connector Table 1 8 MVME721 Rear Transition Module Connectors continued Connector Function ...

Page 34: ...Hardware Preparation and Installation MVME3100 Single Board Computer Installation and Use 6806800M28C 34 ...

Page 35: ...ard provides a single push button switch that provides both abort and reset ABT RST functions When the switch is pressed for less than five seconds an abort interrupt isgeneratedtotheprocessor Iftheswitchisheldformorethanfiveseconds aboardhardreset is generated The board hard reset will reset the MPC8540 local PCI PCI X buses Ethernet PHYs serial ports Flash devices and PLD s If the MVME3100 is co...

Page 36: ...8C 36 GENET 1 Link Speed SPEED Off No link Yellow 10 100Base T operation Green 1000Base T operation GENET 1 Activity ACT Blinking Green Activity proportional to bandwidth utilization Off No activity Table 2 1 Front Panel LED Status Indicators continued Function Label Color Description ...

Page 37: ...Startup and Operation MVME3100 Single Board Computer Installation and Use 6806800M28C 37 Figure 2 1 Front Panel LEDs and Connectors ABORT RESET G ENET 1 COM 1 SATA 1 USER 1 SPEED PMC 1 PMC 2 FAIL ACT ...

Page 38: ... link Yellow 10 100Base T operation ENET 1 Activity ACT Blinking Green Activity proportional to bandwidth utilization Off No activity Table 2 3 Additional Onboard Status Indicators Function Label Color Description User Defined LED 2 DS7 silkscreen Green This indicator is illuminated by software assertion of its corresponding register bit User Defined LED 3 DS8 silkscreen Green This indicator is il...

Page 39: ..._OUT so the LED can be programmed to indicate one of three trigger events based on the value in the MPC8540 TOSR register GENET 1 Link Quality DS2 silkscreen Off Slow Blink Green Fast Blink Green Green Extremely poor Signal to Noise ratio cannot receive data Poor SNR receive errors detected Fair SNR close to data error threshold Good SNR on link GENET 2 Link Quality DS3 Same as DS2 Table 2 3 Addit...

Page 40: ...Startup and Operation MVME3100 Single Board Computer Installation and Use 6806800M28C 40 ...

Page 41: ...tion and Memory Requirements The implementation of MOTLoad and its memory requirements are product specific The MVME3100 Single Board Computer SBC is offered with a wide range of memory for example DRAM external cache flash Typically the smallest amount of on board DRAM that an Emerson SBC has is 32 MB Each supported product line has its own unique MOTLoad binary image s Currently the largest MOTL...

Page 42: ...ts operate automatically without any user interaction There are a few tests where the functionality being validated requires user interaction that is switch tests interactive plug in hardware modules etc Most MOTLoad test results error data status data are logged not printed All MOTLoad tests commands have complete and separate descriptions refer to the MOTLoad Firmware Package User s Manual for t...

Page 43: ...kage User s Manual Test results and test status are obtained through the testStatus errorDisplay and taskActive commands Refer to the appropriate command description page in the MOTLoad Firmware Package User s Manual for more information 3 3 3 Command List The following table provides a list of all current MOTLoad commands Products supported by MOTLoad may or may not employ the full command set Ty...

Page 44: ...tory Table s cm Turns on Concurrent Mode csb csh csw Calculates a Checksum Specified by Command line Options devShow Display Show Device Node Table diskBoot Disk Boot Direct Access Mass Storage Device downLoad Down Load S Record from Host ds One Line Instruction Disassembler echo Echo a Line of Text elfLoader ELF Object File Loader errorDisplay Display the Contents of the Test Error Status Table e...

Page 45: ...able Area Initialize NVRAM Header gevList Global Environment Variable Labels Names Listing gevShow Global Environment Variable Show gn Go Execute User Program to Next Instruction go Go Execute User Program gt Go Execute User Program to Temporary Break Point hbd Display History Buffer hbx Execute History Buffer Entry help Display Command Test Help Strings l2CacheShow Display state of L2 Cache and L...

Page 46: ...ister pciDump Dump PCI Device Configuration Header Register pciShow Display PCI Device Configuration Header Register pciSpace Display PCI Device Address Space Allocation ping Ping Network Host portSet Port Set portShow Display Port Device Configuration Data rd User Program Register Display reset Reset System rs User Program Register Set set Set Date and Time sromRead SROM Read sromWrite SROM Write...

Page 47: ...itor for ECC Errors testRamMarch RAM March testRamPatterns RAM Patterns testRamPerm RAM Permutations testRamQuick RAM Quick testRamRandom RAM Random Data Patterns testRtcAlarm RTC Alarm testRtcReset RTC Reset testRtcRollOver RTC Rollover testRtcTick RTC Tick testSerialExtLoop Serial External Loopback testSeriallntLoop Serial Internal Loopback testStatus Display the Contents of the Test Status Tabl...

Page 48: ...to signify the end of input MOTLoad then performs the specified action An example of a MOTLoad command line promptis shown below The MOTLoad promptchanges according towhatproduct it is used on for example MVME5500 MVME6100 MVME3100 Example MVME3100 If an invalid MOTLoad command is entered at the MOTLoad command line prompt MOTLoad displays a message that the command was not found Example tftpPut T...

Page 49: ...imizestherequiredamountofcommandlineinput MOTLoad isaneverchangingfirmware package so user input shortcuts may change as command additions are made Example MVME3100 version Copyright Motorola Inc 1999 2002 All Rights Reserved MOTLoad RTOS Version 2 0 PAL Version 0 1 Motorola MVME3100 Example MVME3100 ver Copyright Motorola Inc 1999 2002 All Rights Reserved MOTLoad RTOS Version 2 0 PAL Version 0 1 ...

Page 50: ...All commands command options and device tree strings are case sensitive Example MVME3100 flashProgram d dev flash0 n00100000 For more information on MOTLoad operation and function refer to the MOTLoad Firmware Package User s Manual 3 4 2 Command Line Help Each MOTLoad firmware package has an extensive product specific help facility that can be accessed through the help command The user can enter h...

Page 51: ...the firmware command utility vmeCfg 3 5 1 Default VME Settings As shipped from the factory the MVME3100 has the following VME configuration programmed via Global Environment Variables GEVs for the Tsi148 VME controller The firmware allows certain VME settings to be changed in order for the user to customize the environment The following is a description of the default VME settings that are changea...

Page 52: ...ibute Register 00000000 CRG Base Address Upper Register 00000000 CRG Base Address Lower Register 00000000 MVME3100 The CRG Attribute Register is set to the default RESET condition z MVME3100 vmeCfg s i0 Displaying the selected Default VME Setting interpreted as follows Inbound Image 0 Attribute Register 000227AF Inbound Image 0 Starting Address Upper Register 00000000 Inbound Image 0 Starting Addr...

Page 53: ...slation Offset Upper Register 00000000 Outbound Image 1 Translation Offset Lower Register 70000000 Outbound Image 1 2eSST Broadcast Select Register 00000000 MVME3100 Outbound window 1 OTAT1 is enabled 2eSST timing at SST320 transfer mode of 2eSST A32 D32 Supervisory access The window accepts transfers on the PCI X Local Bus from 0x91000000 0xAFFF0000 and translates them onto the VMEbus using an of...

Page 54: ...ddress Lower Register B3FF0000 Outbound Image 3 Ending Address Upper Register 00000000 Outbound Image 3 Ending Address Lower Register B3FF0000 Outbound Image 3 Translation Offset Upper Register 00000000 Outbound Image 3 Translation Offset Lower Register 4C000000 Outbound Image 3 2eSST Broadcast Select Register 00000000 MVME3100 Outbound window 3 OTAT3 is enabled 2eSST timing at SST320 transfer mod...

Page 55: ... Register Control Status Register Settings The CR CSR base address is initialized to the appropriate setting based on the Geographical address that is the VME slot number See the VME64 Specification and the VME64 Extensions for details As a result a 512K byte CR CSR area can be accessed from the VMEbus using the CR CSR AM code 3 5 3 Displaying VME Settings To display the changeable VME setting typ...

Page 56: ...are prompt z vmeCfg e m Edits Master Enable state z vmeCfg e i 0 7 Edits selected Inbound Window state z vmeCfg e o 0 7 Edits selected Outbound Window state z vmeCfg e r184 Edits PCI Miscellaneous Register state z vmeCfg e r188 Edits Special PCI Target Image Register state z vmeCfg e r400 Edits Master Control Register state z vmeCfg e r404 Edits Miscellaneous Control Register state z vmeCfg e r40C...

Page 57: ...bound Window state z vmeCfg d r184 Deletes PCI Miscellaneous Register state z vmeCfg d r188 Deletes Special PCI Target Image Register state z vmeCfg d r400 Deletes Master Control Register state z vmeCfg d r404 Deletes Miscellaneous Control Register state z vmeCfg d r40C Deletes User AM Codes Register state z vmeCfg d rF70 Deletes VMEbus Register Access Image Control Register state 3 5 6 Restoring ...

Page 58: ... the target CR CSR slave addresses configured by MOTLoad are assigned according to the installation slot in the backplane as indicated by the VME64 Specification For reference the following values are provided For further details on CR CSR space please refer to the VME64 Specification listed in Appendix B Related Documentation The MVME3100 uses a Discovery II for its VME bridge The offsets of the ...

Page 59: ...ng to support reads and writes of address 0x002ff348 in VME CR CSR space 0x280000 0x7f348 3 7 Alternate Boot Images and Safe Start Some later versions of MOTLoad support Alternate Boot Images and a Safe Start recovery procedure If Safe Start is available on the MVME3100 Alternate Boot Images are supported With Alternate Boot Image support the bootloadercode in the boot block examines the upper 8MB...

Page 60: ...age The scan is performed by examining each 1MB boundary for a defined set of flags that identify the image as being Power On SelfTest POST USER or MCG MOTLoad is an MCG image POST is a user developed Power On Self Test that would perform a set of diagnostics and then return to the bootloader image User would be a boot image such as the VxWorks bootrom which would perform board initialization A bo...

Page 61: ...e is provided to enable recovery in cases when the programmed Alternate Boot Image is no longer desired The following output is an example of an interactive Safe Start ABCDEInteractive Boot Mode Entered boot Interactive boot commands d show directory of alternate boot images c continue with normal startup q quit without executing any alternate boot image r address execute specified or default alte...

Page 62: ...he checksum calculation The calculation assumes the location to be zero The algorithm is implemented using the following code Unsigned int checksum Unsigned int startPtr starting address Unsigned int endPtr ending address unsigned int checksum 0 while startPtr endPtr checksum startPtr Name Type Size Notes UserDefined unsigned integer 8 User defined ImageKey 1 unsigned integer 1 0x414c5420 ImageKey...

Page 63: ...e z IMAGE_MCG If set this flag defines the image as being an Alternate MOTLoad as opposed to USER image This bit should not be set by developers of alternate boot images z IMAGE_POST If set this flag defines the image as being a power on self test image This bit flag is used to indicate that the image is a diagnostic and should be run prior to running either USER or MCG boot images POST images are...

Page 64: ... and is mapped starting at CPU address 0 z If RAM ECC or parity is supported RAM has been scrubbed of ECC or parity errors z The active Flash bank boot is mapped from the upper end of the address space z If specified by COPY_TO_RAM the image has been copied to RAM at the address specified by ImageRamAddress z CPU register R1 the stack pointer has been initialized to a value near the end of RAM z C...

Page 65: ...e board to whatever state the image may further require for its execution POST images are expected but not required to return to the boot loader Upon return the boot loader proceeds with the scan for an executable alternate boot image POST images that return control to the boot loader must ensure that upon return the state of the board is consistent with the state that the board was in at POST ent...

Page 66: ...s of the same type control is passed to the first image encountered in the scan SafeStart whetherinvokedbyhittingESContheconsolewithinthefirstfivesecondsfollowing power on reset or by setting the Safe Start jumper interrupts the scan process The user may then display the available boot images and select the desired image The feature is provided to enable recovery incaseswhenthe programmed Alternat...

Page 67: ...sh bank possibly interactively for a valid USER boot image If found the USER boot image executes A return to the boot block code is not anticipated z If a valid USER boot image is not found search the active flash bank possibly interactively for a valid Alternate MOTLoad boot image anticipated to be an upgrade of alternate MOTLoad firmware If found the image is executed A return to the boot block ...

Page 68: ...MOTLoad Firmware MVME3100 Single Board Computer Installation and Use 6806800M28C 68 ...

Page 69: ...Integrated PCI PCI X controller Two integrated 10 100 1000 Ethernet controllers Integrated 10 100 Ethernet controller Integrated dual UART Integrated I2C controller Integrated programmable interrupt controller Integrated local bus controller Integrated DDR SDRAM controller System Memory One SODIMM socket Up to DDR333 ECC One or two banks of memory on a single SODIMM I2C Interface One 8KB VPD seria...

Page 70: ... integrated LEDs for front I O one serial channel One front panel RJ45 connector with integrated LEDs for front I O one 10 100 1000 Ethernet channel One front panel external sATA data connector for front I O one sATA channel One front panel USB Type A upright receptacle for front I O one USB 2 0 channel 1263 version PMC site 1 front I O and rear P2 I O PMC site 2 front I O Serial ATA One four chan...

Page 71: ...nel reset abort switch Four front panel status indicators 10 100 1000 Ethernet link speed and activity board fail and user software controlled LED Six planar status indicators one power supply status LED two user software controlled LEDs three sATA activity LEDs one per channel One standard 16 pin COP header Boundary scan support Switches for VME geographical addressing in a three row backplane So...

Page 72: ...3100 Single Board Computer Installation and Use 6806800M28C 72 Miscellaneous Four status indicators 10 100 1000 and 10 100 Ethernet link speed and activity LEDs Table 4 2 MVME721 RTM Features Summary continued Feature Description ...

Page 73: ...puter Installation and Use 6806800M28C 73 4 3 Block Diagrams Figure 4 1 shows a block diagram of the overall board architecture and Figure 4 2 shows a block diagram of the MVME721 rear transition module architecture Figure 4 1 MVME3100 Block Diagram ...

Page 74: ...DIMM socket This socket supports standard single or dual bank unbuffered SSTL 2 DDR I JESD8 9B compliant SODIMM module with ECC The MPC8540 DDR memory interface supports up to 166 MHz 333 MHz data rate operation Figure 4 2 MVME721 RTM Block Diagram 4390 0106 PIM 10 PIM U S B sATA P2 P0 GigE RJ45 GigE 2 10 100 Serial Port 4 Serial Port 3 Serial Port 2 Serial Port 1 VPD 8K8 I2 C Bus Rear Panel Futur...

Page 75: ...sh Memory The MVME3100 provides one physical bank of soldered on Flash memory The bank is composed of two physical Flash devices configured to operate in 16 bit mode to form a 32 bit Flash bank The default configuration for the MVME3100 1263 is 128MB using two 512Mb devices and for the MVME3100 1152 it is 64MB using two 256Mb devices Refer to the MVME3100 Single Board Computer Programmer s Referen...

Page 76: ...o the on board SODIMM socket This allows the serial presence detect SPD in the serial EEPROM which is located on the memory module to be read and used to configure the memory controller accordingly Similarly the I2C interface is routed to the P2 connector for access to the serial EEPROM located on the RTM The device address for the RTM serial EERPOM is user selectable using configuration switches ...

Page 77: ...ntroller bus to provide additional asynchronous serial ports The QUART provides four asynchronous serial ports SP1 SP4 which are routed to the P2 connector Refer to the ST16C554D Datasheet listed in Appendix B Related Documentation for additional details and or programming information 4 10 PCI PCI X Interfaces and Devices The MVME3100 provides three separate PCI PCI X bus segments Bus segment A op...

Page 78: ... to a sATA connector mounted on the front panel for an external drive connection Channel 1 is routed to a planar sATA connector for an inside the chassis drive connection Collocated with the planar connector is a sATA power connector The sATA controller can operate in legacy Native PCI IDE and Direct Port Access DPA mode The MVME3100 provides two programmable LEDs to indicate sATA channel activity...

Page 79: ... or PrPMC from either supply PMC slot 1 supports PMC slot 2 supports You cannot use 3 3V and 5V PMCs together the voltage keying pin on slots 1 and 2 must be identical When in 5V mode the bus runs at 33 MHz In addition the PMC connectors are located such that a double width PMC may be installed in place of the two single width PMCs Feature Description Mezzanine Type PMC PCI Mezzanine Card Mezzanin...

Page 80: ...limiting over current detection and power enable for port 1 Refer to the μPD720101 USB 2 0 Host Controller Datasheet listed in Appendix B Related Documentation for additional details 4 10 7 PMC Expansion The MVM3E3100 provides additional PMC module capability through the use of a connector on bus C that is compatible with the PMCspan boards Up to four additional PMC modules may be added by using e...

Page 81: ... the MVME3100 This SMTU2430 1 holder allows for quick and easy replacement of a 3V button cell lithium battery CR2430 which provides back up power to the on board DS1375 RTC A battery switching circuit provides automatic switching between the 3 3V and battery voltages The battery provides backup power to the RTC for a minimum of one year at nominal temperature 4 13 Reset Control Logic The sources ...

Page 82: ...d Computer Installation and Use 6806800M28C 82 4 14 Debug Support The MVME3100 provides a boundary scan header for boundary scan test access and device programming This board also provides a separate standard COP header for MPC8540 COP emulation ...

Page 83: ...1B GENET2 J2B ENET1 J2A z PCI Mezzanine Card PMC Connectors J11 J14 J21 J23 z Serial Port Connectors COM1 J41A COM2 COM5 J2A D z VMEbus P1 Connector z VMEbus P2 Connector z MVME721 PMC I O Module PIM Connectors J10 J14 z Planar sATA Power Connector J30 z USB Connector J27 z sATA Connectors J28 and J29 The following headers are described in this chapter z Boundary Scan Header J24 z Processor COP He...

Page 84: ...for this connector are as follows Table 5 1 PMC Expansion Connector J4 Pin Assignments Pin Signal Signal Pin 1 3 3V GND 3 3V 2 3 PCICLK PMCINTA 4 5 GND PMCINTB 6 7 PURST PMCINTC 8 9 HRESET PMCINTD 10 11 TDO TDI 12 13 TMS TCK 14 15 TRST PEP 16 17 PCIXGNT PCIXREQ 18 19 12V 12V 20 21 PERR SERR 22 23 LOCK No Connect 24 25 DEVSEL No Connect 26 27 GND PCI XCAP 28 29 TRDY IRDY 30 31 STOP FRAME 32 33 GND ...

Page 85: ...2 44 45 AD1 AD0 46 47 AD3 AD2 48 49 AD5 AD4 50 51 AD7 AD6 52 53 AD9 AD8 54 55 AD11 AD10 56 57 AD13 AD12 58 59 AD15 AD14 60 61 AD17 AD16 62 63 AD19 AD18 64 65 AD21 AD20 66 67 AD23 AD22 68 69 AD25 AD24 70 71 AD27 AD26 72 73 AD29 AD28 74 75 AD31 AD30 76 Table 5 1 PMC Expansion Connector J4 Pin Assignments continued Pin Signal Signal Pin ...

Page 86: ...C BE4 80 81 C BE7 C BE6 82 83 AD33 AD32 84 85 AD35 AD34 86 87 AD37 AD36 88 89 AD39 AD38 90 91 AD41 AD40 92 93 AD43 AD42 94 95 AD45 AD44 96 97 AD47 AD46 98 99 AD49 AD48 100 101 AD51 AD50 102 103 AD53 AD52 104 105 AD55 AD54 106 107 AD57 AD56 108 109 AD59 AD58 110 111 AD61 AD60 112 113 AD63 AD62 114 Table 5 1 PMC Expansion Connector J4 Pin Assignments continued Pin Signal Signal Pin ...

Page 87: ...r rear I O The pin assignments for these connectors are as follows 5 2 3 PCI Mezzanine Card PMC Connectors J11 J14 J21 J23 There are seven 64 pin SMT connectors on the MVME3100 to provide 32 64 bit PCI interfaces and P2 I O for one optional add on PMC PMC slot connector J14 contains the signals that go to VME P2 I O rows A C D and Z The pin assignments for these connectors are as follows Table 5 2...

Page 88: ... AD28 AD27 22 23 AD25 GND 24 25 GND C BE3 26 27 AD22 AD21 28 29 AD19 5V 30 31 3 3V VIO AD17 32 33 FRAME GND 34 35 GND IRDY 36 37 DEVSEL 5V 38 39 GND LOCK 40 41 PCI_RSVD PCI_RSVD 42 43 PAR GND 44 45 3 3V VIO AD15 46 47 AD12 AD11 48 49 AD09 5V 50 51 GND C BE0 52 53 AD06 AD05 54 55 AD04 GND 56 57 3 3V VIO AD03 58 59 AD02 AD01 60 Table 5 3 PMC Slot 1 Connector J11 Pin Assignments continued Pin Signal ...

Page 89: ... GND 6 7 GND Not Used 8 9 Not Used Not Used 10 11 Pull up 3 3V 12 13 RST Pull down 14 15 3 3V Pull down 16 17 Not Used GND 18 19 AD30 AD29 20 21 GND AD26 22 23 AD24 3 3V 24 25 IDSEL1 AD23 26 27 3 3V AD20 28 29 AD18 GND 30 31 AD16 C BE2 32 33 GND IDSEL1B 34 35 TRDY 3 3V 36 37 GND STOP 38 39 PERR GND 40 41 3 3V SERR 42 43 C BE1 GND 44 Table 5 3 PMC Slot 1 Connector J11 Pin Assignments continued Pin ...

Page 90: ...0 61 ACK64 3 3V 62 63 GND No Connect MONARCH 64 Table 5 5 PMC Slot 1 Connector J13 Pin Assignments Pin Signal Signal Pin 1 Reserved GND 2 3 GND C BE7 4 5 C BE6 C BE5 6 7 C BE4 GND 8 9 3 3V VIO PAR64 10 11 AD63 AD62 12 13 AD61 GND 14 15 GND AD60 16 17 AD59 AD58 18 19 AD57 GND 20 21 3 3V VIO AD56 22 23 AD55 AD54 24 25 AD53 GND 26 27 GND AD52 28 Table 5 4 PMC Slot 1 Connector J12 Pin Assignments cont...

Page 91: ... AD36 52 53 AD35 AD34 54 55 AD33 GND 56 57 3 3V VIO AD32 58 59 Reserved Reserved 60 61 Reserved GND 62 63 GND Reserved 64 Table 5 6 PMC Slot 1 Connector J14 Pin Assignments Pin Signal Signal Pin 1 PMC1_1 P2 C1 PMC1_2 P2 A1 2 3 PMC1_3 P2 C2 PMC1_4 P2 A2 4 5 PMC1_5 P2 C3 PMC1_6 P2 A3 6 7 PMC1_7 P2 C4 PMC1_8 P2 A4 8 9 PMC1 _9 P2 C5 PMC1_10 P2 A5 10 11 PMC1_11 P2 C6 PMC1_12 P2 A6 12 Table 5 5 PMC Slot...

Page 92: ...33 P2 C17 PMC1_34 P2 A17 34 35 PMC1_35 P2 C18 PMC1_36 P2 A18 36 37 PMC1_37 P2 C19 PMC1_38 P2 A19 38 39 PMC1_39 P2 C20 PMC1_40 P2 A20 40 41 PMC1_41 P2 C21 PMC1_42 P2 A21 42 43 PMC1_43 P2 C22 PMC1_44 P2 A22 44 45 PMC1_45 P2 C23 PMC1_46 P2 A23 46 47 PMC1_47 P2 C24 PMC1_48 P2 A24 48 49 PMC1_49 P2 C25 PMC1_50 P2 A25 50 51 PMC1_51 P2 C26 PMC1_52 P2 A26 52 53 PMC1_53 P2 C27 PMC1_54 P2 A27 54 55 PMC1_55 P...

Page 93: ...PMCPRSNT1 5V 8 9 INTB PCI_RSVD 10 11 GND 3 3Vaux 12 13 CLK GND 14 15 GND PMCGNT1 16 17 PMCREQ1 5V 18 19 3 3V VIO AD31 20 21 AD28 AD27 22 23 AD25 GND 24 25 GND C BE3 26 27 AD22 AD21 28 29 AD19 5V 30 31 3 3V VIO AD17 32 33 FRAME GND 34 35 GND IRDY 36 37 DEVSEL 5V 38 39 GND LOCK 40 41 PCI_RSVD PCI_RSVD 42 43 PAR GND 44 45 3 3V VIO AD15 46 47 AD12 AD11 48 49 AD09 5V 50 51 GND C BE0 52 53 AD06 AD05 54 ...

Page 94: ... Signal Signal Pin 1 12V TRST 2 3 TMS TDO 4 5 TDI GND 6 7 GND Not Used 8 9 Not Used Not Used 10 11 Pull up 3 3V 12 13 RST Pull down 14 15 3 3V Pull down 16 17 Not Used GND 18 19 AD30 AD29 20 21 GND AD26 22 23 AD24 3 3V 24 25 IDSEL1 AD23 26 27 3 3V AD20 28 29 AD18 GND 30 31 AD16 C BE2 32 33 GND IDSEL1B 34 35 TRDY 3 3V 36 37 GND STOP 38 Table 5 7 PMC Slot 2 Connector J21 Pin Assignments continued Pi...

Page 95: ...ND 56 57 Not Used EREADY1 58 59 GND Not Used 60 61 ACK64 3 3V 62 63 GND No Connect MONARCH 64 Table 5 9 PMC Slot 2 Connector J23 Pin Assignments Pin Signal Signal Pin 1 Reserved GND 2 3 GND C BE7 4 5 C BE6 C BE5 6 7 C BE4 GND 8 9 3 3V VIO PAR64 10 11 AD63 AD62 12 13 AD61 GND 14 15 GND AD60 16 17 AD59 AD58 18 19 AD57 GND 20 21 3 3V VIO AD56 22 Table 5 8 PMC Slot 2 Connector J22 Pin Assignments cont...

Page 96: ... 32 33 GND AD48 34 35 AD47 AD46 36 37 AD45 GND 38 39 3 3V VIO AD44 40 41 AD43 AD42 42 43 AD41 GND 44 45 GND AD40 46 47 AD39 AD38 48 49 AD37 GND 50 51 GND AD36 52 53 AD35 AD34 54 55 AD33 GND 56 57 3 3V VIO AD32 58 59 Reserved Reserved 60 61 Reserved GND 62 63 GND Reserved 64 Table 5 9 PMC Slot 2 Connector J23 Pin Assignments continued Pin Signal Signal Pin ...

Page 97: ...Ebus P1 Connector The VME P1 connector is a 160 pin DIN The P1 connector provides power and VME signals for 24 bit address and 16 bit data The pin assignments for the P1 connector is as follows Table 5 10 COM Port Connector Pin Assignments Pin Signal 1 No connect 2 RTS 3 GND 4 TX 5 RX 6 GND 7 CTS 8 No connect Table 5 11 VMEbus P1 Connector Pin Assignments ROW Z ROW A ROW B ROW C ROW D 1 Reserved D...

Page 98: ...AM1 A21 GA4_L 17 18 GND AS AM2 A20 Reserved 18 19 Reserved GND AM3 A19 Reserved 19 20 GND IACK GND A18 Reserved 20 21 Reserved IACKIN SERA A17 Reserved 21 22 GND IACKOUT SERB A16 Reserved 22 23 Reserved AM4 GND A15 Reserved 23 24 GND A07 IRQ7 A14 Reserved 24 25 Reserved A06 IRQ6 A13 Reserved 25 26 GND A05 IRQ5 A12 Reserved 26 27 Reserved A04 IRQ4 A11 Reserved 27 28 GND A03 IRQ3 A10 Reserved 28 29 ...

Page 99: ...6 VRETRY_L PMC1_IO5 GND 4 GND PMC1_IO8 VA24 PMC1_IO7 E1 2 5 SP1CTS PMC1_IO10 VA25 PMC1_IO9 E1 2 6 GND PMC1_IO12 VA26 PMC1_IO11 GND 7 SP1RTS PMC1_IO14 VA27 PMC1_IO13 NC 8 GND PMC1_IO16 VA28 PMC1_IO15 NC 9 SP2RX PMC1_IO18 VA29 PMC1_IO17 GND 10 GND PMC1_IO20 VA30 PMC1_IO19 NC 11 SP2TX PMC1_IO22 VA31 PMC1_IO21 NC 12 GND PMC1_IO24 GND PMC1_IO23 GND 13 SP2CTS PMC1_IO26 5V PMC1_IO25 I2C_SDA 14 GND PMC1_I...

Page 100: ...C1_IO45 E2 3 24 GND PMC1_IO48 VD25 PMC1_IO47 E2 3 25 SP4RX PMC1_IO50 VD26 PMC1_IO49 GND 26 GND PMC1_IO52 VD27 PMC1_IO51 E2 2 27 SP4TX PMC1_IO54 VD28 PMC1_IO53 E2 2 28 GND PMC1_IO56 VD29 PMC1_IO55 GND 29 SP4CTS PMC1_IO58 VD30 PMC1_IO57 E2 1 30 GND PMC1_IO60 VD31 PMC1_IO59 E2 1 31 SP4RTS PMC1_IO62 GND PMC1_IO61 GND 32 GND PMC1_IO64 5V PMC1_IO63 5V Table 5 12 VME P2 Connector Pinouts continued Pin P2...

Page 101: ...No Connect GND 34 35 No Connect No Connect 36 37 5V No Connect 38 39 No Connect No Connect 40 41 No Connect 3 3V 42 43 No Connect No Connect 44 45 GND No Connect 46 47 No Connect No Connect 48 49 No Connect GND 50 51 No Connect No Connect 52 53 5V No Connect 54 55 No Connect No Connect 56 57 No Connect 3 3V 58 59 No Connect No Connect 60 61 No Connect No Connect 62 63 No Connect No Connect 64 Tabl...

Page 102: ...l ATA sATA drive mounted on the board or somewhere within the chassis The pin assignments for this header are as follows 5 2 9 USB Connector J27 ThereisoneUSBTypeAconnectorlocatedontheMVME3100frontpanel Thepinassignments are as follows Table 5 14 Planar sATA Power Connector J30 Pin Assignments Pin Signal 1 5V 2 5V 3 GND 4 GND Table 5 15 USB Connector J27 Pin Assignments Pin Signal 1 USB_VBUS 5 0V ...

Page 103: ...nment for these connectors is as follows 5 3 Headers This section describes the pin assignments of the Headers on the MVME3100 For Hheader settings refer to Configuring Hardware on page 22 5 3 1 Boundary Scan Header J24 The 14 pin boundary scan header provides an interface for programming the on board PLDs and for boundary scan testing debug purposes The pin assignments for this header are as foll...

Page 104: ...esettable fuse and can supply up to 0 5A to power I O buffers in the COP controller 5 TDI GND 6 7 TMS GND 8 9 TCK GND 10 11 NC GND BSCANEN_L 12 13 BSCAN_AW_L GND 14 Table 5 17 Boundary Scan Header J24 Pin Assignments continued Pin Signal Signal Pin Table 5 18 Processor COP Header J25 Pin Assignments Pin Signal Signal Pin 1 CPU_TDO No Connect 2 3 CPU_TDI CPU_TRST_L 4 5 Pullup CPU_VIO 3 3V 6 7 CPU_T...

Page 105: ... the full 8MB of default boot space and the 1MB of CCSR space additional TLB entries must be set up within the e500 core for mapping these regions Refer to the MPC8540 Reference Manual listed in Appendix B Related Documentation for details This is the default location for the CCSRs but it is not mapped after reset Only FFFF F000 to FFFF FFFF is mapped after reset The e500 core fetches the first in...

Page 106: ...B Table 6 2 MOTLoad s Processor Address Map Processor Address Size Definition Notes Start End 0000 0000 top_dram 1 dram_size 2GB max System Memory on board DRAM 8000 0000 DFFF FFFF 1 5GB PCI Memory Space VME E000 0000 E0FF FFFF 16MB PCI I O Space E100 0000 E10F FFFF 1MB MPC8540 CCSR E1100 0000 E1FF FFFF 15MB Not Used E200 0000 E2FF FFFF 16MB Status Control Registers UARTs External Timers E300 0000...

Page 107: ...tus Register 2 3 E200 0001 System Control Register 2 3 E200 0002 Status Indicator Register 2 3 E200 0003 Flash Control Status Register 2 3 E200 0004 PCI Bus A Status Register 2 3 E200 0005 PCI Bus B Status Register 2 3 E200 0006 PCI Bus C Status Register 2 3 E200 0007 Interrupt Detect Register 2 3 E200 0008 Presence Detect Register 2 3 E200 0009 PLD Revision 2 3 E200 000C PLD Date Code 32 bits 2 3...

Page 108: ...nal PLD Tick Timer 2 Control Register 4 2 E202 0024 External PLD Tick Timer 2 Compare Register 4 2 E202 0028 External PLD Tick Timer 2 Counter Register 4 2 E202 002C Reserved 4 2 E202 0030 External PLD Tick Timer 3 Control Register 4 2 E202 0034 External PLD Tick Timer 3 Compare Register 4 2 E202 0038 External PLD Tick Timer 3 Counter Register 4 2 E202 003C Reserved 4 2 E202 0040 External PLD Tick...

Page 109: ...termine the state of the abort switch A cleared condition indicates the abort switch is not depressed while a set condition indicates the abort switch is asserted SAFE_START ENV safe start This bit reflects the current state of the ENV safe start select switch A set condition indicates that firmware should use the safe ENV settings A cleared condition indicates that the ENV settings programmed in ...

Page 110: ...learing this bit will enable writes to the EEPROM devices Setting this bit write protects the devices The devices are write protected following a reset BRD_RST Board reset These bits force a hard reset of the board If a pattern is written in bits 5 7 where bit 7 is set bit 6 is cleared and bit 5 is set 101 a hard reset is generated Any other pattern written in bits 5 7 does not generate a hard res...

Page 111: ...the front panel LED USR1_LED User LED 1 This bit controls the USR1 LED located on the front panel A set condition illuminates the front panel LED and a cleared condition extinguishes the front panel LED USR2_LED User LED 2 This bit controls the planar USR2 LED A set condition illuminates the LED and a cleared condition extinguishes the LED USR3_LED User LED 3 This bit controls the planar USR3 LED ...

Page 112: ...e FLASH BANK WP switch A set condition indicates that the entire Flash bank is write protected A cleared condition indicates that the Flash bank is not write protected F_WP_SW Software Flash bank write protect This bit provides software controlled protection against inadvertent writes to the Flash memory devices A set condition indicates that the entire Flash is write protected A cleared condition...

Page 113: ... set condition indicates that bus A is operating in PCI X mode A cleared condition indicates PCI mode PCI_A_64B PCI bus A 64 bit A set condition indicates that bus A is enabled to operate in 64 bit mode A cleared condition indicates 32 bit mode RSVD Reserved for future implementation Table 6 8 PCI Bus A Status Register REG PCI Bus A Status Register 0xE2000004 BIT 7 6 5 4 3 2 1 0 FIELD RSVD RSVD RS...

Page 114: ...he PrPMC module installed in PMC site 1 is ready for enumeration when set If cleared the PrPMC module is not ready for enumeration If no PrPMC is installed this bit is always set ERDY2 EREADY2 Indicates that the PrPMC module installed in PMC site 2 is ready for enumeration when set If cleared the PrPMC module is not ready for enumeration If no PrPMC is installed the bit is always set 5 0V_VIO 5 0V...

Page 115: ...C PCI X bus C A set condition indicates that bus C is operating in PCI X mode A cleared condition indicates PCI mode PCI_C_64B PCI bus C 64 bit A set condition indicates that bus C is enabled to operate in 64 bit mode A cleared condition indicates 32 bit mode RSVD Reserved for future implementation Table 6 10 PCI Bus C Status Register REG PCI Bus C Status Register 0xE2000006 BIT 7 6 5 4 3 2 1 0 FI...

Page 116: ...s not asserted If set the TSEC2 interrupt is asserted FEC_PHY FEC PHY interrupt If cleared the FEC interrupt is not asserted If set the FEC interrupt is asserted RSVD Reserved for future implementation 6 1 11 Presence Detect Register The MVME3100 provides a Presence Detect register that may be read by the system software to determine the presence of optional devices Table 6 11 Interrupt Detect Reg...

Page 117: ... RSVD Reserved for future implementation 6 1 12 PLD Revision Register The MVME3100 provides a PLD Revision register that may be read by the system software to determine the current revision of the timers registers PLD PLD_REV 8 bit field containing the current timer register PLD revision The revision number starts with 01 FIELD RSVD RSVD RSVD RSVD RSVD PEP PMC2P PMC1P OPER R R R R R R R R RESET 0 ...

Page 118: ...d Day vv Version 6 1 14 Test Register 1 The MVME3100 provides a 32 bit general purpose read write register that can be used by software for PLD test or general status bit storage TEST1 General purpose 32 bit read write field Table 6 14 PLD Data Code Register REG PLD Data Code Register 0xE200000C BIT 31 24 23 16 15 8 7 0 FIELD yy mm dd vv OPER R W RESET xxxx Table 6 15 Test Register 1 REG Test Regi...

Page 119: ... implemented in the timers registers PLD These registers are 32 bit registers and are not byte writable The following sections describe the external timer prescaler and control registers 6 1 16 1 Prescalar Register The prescaler provides the clock required by each of the four timers The tick timers require a 1 MHz clock input The input clock to the prescaler is 25 MHz The default value is set for ...

Page 120: ... counter is reset to 0 when it compares with the compare register When this bit is low the counter is not reset COVF Clear overflow bits The overflow counter is cleared when a 1 is written to this bit OVF Overflow bits These bits are the output of the overflow counter The overflow counter is incremented each time the tick timer sends an interrupt to the local bus interrupter The overflow counter c...

Page 121: ...e compare register value for a specific period T Compare register value T us When programming the tick timer for periodic interrupts the counter should be cleared to zero by software and then enabled If the counter does not initially start at 0 the time to the first interrupt may be longer or shorter than expected The rollover time for the counter is 71 6 minutes Table 6 19 Tick Timer Compare Regi...

Page 122: ...egister in the TSi148 provides the VMEbus geographical address of the MVME3100 This register reflects the inverted states of the geographical address pins at the 5 row 160 pin P1 connector Table 6 20 Tick Timer Counter Registers REG Tick Timer 1 Counter Register 0xE202 0018 32 bits Tick Timer 2 Counter Register 0xE202 0028 32 bits Tick Timer 3 Counter Register 0xE202 0038 32 bits Tick Timer 4 Coun...

Page 123: ...540 Interrupt Controller on page 129 z Local Bus Controller Chip Select Assignments on page 130 z Two Wire Serial Interface on page 130 z User Configuration EEPROM on page 131 z VPD EEPROM on page 132 z RTM VPD EEPROM on page 132 z Ethernet PHY Address on page 132 z Flash Memory on page 133 z PCI IDSEL Definition on page 134 z PCI Arbitration Assignments on page 136 z Clock Distribution on page 13...

Page 124: ...rogramming information Table 7 1 MPC8540 Power on Reset Configuration Settings MPC8540 Signal Select Option Default Setting Description State of Bit vs Function 1 PCI_REQ64_L PLD logic 0 PCI 32 Configuration 0 PCI PCI X interface is 64 bit 1 PCI PCI X interface is 32 bit PCI_GNT1_L Resistor 0 PCI Interface I O Impedance 0 25 ohm drivers 1 42 ohm drivers PCI_GNT2_L Resistor 1 PCI Arbiter Configurat...

Page 125: ...tors 111 Boot ROM Location 000 PCI PCI X 001 DDR SDRAM 011 RapidIO 101 Local Bus GPCM 8 bit ROM 110 Local Bus GPCM 16 bit ROM 111 Local Bus GPCM 32 bit ROM TSEC2_ TXD7 Resistor 0 TSEC2 Protocol Configuration 0 TSEC2 controller uses GMII protocol or RGMII if TSEC2 configured in reduced mode 1 TSEC2 controller uses TBI protocol or RTBI ifTSEC2 configured in reduced mode Table 7 1 MPC8540 Power on Re...

Page 126: ...E TSEC2_ TXD 2 4 Fixed 000 RapidIO Device ID 3 lower order bits 000 Unconnected Inputs LA27 Resistor 1 CPU Boot Configuration 0 CPU boot hold off mode3 1 e500 core boots without waiting for configuration by an external master LA 28 31 PLD logic 0011 for 100 MHz PCI bus 0101 for 66 MHz PCI bus CCB Clock PLL Ratio CCB Clock SYSCLK 0000 16 1 0010 2 1 0011 3 1 0100 4 1 0101 5 1 0110 6 1 1000 8 1 1001 ...

Page 127: ...ors 11 MPC8540 Host Agent Configuration 00 Agent of RapidIO and PCI PCI X 01 Agent of a RapidIO 10 Agent of a PCI PCI X 11 Host of both RapidIO and PCI PCI X LALE LGPL2 Resistor 01 e500 Core Clock PLL Ratio e500 Core CCB Clock 00 2 1 01 5 2 10 3 1 11 7 2 LGPL0 LGPL1 Fixed 11 RapidIOTransmitClock Source 00 Reserved 01 RapidIO rcv clock is source of xmit clock 10 RapidIOxmitclockinputs are source of...

Page 128: ...C address mode 10 Boot sequencer enabled with extended I2C address mode 11 Boot sequencer disabled LAD 28 31 Resistor 7 XX General Purpose POR Configuration XX General purpose POR configuration vector to be placed in CPPORCR register bits MSRCID0 Resistor 1 Memory Debug Configuration 0 Debug info from the LBC is driven on MSRCID MDVAL pins 1 Debug info from the DDR SDRAM controller is driven on MS...

Page 129: ...nterrupt assignments along with corresponding edge levels and polarities are shown in the following table Refer to the MPC8540 Reference Manual listed in Appendix B Related Documentation for additional details regarding the operation of the MPC8540 PIC Table 7 2 MPC8540 Interrupt Controller Interrupt Edge Level Polarity Interrupt Source Notes 0 Level Low VME0 1 Level Low VME1 External Timers 1 2 L...

Page 130: ...ollowing table contains the I2C devices used for the MVME3100 and their assigned device addresses Table 7 3 LBC Chip Select Assignments LBC Bank Chip Select Local Bus Function Size Data Bus Width Notes 0 Boot Flash bank 32MB 128MB 32 bits 1 1 Optional second Flash bank 32MB 128MB 32 bits 1 2 Control Status registers 64 KB 32 bits 2 3 Quad UART 64 KB 8 bits 4 32 bit timers 64 KB 32 bits 3 5 7 Not u...

Page 131: ... MPC8540 memory controller chip selects 0 and 1 1 A2 001 Reserved A4 010 65 536 x 8 User configuration 2 A6 011 65 536 x 8 User configuration 2 A8 100 8192 x 8 VPD on board system configuration 2 AA 101 8192 x 8 RTM VPD off board configuration 2 3 AC 110 Reserved AE 111 Reserved D0 N A N A DS1375 real time clock 1 Each SPD defines the physical attributes of each bank or group of banks If both bank...

Page 132: ...al EEPROM containing VPD configuration information specific to the MVME3100 RTM Typical information that may be present in the EEPROM may include manufacturer board revision build version date of assembly options present etc The RTM VPD EEPROM device ID is user selectable with the recommended value for MVME3100 as shown in Table 7 4 on page 130 Refer to the2 Wire Serial EEPROM Datasheet listed in ...

Page 133: ...Regardless of the state of the software Flash write protect bit in the Flash Control Status register write protection is enabled for both banks when this switch is ON When this switch is OFF write protection iscontrolledby the state of the software Flash write protect bit and can only be disabled by clearing this bit in the Flash Control Status register Refer to Flash Control Status Register on pa...

Page 134: ...chofthe PCIbusesonthe board along with thecorrespondinginterrupt assignment to the PIC external interrupt pins Refer to the MPC8540 Reference Manual and PCI6520CB Data Book and for details on generating configuration cycles on each of the PCI busses Table 7 7 IDSEL and Interrupt Mapping for PCI Devices PCI Bus Device Number Field AD Line for IDSEL PCI Device or Slot Device Slot INT to MPC8540 Ext ...

Page 135: ...8 PMCSpan Slot 1 IRQ6 IRQ7 IRQ4 IRQ5 0b0_0011 19 PMCSpan Slot 2 IRQ7 IRQ4 IRQ5 IRQ6 0b0_0100 20 PMCSpan Slot 3 IRQ4 IRQ5 IRQ6 IRQ7 0b0_0101 21 PMCSpan Slot 4 IRQ5 IRQ6 IRQ7 IRQ4 Table 7 7 IDSEL and Interrupt Mapping for PCI Devices continued PCI Bus Device Number Field AD Line for IDSEL PCI Device or Slot Device Slot INT to MPC8540 Ext IRQ INTA INTB INTC INTD Table 7 8 Planar PCI Device Identifica...

Page 136: ...k Distribution The clock function generates and distributes all of the clocks required for system operation The clock tree is designed in such a manner as to maintain the strict edge to edge jitter and low clock to clock skew required by the devices Additional clocks required by individual devices are generated near the devices using individual oscillators Table 7 10 on page 137 lists Table 7 9 PC...

Page 137: ...ed to be synchronized with each other Table 7 10 Clock Assignments Device Clock Signal s Frequency MHz Clock Tree Source Qty VIO MPC8540 CLK_8540 66 100 A 1 3 3V TSi148 CLK_VME 66 100 A 1 3 3V sATA CLK_SATA 66 100 A 1 3 3v PCI6520 Primary CLK_P2P_ABP 66 100 A 2 3 3V CLK_P2P_ACP PMC1 CLK_PMC1 33 66 100 B 1 3 3V PMC2 CLK_PMC2 33 66 100 B 1 3 3V PCI6520 Secondary CLK_P2P_ABS 33 66 100 B 1 3 3V CLK_P2...

Page 138: ...by the control and timers PLD The LBC clock is derived from a divide by 2 4 or 8 ratio of the internal CCB core complex bus clock as determined by the clock ratio register LCRR CLKDIV For proper operation of the local bus CLKDIV must be set for divide by 8 which is the default value The software must leave this register configured for divide by 8 during initialization ControlandTimers PLD CLK25_33...

Page 139: ...of 50 watts A 2 Environmental Specifications Table A 2 lists the environmental specifications along with the board dimensions Table A 1 Current Requirements Model Power MVME3100 No PMCs or peripherals attached Typical 4 5 A 22 5 W 5 V 0 Maximum 5 6 A 28 W 5 0 V Table A 2 MVME3100 Specifications Characteristics Specifications Operating Temperature 0 to 55 C 32 F to 131 F or inlet air temperature wi...

Page 140: ...cuits z Do not operate the product outside the specified environmental limits Make sure the product is completely dry and there is no moisture on any surface before applying power Table A 3 Thermally Significant Components Reference Designator Generic Description Max Allowable Component Temperature Celsius Measurement Location U1012 Processor 0ºC to 105ºC 32 F to 221 F Junction XU1 Memory 0ºC to 7...

Page 141: ...Specifications MVME3100 Single Board Computer Installation and Use 6806800M28C 141 Figure A 1 Primary Side Components U21 U1012 U1010 U5000 U1052 U1051 XU1 ...

Page 142: ...tion case or ambient as specified in the table Junction temperature refers to the temperature measured by an on chip thermal device Case temperature refers to the temperature at the top center surface of the component Air temperature refers to the ambient temperature near the component Figure A 2 Secondary Side Components U1028 U1054 U1039 U1029 ...

Page 143: ... refer to the following table for manufacturers data sheets or user s manuals As an additional help a source for the listed document is provided Please note that while these sources have been verified the information is subject to change without notice Table B 1 Emerson Network Power Embedded Computing Documents Document Title Publication Number MVME3100 Single Board Computer Programmer s Referenc...

Page 144: ...t Silicon Image Corporation Web Site http www siliconimage com docs SiI DS 0160 C pdf SiI DS 0160 C pdf S29GLxxxN MirrorBit Flash Family S29GL512N S29GL256N S29GL128N AMD Inc Web Site www amd com us en FlashMemory 27631 Revision A Amendment 3 May 13 2004 mPD720101 USB 2 0 Host Controller Datasheet NEC Electronics Web Site www necel com usb en document index html S16265EJ3V0DS00 April 2003 PCI6520C...

Page 145: ...eb Site www maxim ic com DS1621 Maxim DS1375 Serial Real Time Clock Maxim Integrated Products Web Site www maxim ic com Rev 121203 TSOP Type I Shielded Metal Cover SMT Yamaichi Electronics USA Web Site www yeu com Table B 2 Manufacturers Documents continued Document Title and Source Publication Number Table B 3 Related Specifications Document Title and Source Publication Number VITA http www vita ...

Page 146: ...tute of Electrical and Electronics Engineers Inc P1386 Draft 2 0 IEEE PCI Mezzanine Card Specification PMC Institute of Electrical and Electronics Engineers Inc P1386 1 Draft 2 0 USB http www usb org developers docs Universal Serial Bus Specification Revision 2 0 April 27 2000 Table B 3 Related Specifications continued Document Title and Source Publication Number ...

Page 147: ...Related Documentation MVME3100 Single Board Computer Installation and Use 6806800M28C 147 ...

Page 148: ...other application may require safety evaluation specific to that application Only personnel trained by Emerson or persons qualified in electronics or electrical engineering are authorized to install remove or maintain the product The information given in this manual is meant to complete the knowledge of a specialist and must not be used as replacement for qualified personnel Keep away from live ci...

Page 149: ...r will be required to correct the interference at his own expense Installation Damage of Circuits Electrostatic discharge and incorrect blade installation and removal can damage circuits or shorten their life Before touching the blade or electronic components make sure that you are working in an ESD safe environment Damage of the Product and Additional Devices and Modules Incorrect installation or...

Page 150: ...Do not operate the product outside the specified environmental limits Make sure the product is completely dry and there is no moisture on any surface before applying power Environment Environmental Damage Improperly disposing of used products may harm the environment Always dispose of used products according to your country s legislation and manufacturer s instructions ...

Page 151: ...Safety Notes MVME3100 Single Board Computer Installation and Use 6806800M28C 151 ...

Page 152: ...itte an die für Sie zuständige Geschäftsstelle von Emerson Das Produkt wurde entwickelt um die Sicherheitsanforderungen für SELV Geräte nach der Norm EN 60950 1 für informationstechnische Einrichtungen zu erfüllen Die Verwendung des Produkts in einer anderen Anwendung erfordert eine Sicherheitsüberprüfung für diese spezifische Anwendung Einbau Wartung und Betrieb dürfen nur von durch Emerson ausge...

Page 153: ...en im Hochfrequenzbereich auftreten Warnung Dies ist eine Einrichtung der Klasse A Diese Einrichtung kann im Wohnbereich Funkstörungen verursachen In diesem Fall kann vom Betreiber verlangt werden angemessene Maßnahmen durchzuführen Installation Beschädigung von Schaltkreisen Elektrostatische Entladung und unsachgemäßer Ein und Ausbau von Blades kann Schaltkreise beschädigen oder ihre Lebensdauer ...

Page 154: ...served gekennzeichnet sind Betrieb Beschädigung des Blades Hohe Luftfeuchtigkeit und Kondensat auf der Oberfläche des Blades können zu Kurzschlüssen führen Betreiben Sie das Blade nur innerhalb der angegebenen Grenzwerte für die relative Luftfeuchtigkeit und Temperatur Stellen Sie vor dem Einschalten des Stroms sicher dass sich auf dem Blade kein Kondensat befindet Umweltschutz Umweltverschmutzung...

Page 155: ......

Page 156: ...Network Power logo are trademarks and service marks of Emerson Electric Co All other product or service names are the property of their respective owners 2011 Emerson Electric Co Emerson Network Power The global leader in enabling Business Critical Continuity AC Power Systems Connectivity DC Power Systems Embedded Computing Embedded Power Integrated Cabinet Solutions Outside Plant Power Switching ...

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