Functional Description
ATCA-F140 Installation and Use (6806800M67H)
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4.12.2.2 Broadcom BCM56846
A power-on or hard reset is initiated by an active low pulse on the SYS_RST_L signal of the
Broadcom BCM56846 Fabric Channel Switch. The initialization process loads all the pin
configurable modes, clears all switching tables and places the switch in a disabled and idle
state.
4.12.3 Physical Interconnect Devices
Broadcom PHYs use a hardware reset pin RESET_L, which resets all internal nodes to a known
state. RESET_L is always asserted after power-up. Mode pins are latched at the time that
hardware reset is deasserted.
4.12.4 AMC Bay
The IPMC on the ATCA-F140 is responsible for resetting the AMC bay. It initiates a reset cycle
after an AMC module is plugged in or if the payload power of the carrier board is in a power
cycle. The IPMC drives the ENABLE# signal active low as an input to the AMC module. The
82571EB device is reset in parallel to the AMC.
4.12.5 Rear Transition Module
The RTM-ATCA-F140 is reset by two reset sources, the IPMC and the reset controller inside the
FPGA. During normal operation, the RTM-ATCA-F140 and the ATCA-F140 front board are
treated as one reset domain using the RTM_RST_L signal from the FPGA.
4.13 Interrupt Structure
All external interrupts belonging to the service processor interrupt structure are routed to the
P2020 QorIQ Integrated Processor. The PIC inside the P2020 QorIQ Integrated Processor is
compliant with the OpenPIC architecture. The interrupt controller provides interrupt
management, and is responsible for receiving hardware-generated interrupts from different
sources (both internal and external), prioritizing them, and delivering them to the CPU for
servicing. The PIC is set to the mixed mode on ATCA-F140 so that both internal and external
interrupts are delivered using normal priority and delivery mechanisms.
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