
Intr
oduc
tion
Introduction
User's Manual
PC_EYE®2+
1—3
Figure 1—2: Block-Diagram PC_EYE 260
Hirose
X103
X104
X105
X102
10 pin
Header
GPO (0..11)
GPO (12..15)
Input
B
15 pin
HD
I1/G(0..7)
I2/B(0..7)
I3(0..7)
Ext-Clock(0..3)
Ext-Trigger(0..3)
GPI (0..3)
I0/R(0..7)
Sync4
Sync3
Sync2
Sync1
Opto
Clock
Restoration
MUX
4 x
4:1
FPGA-2
DMA-
Controller
Frontend
Sync-
detect
A/D
Sync-
detect
A/D
Sync-
detect
A/D
Sync-
detect
A/D
ICD2061
EE-Prom
PCI-
BUS
FPGA-1
PCI-Core
Sync-
detect
Sync0