
In
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Introduction
User's Manual
1—2
PC_EYE®2+
Figure 1—1: Block Diagram PC_EYE 250
10 pin
Header
GPO (12..15)
EE-Prom
PCI-
BUS
FPGA-1
PCI-Core
GPO (0, 1, 3, 4)
FPGA-2
DMA-
Controller
Frontend
Sync0
Sync-
detect
Input
A
15 pin
HD
MUX
4 x
4:1
A/D
I0/R(0..7)
Sync1
Sync-
detect
A/D
I1/G(0..7)
Sync2
Sync-
detect
Input
B
15 pin
HD
A/D
I2/B(0..7)
Sync3
Sync-
detect
I3(0..7)
A/D
Sync4
Sync-
detect
Ext-Trigger(0..3)
Opto
Ext-Clock(0..1)
Clock
Restoration
ICD2061