Trion T20 BGA256 Development Kit User Guide
•
User inputs:
—
8 LEDs on T20F256C bank 3 for user outputs
—
3 pushbutton switches (connected to bank 1A I/O pins)
—
3 DIPswitches (connected to bank 3 I/O pins) for user inputs
•
3 GPIO headers and 2 LVDS headers to connect to external devices
•
Power good and T20F256C configuration done LEDs
Overview
The board features the Efinix
®
T20 programmable device in a 256-ball FBGA package, which
is fabricated using Efinix
®
Quantum
™
technology. The Quantum
™
-accelerated programmable
logic and routing fabric is wrapped with an I/O interface in a small footprint package. T20
devices also include embedded memory blocks and multiplier blocks (or DSP blocks). You
create designs for the T20 device in the Efinity
®
software, and then download the resulting
configuration bitstream to the board using the USB connection.
Note:
For more information on T20 FPGAs, refer to the
, which you can download in our
Support Center under Docs (
Figure 2: Trion
™
T20 BGA256 Development Board Components
256 Mb SDR SDRAM
Micro-USB
Port (CON2)
50 MHz Oscillator
GPIO Banks
1B, 1C (H4)
Clock Select Header (J3)
(On-Board Oscillator or SMA)
5 V DC Input
Jack (CON1)
GPIO Bank 3 (H3)
FTDI Module
SMA Clock Input (J5)
LVDS Receiver (RX)
& Clock (CON3)
LVDS Transmitter (TX)
(CON4)
5 V Power for
External Devices
GPIO Banks
1D, 1E (H2)
Power Switch (S2)
SPI Header (H1)
JTAG Header (H6)
CDONE (D1) &
NSTATUS (D2) LEDs
User DIPswitches (SW3)
User Pushbuttons (SW4 - SW6)
User LEDs (D3 - D10)
Banks 1B/1C
Voltage Select (H7)
Banks 1D/1E
Voltage Select (H8)
Trion FPGA
T20BGA256C
The FTDI FT2232H module has two channels to support SPI (FTDI interface 0) and
JTAG (FTDI interface 1) configuration. It receives the T20 configuration bitstream from a
USB host and writes to the on-board SPI NOR flash memory. After a reset in SPI passive
mode, the FTDI controller can also write the configuration bitstream directly to the
FPGA. Additionally, it supports direct JTAG programming mode in which it writes the
configuration bitstream directly to the FPGA through the JTAG interface.
Note:
Refer to
AN 006 Configuring Trion FPGAs
www.efinixinc.com
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