TSEV8308500 Evaluation Board
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User Guide
Page 1: ...TSEV8308500 Evaluation Board User Guide...
Page 2: ......
Page 3: ...1 Board 2 1 2 2 AC Inputs Digital Outputs 2 1 2 3 DC Functions Settings 2 1 2 4 Power Supplies 2 2 2 5 Board Implementation 2 2 Section 3 Operating Procedures and Characteristics 3 1 3 1 Introduction...
Page 4: ...09 e2v semiconductors SAS 2009 4 9 Test Bench Description 4 5 Section 5 Package Description 5 1 5 1 TS8308500GL Pinout 5 1 5 2 Thermal Characteristics 5 3 Section 6 Schematics 6 1 6 1 TSEV8308500 Elec...
Page 5: ...le evaluation of the TS8308500 ADC performances over the temperature range The TS8308500 Evaluation Board EB is very straightforward as it only implements the TS8308500 ADC device SMA connectors for i...
Page 6: ...ifferential Clock inputs Z0 50 Z0 50 VIN VINB ADC Gain Adjust GAIN GND VCC GORB GORB DR DRB D0 D0B Z0 50 Z0 50 Z0 50 Z0 50 D7 D7B OR ORB VCC VCC 5V GND VPLUSD GND 0V VPLUSD 0V ECL VPLUSD 2 4V LVDS AVE...
Page 7: ...ls with specific characteristics A low insertion loss RO4003 Hydrocarbon wovenglass dielectric layer of 200 m thickness chosen for its low loss 0 318 dB inch and enhanced dielectric consistency in the...
Page 8: ...ilitary temperature range 1 4 Analog Input Clock Input and De embedding Fixture Accesses The differential active inputs Analog Clock De embedding fixture are provided by SMA connectors Reference VITEL...
Page 9: ...r supplies 2 2 AC Inputs Digital Outputs The board uses 50 impedance microstrip lines for the differential analog inputs clock inputs and differential digital outputs including the Out of Range Bit an...
Page 10: ...ce pins for microstrip line back termination and bypassing Connecting the positive supply pads The positive supply pads denoted VCC The corresponding VCC pad numbers are 19 21 23 30 39 40 Each VCC pow...
Page 11: ...S8308500 clock inputs with bal anced signals Connect directly the RF sources to the in phase analog and clock inputs of the converter However dynamic performances can be somewhat improved by entering...
Page 12: ...ectively from 10 Msps up to 500 Msps in binary output format and 10 Msps up to 500 Msps in Gray output format It is capable of sam pling analog input waveforms ranging from DC up to 1 3 GHz 3 3 Electr...
Page 13: ...ply current dedicated to TS8308500 ADC only ICC 400 425 mA IPLUSD 120 130 mA IEEA 170 185 mA IEED 140 160 mA Positive supply voltage not used by default If installed dedicated to MC100EL16 differentia...
Page 14: ...Operating Procedures and Characteristics 3 4 TSEV8308500 Evaluation Board User Guide 0968D BDC 01 09 e2v semiconductors SAS 2009...
Page 15: ...Moreover the clock input common mode may be 0V or 1 3V if ECL input format is used for the clock inputs As for the analog input either clock input can be chosen leaving the other input open as both cl...
Page 16: ...gain from approximately 0 85 up to 1 15 The gain adjust transfer function is given below Figure 4 1 ADC Gain Adjust 4 6 SMA Connectors and Microstrip Lines De embedding Fixture Attenuation in microstr...
Page 17: ...rce current and measure the VBE voltage across the dedicated transistor connected between pads 32 and 33 The measurement method consists of forcing a 3 mA current flowing into a diode mounted transist...
Page 18: ...output remains at logical zero and is independent of the external free run ning encoding clock The Data ready output signal DR DRB is reset to logical zero after TRDR 720 ps typical TRDR is measured...
Page 19: ...guration Signal Generator Signal Generator 121 dBc Hz at 1 Hz offset from fc 0 180 Hybrid 0 180 Hybrid BPF Data Acquisition System TS8308500 ADC 117 dBc Hz at 20 Hz offset from fc PC GPIB CLKB CLK DR...
Page 20: ...Application Information 4 6 TSEV8308500 Evaluation Board User Guide 0968D BDC 01 09 e2v semiconductors SAS 2009...
Page 21: ...kage 1 2 3 4 5 6 7 8 9 10 11 VPLUSD VPLUSD NC B3b DRb GND GND B4 B5 NC DVEE GND GND B2 VPLUSD B3 DR B4b B5b VPLUSD B6b B2b B6 B1 B7b B1b B7 B0 ORb B0b OR Gorb VCC VCC GAIN VCC VCC GND GND GND GND VCC...
Page 22: ...er VINB 1 L4 Inverted phase of ECL clock input signal CLK CLK C1 In phase ECL clock input signal The analog input is sampled and held on the rising edge of the CLK signal CLKB D1 Inverted phase of ECL...
Page 23: ...l component heatsink or PCBoard As an example 2 0 C W can be taken for 50 m of thermal grease 5 2 3 CBGA68 Board Assembly with External Heatsink It is recommended to use an external heatsink or PCBoar...
Page 24: ...ure Range Screening Level Comments TSX8308500GL CBGA 68 Ambient Prototype Prototype Version TS8308500CGL CBGA 68 C grade 0 C Tc Tj 90 C Standard TS8308500VGL CBGA 68 V grade 40 C Tc Tj 110 C Standard...
Page 25: ...TSEV8308500 Evaluation Board User Guide 6 1 0968D BDC 01 09 e2v semiconductors SAS 2009 Section 6 Schematics 6 1 TSEV8308500 Electrical Schematics Please see the following figures...
Page 26: ...Schematics 6 2 TSEV8308500 Evaluation Board User Guide 0968D BDC 01 09 e2v semiconductors SAS 2009 Figure 6 1 TSEV8308500 Electrical Schematic...
Page 27: ...Option Using MC100EL16 Differential Receivers VDD 2V IN INb OUT OUTb To output connector Z0 50 Z0 50 50 50 Digital data 50 differential termination GND D0 D7 OR DR D0B D7B ORB DRB 100 pF R4 50 R3 50 O...
Page 28: ...User Guide 0968D BDC 01 09 e2v semiconductors SAS 2009 6 2 Evaluation Board Schematics Figure 6 4 Component Side Description Figure 6 5 Ground Plane Figure 6 6 Power Supplies Planes Figure 6 7 TSEV83...
Page 29: ...Waterhouse Lane Chelmsford Essex CM1 2QU England Tel 44 0 1245 493493 Fax 44 0 1245 492492 mailto enquiries e2v com e2v sas 16 Burospace F 91572 Bi vres Cedex France Tel 33 0 16019 5500 Fax 33 0 1601...
