manualshive.com logo in svg

Diodes PI7C9X2G304SL, Manual, Page: 1 / 89

Share
Download
Diodes PI7C9X2G304SL Manual Download Page 1

Document Number DS39933 Rev  2-2

 

 

 

 

 

 

 

 

 

 

 

 

PI7C9X2G304SL 

PCI EXPRESS GEN 2 PACKET SWITCH 

3-Port, 4-Lane, SlimPacket PCIe 2.0 Packet Switch

 

DATASHEET

 

REVISION 2-2 

September 2017

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1545 Barber  Lane  Milpitas, CA 95035 

Telephone:  408-232-9100 

FAX:  408-434-1040 

Internet: 

http://www.diodes.com

 

 

 

Summary of Contents for PI7C9X2G304SL

Page 1: ...7C9X2G304SL PCI EXPRESS GEN 2 PACKET SWITCH 3 Port 4 Lane SlimPacket PCIe 2 0 Packet Switch DATASHEET REVISION 2 2 September 2017 1545 Barber Lane Milpitas CA 95035 Telephone 408 232 9100 FAX 408 434...

Page 2: ...United States international or foreign patents pending Product names and markings noted herein may also be covered by one or more United States international or foreign trademarks This document is wri...

Page 3: ...ircuit Updated Section 5 1 7 Drive De Emphasis Updated Section 7 2 75 Device Capabilities Register Max_Payload_Size Supported Updated Section 13 Ordering Information Updated Table 11 2 DC Electrical C...

Page 4: ...19 5 1 6 DRIVE AMPLITUDE 20 5 1 7 DRIVE DE EMPHASIS 21 5 1 8 TRANSMITTER ELECTRICAL IDLE LATENCY 21 5 2 DATA LINK LAYER DLL 21 5 3 TRANSACTION LAYER RECEIVE BLOCK TLP DECAPSULATION 22 5 4 ROUTING 22 5...

Page 5: ...ET 30h 44 7 2 25 CAPABILITY POINTER REGISTER OFFSET 34h 44 7 2 26 INTERRUPT LINE REGISTER OFFSET 3Ch 45 7 2 27 INTERRUPT PIN REGISTER OFFSET 3Ch 45 7 2 28 BRIDGE CONTROL REGISTER OFFSET 3Ch 45 7 2 29...

Page 6: ...ER OFFSET 104h 66 7 2 84 UNCORRECTABLE ERROR MASK REGISTER OFFSET 108h 67 7 2 85 UNCORRECTABLE ERROR SEVERITY REGISTER OFFSET 10Ch 67 7 2 86 CORRECTABLE ERROR STATUS REGISTER OFFSET 110 h 68 7 2 87 CO...

Page 7: ...80 9 2 BYPASS REGISTER 80 9 3 DEVICE ID REGISTER 80 9 4 BOUNDARY SCAN REGISTER 81 9 5 JTAGBOUNDARY SCAN REGISTER ORDER 81 10 POWER MANAGEMENT 83 11 POWER SEQUENCE 84 12 ELECTRICAL AND TIMING SPECIFICA...

Page 8: ...SETTINGS 21 TABLE 5 9 SUMMARY OF PCI EXPRESS ORDERING RULES 23 TABLE 6 1 SMBUS ADDRESS PIN CONFIGURATION 36 TABLE 7 1 REGISTER ARRAY LAYOUT FOR VC ARBITRATION 74 TABLE 7 2 TABLE ENTRY SIZE IN 4 BITS 7...

Page 9: ...d Power Saving Empty downstreamports are set to idle state to minimize power consumption Link Power Management Supports L0 L0s L1 L2 L2 L3Ready and L3 link power states Active state power management f...

Page 10: ...or packets destined to different egress ports since the operation of producer consumer model has to be retained otherwise the system might occur hang up problem On the other hand the Switch places rep...

Page 11: ...11 September 2017 Document Number DS39933 Rev 2 2 www diodes com Diodes Incorporated PI7C9X2G304SL used by the downstream PCI Express end devices The clock buffer feature can be enabled and disabled...

Page 12: ...e internal states of wholechipexcept stickylogics are initialized Please refer toTable 11 2forPREST_L spec DWNRST_L 2 1 6 5 O Downstream Device Reset Active LOW DWNRST_Lprovides a reset signal to the...

Page 13: ...19 I Present WhenPRSNT is assertedlow it indicates that the device is present in theslot ofdownstreamport Otherwise it indicates the absence of the device PRSNT x is correspondent toPort x where x 1...

Page 14: ...eration Port Status OutputEnable In debugmode it is usedto enable PortStatus output TEST1 9 I Test1 The pinis for internal test purpose It shouldbe tiedto 3 3V through a 5 1K ohmpull upresistorfor nor...

Page 15: ...ins CVDDR 79 82 84 P VDDR Supply 3 3V Usedas referenceclockpower pins VDDCAUX 13 14 P VDDCAUXSupply 1 0V Usedas auxiliary core power pins VAUX 15 P VAUXSupply 3 3V Usedas auxiliary I O power pins AVDD...

Page 16: ...75 NC 107 PETN 2 12 VSS 44 GPIO 7 76 NC 108 AVDD 13 VDDCAUX 45 SLOT_IMP 1 77 REFCLKO_N 2 109 CGND 14 VDDCAUX 46 SLOT_IMP 2 78 REFCLKO_P 2 110 REFCLKP 15 VAUX 47 NC 79 CVDDR 111 REFCLKN 16 TEST2 48 NC...

Page 17: ...onsists of framer 8B 10B encoder decoder receiver elastic buffer and PIPE PHY control status circuitries To provide the flexibility for port configuration each lane has its own control and status sign...

Page 18: ...ng mode the transmitters implement de emphasis while in half swing mode the transmitters do not The Transmitter Swing field in the PHY Parameter 2 Register offset 7Ch Bit 30 is used for the selection...

Page 19: ...e Emphasis Condition Swing Condition C_DRV_LVL_3P5_NOM 3 5 db Full C_DRV_LVL_6P0_NOM 6 0 db Full C_DRV_LVL_HALF_NOM N A Half Table 5 6 Drive Amplitude Base Level Settings Setting Amplitude mV pd Setti...

Page 20: ...value due to process variations andenvironment factors such as voltage overheadcompression package losses boardlosses andothereffects 5 1 8 TRANSMITTER ELECTRICAL IDLE LATENCY After the last character...

Page 21: ...forward I O or memory transactions to the destination port which is located within the address range indicated by the address field carried in the packet header The packet header indicates the packet...

Page 22: ...quest cannot be mapped into VC1 5 6 4 CPLH CPLH queue provides TLP header space for completion packets Each header space takes twelve bytes to accommodate a 3 DW header Please note that there are no 4...

Page 23: ...st transaction Such transactions are actually transmitting in the opposite directions and hence have no ordering relationship 5 Posted Request transactions must be given opportunities to pass Non post...

Page 24: ...accessed and regenerate the message that terminates at receiver to RC if acting as an upstreamport 5 12 Access Control Service Traditionally the packet routing between the peer to peer downstreamports...

Page 25: ...During a reset the Switch will automatically load the information data from the EEPROM if the automatic load condition is met The first offset in the EEPROM contains a signature If the signature is re...

Page 26: ...Reserved 4Eh PM Data for Port 0 PM Capability for Port 0 50h PM Data for Port 1 PM Capability for Port 1 52h PM Data for Port 2 PM Capability for Port 2 54h Reserved 56h Reserved 58h Reserved 5Ah Rese...

Page 27: ...2 C4h Reserved C6h Reserved C8h Reserved CAh Reserved CCh Reserved CEh REV_TS_CTR Replay Time out Counter for Port 0 D0h REV_TS_CTR Replay Time out Counter for Port 1 D2h REV_TS_CTR Replay Time out Co...

Page 28: ...Bit 3 Max_Payload_Size Supportfor Port0 2 Bit 1 0 Indicated the maximum payloadsize that the device can support forthe TLP ASPMSupportfor Port0 2 Bit 3 2 Indicate the level of ASPM supportedon thePCI...

Page 29: ...or Port 0 2 Bit 15 0 XPIP_CSR5 15 0 1C 88h Port 0 2 88h Bit 23 16 8Ch Port0 2 8Ch Bit 23 21 98h Port 0 2 98h Bit 20 16 XPIP_CSR5 28 16 for Port 0 2 Bit 7 0 XPIP_CSR5 23 16 XPIP_CSR6 7 5 for Port0 2 Bi...

Page 30: ...30 16 PHY Parameter2_1 for Port 2 Bit 14 0 PHY parameter2 40h 7Ch Port0 7Ch Bit 12 8 90h Port 0 90h Bit 6 0 F0h Port 0 F0h Bit 6 78h Port 0 78h Bit 11 8Ch Port0 8Ch Bit 9 8 PHY Parameter 2_1for Port...

Page 31: ...te Bridge supports the D2 power management state Bit 7 6 PMESupport for D2andD1 states 53h 44h Port 1 44h Bit 31 24 Power Management DataforPort1 Bit 15 8 readonlyas Dataregister 54h 44h Port 2 44h Bi...

Page 32: ...henset the component uses the clock providedon the Connector Device specific Initialization forPort2 Bit 2 Whenset the DSI is required LPVC CountforPort2 Bit 3 Whenset the VC1 is allocatedtoLPVC of Eg...

Page 33: ...4h D4h Port2 D4h Bit 31 16 Slot Capability1 of Port 2 Bit 15 0 Mappingtothe highwordof slot capabilityregister B0h 80h Port 0 80h Bit 15 0 XPIP_CSR3_0 for Port 0 Bit 15 0 XPIP_CSR3 15 0 B2h 80h Port 1...

Page 34: ...5 8 Whenset it indicates the correspondingTC is mapped into VC1 F2h 15Ch Port 1 15Ch Bit 22 16 160h Port1 160h Bit 7 0 VC1 MAXTime Slot and TC VC Map for Port 1 Bit 6 0 The maximum timeslot supportedb...

Page 35: ...egisters that can be auto loaded by the EEPROM interface can also be read and written by the SMBus interface This feature allows increases in the systemexpandability and flexibility in systemimplement...

Page 36: ...ondary Bus Number Primary Bus Number 18h Secondary Status I O Limit Address I O Base Address 1Ch Memory Limit Address Memory Base Address 20h Prefetchable Memory Limit Address Prefetchable Memory Base...

Page 37: ...00h with a PCI Express Enhanced Capability header and the rest of capabilities are located at an offset greater than 0FFh relative to the beginning of PCI compatible configuration space 31 24 23 16 15...

Page 38: ...y SMBus or auto loadingfromEEPROM Resets to 2304h 7 2 3 COMMAND REGISTER OFFSET 04h BIT FUNCTION TYPE DESCRIPTION 0 I O Space Enable RW 0b Ignores I O transactions onthe primaryinterface 1b Enables re...

Page 39: ...t to 1 to enable support for the capabilitylist offset 34his the pointer to the data structure Reset to 1b 21 66MHz Capable RO Does not apply to PCI Express Must be hardwiredto0b 22 Reserved RO Reset...

Page 40: ...fieldis implementedby PCI Express devices as a RW fieldfor legacy compatibility but it has noimpact on any PCI Express device functionality Reset to 0b 7 2 8 PRIMARY LATENCY TIMER REGISTER OFFSET 0Ch...

Page 41: ...to 0h 7 2 15 I O LIMIT ADDRESS REGISTER OFFSET 1Ch BIT FUNCTION TYPE DESCRIPTION 11 8 32 bit Indicator RO Read as 01h to indicate 32 bit I O addressing 15 12 I O Limit Address 15 12 RW Defines the top...

Page 42: ...ess bits 31 20 andare able to be writtento The lower 20 bits correspondingto address bits 19 0 are assumedtobe 0 Reset to 000h 7 2 18 MEMORY LIMIT ADDRESS REGISTER OFFSET 20h BIT FUNCTION TYPE DESCRIP...

Page 43: ...LE MEMORY LIMIT ADDRESS UPPER 32 BITS REGISTER OFFSET 2Ch BIT FUNCTION TYPE DESCRIPTION 31 0 Prefetchable Memory Limit Address Upper 32 bits 63 32 RW Defines the upper 32 bits of a 64 bit top address...

Page 44: ...all I O addresses in the address range definedby the I O Base andLimit registers that arein the first 64KB of PCI I O address space top 768bytes of each1KB block Reset to 0b 19 VGA Enable RW 0b Ignor...

Page 45: ...s or auto loadingfrom EEPROM 25 D1 Power State Support RO Read as 1bto indicate Switch supports the D1 power management state The default value may be changedby SMBus or auto loadingfromEEPROM 26 D2 P...

Page 46: ...egister 15 8 Next ItemPointer RO Pointer points to theVendor specific capability register Reset to 64h 7 2 34 MESSAGE CONTROL REGISTER OFFSET 4Ch Downstream Port Only BIT FUNCTION TYPE DESCRIPTION 16...

Page 47: ...Not Support 23 18 VPD Address RW Contains DWORD address that is usedto generate reador writecycletothe VPD table storedin EEPROM Reset to 00_0000b 30 24 Reserved RsvdP Not Support 31 VPD operation RW...

Page 48: ...default value maybe changedby SMBus or auto loadingfromEEPROM Reset to 000h 12 Enable User Replay Timer RW When asserted the user definedreplaytime out value is be employed The default value may be c...

Page 49: ...may be changedby SMBus or auto loadingfrom EEPROM Reset to 0b 4 Credit Update Mode RW When set thefrequency ofreleasingnewcredit tothe link partner will be all types per update When clear thefrequenc...

Page 50: ...ngfrom EEPROM Reset to 0b 20 16 C_DRV_LVL_3P5_ NOM RO The default value may be changedby SMBus or auto loadingfrom EEPROM Reset to 1_0011b 25 21 C_DRV_LVL_6P0_ NOM RO The default value maybe changedby...

Page 51: ...17 P_DRV_LVL_NOM_ DELATA_EN RO The default value may be changedby SMBus or auto loadingfromEEPROM Reset to 0b 18 P_EMP_POST_MGN _DELATA_EN RO The default value may be changedby SMBus or auto loadingfr...

Page 52: ...ingfromEEPROM Reset to 0b 3 4K Boundary Check Enable RO The default value may be changedby SMBus or auto loadingfromEEPROM Reset to 0b 4 FIFOERR_FIX_SEL RO The default value may be changedby SMBus or...

Page 53: ...TION 15 0 PHY TX Margin RO Reset to 116Bh 23 16 Multilane RXEQ RO Upstreamp Port only Reset to 86h Reservedfor DownstreamPorts Reset to 00h 31 24 Reserved RsvdP Not Support 7 2 56 OPERATION MODE OFFSE...

Page 54: ...0 Output Register RW Value of this bit will be output toGPIO 0 pinif GPIO 0 is configuredas an output pin Reset to 0b 3 Reserved RsvdP Not Support 4 GPIO 1 Input RO State of GPIO 1 pin 5 GPIO 1 Outpu...

Page 55: ...output pin Reset to 0b 27 Reserved RsvdP Not Support 28 GPIO 7 Input RO State of GPIO 7 pin 29 GPIO 7 Output Enable RW 0b GPIO 7 is an input pin 1b GPIO 7 is an output pin Reset to 0b 30 GPIO 7 Output...

Page 56: ...this register will containthe datafromthe EEPROM Reset to 0000h 7 2 63 PCI EXPRESS CAPABILITY REGISTER OFFSET C0h BIT FUNCTION TYPE DESCRIPTION 7 0 Enhanced Capabilities ID RO Read as 10h to indicate...

Page 57: ...ddue to the transition from L1 statetothe L0 state ForSwitch the ASPM software wouldnot check this value Reset to 000b 14 12 Reserved RsvdP Not Support 15 Role_BasedError Reporting RO When set indicat...

Page 58: ...op RO When set it permits toset the No Snoop bit in theattribute fieldof transaction Since the Switch cannot either act as a requester oralter the content of packet it forwards this bit always returns...

Page 59: ...lengthoftime this port requires tocomplete transitionfromL0s toL0is in the range of 256ns toless than 512ns The default value maybe changed by SMBus or auto loadingfromEEPROM Reset to 011b 17 15 L1 E...

Page 60: ...eoperatingwith asynchronous reference clock 1b The components at bothends of a link areoperatingwith a distributed commonreference clock Reset to 0b 7 ExtendedSynch RW When set it transmits 4096FTSord...

Page 61: ...by SMBus or auto loadingfrom EEPROM Reset to 0b 2 Reserved RsvdP Not Support 3 AttentionIndicator Present RO When set it indicates that anAttentionIndicatoris implementedon the chassis for this slot T...

Page 62: ...t Reset to 0b 4 Command CompletedInterrupt Enable RW When set it enables the generationof Hot Pluginterrupt when the Hot Plug Controller completes a command Reset to 0b 5 Hot PlugInterrupt Enable RW W...

Page 63: ...is implementedon all Downstream Ports that implement slots For DownstreamPorts not connectedtoslots wherethe Slot Implementedbit of the PCI Express Capabilities register is 0b this bit returns 1b Rese...

Page 64: ...Target Link Speed RWS Reset to 0010b 4 Enter Compliance RWS Reset to 0b 5 HW_AutoSpeed_Dis RW Reset to 0b 6 Select_Deemp RO Reset to 0b Upstream port Reset to 1b Downstream ports 9 7 Tran_Margin RWS...

Page 65: ...tocol Errorevent has occurred Reset to 0b 11 5 Reserved RsvdP Not Support 12 PoisonedTLP Status RW1CS When set indicates that a PoisonedTLP has been receivedor generated Reset to 0b 13 Flow Control Pr...

Page 66: ...15 CompleterAbort Mask RWS When set theCompleterAbort event is not loggedin the HeaderLogregister andnot issuedas an Error Message to RC either Reset to 0b 16 Unexpected CompletionMask RWS When set th...

Page 67: ...set to 1b 19 ECRC Error Severity RWS 0b Non Fatal 1b Fatal Reset to 0 20 Unsupported Request Error Severity RWS 0b Non Fatal 1b Fatal Reset to 0b 21 ACS Violation Severity RWS 0b Non Fatal 1b Fatal Re...

Page 68: ...ot loggedin the Header Logregister andnot issuedas an Error Message toRC either Reset to 0b 11 9 Reserved RsvdP Not Support 12 Replay Timer Timeout Mask RWS When set theReplayTimer Timeout event is no...

Page 69: ...l Channels in addition to thedefault VC supportedby the Switch The default value maybe changedby the status of strappedpin or auto loadingfrom EEPROM Bit 2 1 Reset to00b Bit 0 Reset to the status of V...

Page 70: ...ION 16 VC Arbitration Table Status RO When set it indicates that any entryof theVC ArbitrationTable is written by software This bit is clearedwhen hardware finishes loadingvalues storedin the VC Arbit...

Page 71: ...et to 0b 19 17 Port Arbitration Select RW This fieldis used to configure thePort Arbitrationby selectingone of the supportedPort Arbitration schemes Thepermissible values forthe schemes supportedby Sw...

Page 72: ...n as an offset fromthe base address of the Virtual Channel Capabilityregister in the unit ofDQWD 16 bytes Reset to 08hforPort ArbitrationTable 1 if offset 144h bit 0 1 Reset to 00hif offset 144h bit...

Page 73: ...Phase 11 Phase 10 Phase 9 Phase 8 04h Phase 23 Phase 22 Phase 21 Phase 20 Phase 19 Phase 18 Phase 17 Phase 16 08h Phase 31 Phase 30 Phase 29 Phase 28 Phase 27 Phase 26 Phase 25 Phase 24 0Ch 7 2 102 PO...

Page 74: ...data reportedthrough thedata register When 00h it selects D0 Maxpower budget When 01h it selects D0 Sustainedpower budget Other values wouldreturn zero power budgets which means not supported Reset to...

Page 75: ...nstream Port Only BIT FUNCTION TYPE DESCRIPTION 0 ACS Source Validation RO Indicatedtheimplements ofACSSource Validation Reset to 1b 1 ACS Translation Blocking RO Indicatedtheimplements ofACSTranslati...

Page 76: ...XTENDED CAPABILITY HEADER OFFSET 230h Upstream Port Only BIT FUNCTION TYPE DESCRIPTION 15 0 PCI Express ExtendedCapability ID RO Read as 0018h to indicatePCI Express ExtendedCapabilityID forLTR Extend...

Page 77: ...ev 2 2 www diodes com Diodes Incorporated PI7C9X2G304SL BIT FUNCTION TYPE DESCRIPTION 28 26 Max No Snoop LatencyScale RW This register provides a scale for thevalue containedwithinthe Maximum No Snoop...

Page 78: ...g table When CLKBUF_PD pin is asserted high the clock buffer is in power down mode and disabled The 100MHz Reference Clock Output Pairs are disabled and The PI7C9X2G304SL requires 100MHz differential...

Page 79: ...tion Register Codes Instruction Operation Code binary Register Selected Operation EXTEST 00000 Boundary Scan Drives receives off chip test data SAMPLE 00001 Boundary Scan Samples inputs pre loads outp...

Page 80: ...loading takes place on the rising edge of TCK 9 5 JTAG BOUNDARY SCAN REGISTER ORDER Table 9 3 JTAG Boundary Scan Register Definition Boundary Scan Register Number Pin Name Ball Location Type Tri stat...

Page 81: ...w diodes com Diodes Incorporated PI7C9X2G304SL Boundary Scan Register Number Pin Name Ball Location Type Tri state Control Cell 44 Internal 45 Control 46 Internal 47 CLKBUF_PD 60 Birdir 45 48 Internal...

Page 82: ...ates During the transition from D3 hot to D3 cold state the main power supplies of VDDC and VDDR are turned off to save power while keeping the VDDCAUX and VAUX with the auxiliary power supplies to ma...

Page 83: ...during this stabilization time the REFCLK starts and stabilizes After there has been time 100 ms for the power and clock to become stable PERST is deasserted high and the PCI Express functions can st...

Page 84: ...ayaffect reliability 12 2 DC SPECIFICATIONS Table 12 2 DC Electrical Characteristics Symbol Description Min Typ Max Unit VDDC1 Digital Core Power 0 95 1 0 1 1 V VDDR Digital I O Power 3 0 3 3 3 6 CVDD...

Page 85: ...e Differential Transmitter TX Output 2 5 Gbps Characteristics Parameter Symbol Min Typ Max Unit Unit Interval UI 399 88 400 0 400 12 ps Differential p p TX voltage swing VTX DIFF P P 800 mV ppd Lowpow...

Page 86: ...12 4 OPERATING AMBIENT TEMPERATURE Table 12 7 Operating Ambient Temperature Above which the useful life may be impaired Item Min Max Units Ambient Temperature withpower applied 40 85 o C Note Exposure...

Page 87: ...DS39933 Rev 2 2 www diodes com Diodes Incorporated PI7C9X2G304SL 13 PACKAGE INFORMATION The package of PI7C9X2G304SL is a 14mm x 14mm LQFP 128 Pin package The following are the package information an...

Page 88: ...ted PI7C9X2G304SL 14 ORDERING INFORMATION Part Number Temperature Range Package Pb Free Green PI7C9X2G304SL FDEX 40o to 85o C Industrial Temperature 128 pin LQFP 14mm x 14mm Yes PI 7C 9X2G304SL FD E X...

Page 89: ...Authorized Distributor Click to View Pricing Inventory Delivery Lifecycle Information Diodes Incorporated PI7C9X2G304SLAFDE PI7C9X2G304SLAFDEX PI7C9X2G304SLBFDEX PI7C9X2G304SLBFDE PI7C9X2G304SLBQFDE P...

Reviews:

No comments