Dini Group DN9002K10PCI, User Manual

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H A R D W A R E
7.3.3 PCI Frequency
No hardware changes are required to operate the board at 66 MHz, 33Mhz. You can operate
the PCI bus at DC speeds also. Dini Group has products that can help you with this. Contact
sales@dinigroup.com
7.4 Host Interface, Mechanical
The DN9002K10PCI meets the requirements for a PCI add-in card for the following
dimensions:
- IO placement for USB and Compact Flash.
- 64-bit connector for 3.3V or 5.0V
It fails to meet the PCI requirements for the following dimensions:
- IO placement for daughtercards, jtag headers, SMA connectors -32-bit connector -Component
height, top side -Component height, bottom side -Board height -Board length
Therefore, the acceptability of each of these board dimensions is the users responsibility. In
general, large "ATX" compatible computer cases will fit the DN9002K10PCI, given that there is
no PCI card in the right adjacent slot, and not a "tall" card in the left adjacent slot.
Some cases may prevent the use of the DN9000k10PCI because the card slot guides are PCI
length and not ISA length. Also, the DN9000K10PCI will always physically fit into a 32-bit PCI
connector; however there may be components on the motherboard that prevent the board from
plugging it.
Typically there is at least one slot on a generic motherboard that will accommodate the
DN9002k10PCI.
7.5 Hardware Design Notes
The interface between the FPGA and the QL5064 PCI bridge is described briefly in the
D:\FPGA_Reference_Designs\DN9002K10PCI\PCI_interface\
QL5064_Interface_Module.pdf
It is recommended that users simply implement the QL5064 interface module instead of trying
to directly interface to the QL5064. The interface details are therefore only provided on request.
FPGA A and the “Spartan” configuration FPGA share the Data bus between the FPGA and
the QL5064. This is how configuration of FPGAs over PCI is possible. In order to prevent the
Spartan and FPGA A from interfering with each other, arbitration is necessary. The provided
QL5064_interface_module module takes care of this arbitration for you. However, a
misbehaving design in FPGA A can prevent the DN9002K10PCI to behave properly over PCI.
The timing of the interface between FPGA A, the QL5064 and the Spartan is fully synchronous
to an external, 75 MHz oscillator. This signal, PCLK is only distributed to these three endpoints.
DN9002K10PCI User Guide www.dinigroup.com 88