Dini Group DN9002K10PCI, User Manual

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H A R D W A R E
data that you would like to write to main bus. After the Spartan 3 has received a write to both
the MBADDR and MBWRDATA registers, it will write to the main bus interface.
To read from the Main Bus over PCI, first write to BAR0 address QLPCI_REG_MBADDR
with the 32-bit value representing the main bus address you would like to read from. Then, read
from BAR0, QLPCI_REG_MBRDDATA. The returned value will be the value read off the
main bus at the selected address. When an error has occurred (No FPGA responded to the read
request) the read will return the value 0xABCDABCD.
QLPCI_REG_MBADDR 0x240
QLPCI_REG_MBCTRL 0x244
QLPCI_REG_MBWRDATA
0x248
QLPCI_REG_MBRDDATA 0x250
7.2.4 FPGA Configuration
FPGAs can be configured over PCI. Data from PCI is directed to the SelectMap interface of
the Virtex-4 FPGAs, and in this way, a host can cause the FPGAs to configure.
To send configuration data to an FPGA
•
“Select” an FPGA. Write one 32-bit word to BAR0, address 0x208. The word
represents which FPGA should be “selected”. The data 0x11 represents FPGA A, 0x12
is FPGA B.
•
Reset the selected FPGA. A full-chip reset is recommended before configuring an
FPGA. To reset an FPGA, the configuration circuit asserts the FPGA PROGn signal.
This process clears a device of any configuration it may have.
•
Read the current initialization state of the selected FPGA. If it is ready to configure, it
asserts the INTn signal. To read this signal read BAR0 address 0x208, bit 6.
•
After the INTn signal is detected, the Host should de-assert PROGn (Reset). Write to
BAR0 address 0x208 the data word representing the selected FPGA. 0x11 is FPGA A,
0x12 is FPGA B.
•
The configuration stream for the FPGA is then sent to BAR0, address 0x210, one byte
at a time. Sometime during the configuration stream byte loading process, a startup
sequence is sent to the FPGA and the FPGA becomes operational. This startup
sequence is contained within the bit file.
•
To determine of the selected FPGA is currently configured (i.e. configuration was
successful), read from BAR0 address 0x208. The bit 5 contains the state of the DONE
FPGA pin, the bit 6 contains the state of the FPGA INIT signal.
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