Q U I C K S T A R T G U I D E
From the FPGA Memory menu, select Test DDR. A box will appear and ask which FPGA
should be tested. The log window will report whether the test passed. If it fails, it will print a list
of addresses and data that failed.
If you would like to simulate a failure, you can repeat this guide with the DDR2 module
removed. Other tests that could be performed from the USB Controller (but aren’t part of this
quick-start) are interconnect tests, Ethernet tests, and something else. For information on
running these tests, see the Software chapter.
5.3
Getting data to and from the FPGA
The USB Controller program also allows you to easily configure and transfer data to and from
the user design on the emulation board. This data transfer occurs over the boards “MainBus”.
This interface is described in the Hardware chapter.
Some users may choose not to implement the “MainBus” interface, and use these signals for
general-purpose FPGA interconnect. To allow this, by default the main bus is disabled, and the
Host interface (USB in this case) is prevented from operating it. To override this setting, hit the
“Enable USB->FPGA communication” button near the top of the window.
To read data from the FPGA design (the Dini Group reference design), select from the menu
MainBus->Read
In the resulting dialog box, enter the address 0x080000000 in the address box, and “10” in the
“number of DWORDs” box. Press OK, and then DONE. The result of the read is printed to
the USB Controller log window.
FPGA READ
0x080000000 0x00000000
0x080000001 0x05000135
0x080000002 0xDEAD1234
0x080000004 0x1D000000
…
Figure 7 USB Controller Log Output
The address 0x080000000 is defined by the “MainBus” interface to be mapped within FPGA A
on the DN9002K10PCI. If FPGA A is not loaded with the Dini Group reference design (or a
design that implements the MainBus slave), then all address reads will return 0xDEADDEAD.
6
Communicating over the Serial Port
You may want to communicate with your design over the user serial port (P2). The MainTest
reference design that you already loaded has an asynchronous loop back on this port. If you
want to test this connection, connect an RS232 terminal to the header and type stuff. The port
should echo back that very same stuff.
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